WO2025254357A1 - Data storage device and operating method thereof - Google Patents

Abstract

An operating method of a data storage device, according to one embodiment of the present invention, comprises the steps of: receiving a control signal that instructs either first firmware stored in a first memory unit or second firmware stored in a second memory unit to operate as main firmware; executing the first firmware as the main firmware according to the control signal; updating the second firmware with reference to the first firmware when booting resulting from the execution of the first firmware as the main firmware is successful; executing the second firmware as the main firmware when booting resulting from the execution of the first firmware as the main firmware fails; and updating the first firmware with reference to the second firmware when booting resulting from the execution of the second firmware as the main firmware is successful.

Description

Data storage device and method of operation thereof

The present invention relates to a data storage device and an operating method thereof.

Data storage devices are widely used in various technological fields, including electronics, communications, vehicles, networks, and telematics. In particular, NAND flash memory is an example of a NAND-based data storage device and is a non-volatile memory.

If a power interruption or unstable power supply occurs to NAND flash memory, data within the memory may be corrupted. For example, if a power interruption occurs during a write/erase operation, data may not be saved properly and may become corrupted. Specifically, while some blocks undergoing write/erase operations can be recovered after backup, some blocks may be difficult to recover.

When a power outage occurs in an embedded system containing NAND flash memory, the system may struggle to boot and its reliability may be compromised. Therefore, a method is needed to maintain system reliability and ensure stable booting even during a power outage.

The technical problem to be achieved by the present invention is to provide a data storage device and an operating method thereof that can stably boot without data loss even when power is cut off.

A method of operating a data storage device according to one embodiment of the present invention includes the steps of: receiving a control signal instructing one of first firmware stored in a first memory unit and second firmware stored in a second memory unit to operate as a main firmware; executing the first firmware as the main firmware according to the control signal; if booting is successful as a result of executing the first firmware as the main firmware, updating the second firmware with reference to the first firmware; if booting fails as a result of executing the first firmware as the main firmware, executing the second firmware as the main firmware; and if booting is successful as a result of executing the second firmware as the main firmware, updating the first firmware with reference to the second firmware.

The first memory unit and the second memory unit may be different dies included in one NAND flash memory.

The address range allocated to the first memory section may not overlap with the address range allocated to the second memory section.

When the first firmware operates as the main firmware, booting may be executed from a first boot start address within an address range allocated to the first memory section, and when the second firmware operates as the main firmware, booting may be executed from a second boot start address within an address range allocated to the second memory section.

The address range allocated to the first memory unit may be 0 to 2 ^N -1, and the address range allocated to the second memory unit may be 2 ^N to 2 ^N+1 -1.

The above control signal can be received through at least one GPIO (general purpose input output).

A data storage device according to one embodiment of the present invention includes a first memory unit for storing a first firmware, a second memory unit for storing a second firmware, and a control unit, wherein the control unit is configured to, when receiving a control signal instructing either the first firmware or the second firmware to operate as a main firmware, execute the first firmware as the main firmware according to the control signal, and, if booting is successful as a result of executing the first firmware as the main firmware, update the second firmware with reference to the first firmware, and, if booting fails as a result of executing the first firmware as the main firmware, execute the second firmware as the main firmware, and, if booting is successful as a result of executing the second firmware as the main firmware, update the first firmware with reference to the second firmware.

According to embodiments of the present invention, a data storage device capable of stable booting without data loss even during a power outage and an operating method thereof can be obtained. In particular, according to embodiments of the present invention, it is possible to recover data lost during a power outage without increasing the memory capacity or physical size. Furthermore, according to embodiments of the present invention, backup data can be updated simultaneously with the normal operation of the data storage device.

FIG. 1 is a block diagram of a system including a data storage device according to one embodiment of the present invention.

FIG. 2 is a block diagram of a data storage device according to one embodiment of the present invention.

Figure 3 is a block diagram of a data storage device according to another embodiment of the present invention.

FIG. 4 is a flowchart of an operating method of a data storage device according to one embodiment of the present invention.

FIG. 5 is a flowchart of an operating method of a data storage device according to another embodiment of the present invention.

Figure 6 is a flowchart of an operating method of a data storage device according to another embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and/or at least one (or more) of B, C”, it may include one or more of all combinations that can be combined with A, B, C.

Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it can include the meaning of a downward direction as well as an upward direction based on one component.

Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

FIG. 1 is a block diagram of a system including a data storage device according to one embodiment of the present invention.

Referring to FIG. 1, a system (10) according to one embodiment of the present invention includes a power supply (100) and a data storage device (200).

The power supply (100) may include a conversion unit (110), an input voltage detection unit (120), and a detection signal transmission unit (130). The conversion unit (110) may receive an input voltage corresponding to the main power, and may convert the received input voltage into a voltage required by each component of the data storage device (200) and output the converted voltage. More specifically, the conversion unit (110) may be implemented as a regulator. The regulator may receive an input voltage through an input terminal and output an output voltage through an output terminal. The output voltage of the regulator may be a driving voltage of the data storage device (200). The regulator may stabilize the input voltage and output it, thereby driving a stable driving voltage to the data storage device (200).

The input voltage detection unit (120) can detect the magnitude of the input voltage supplied to the main power source and output a detection signal accordingly. For example, the input voltage detection unit (120) can include a comparator and output a detection signal according to the comparison result between the input voltage and a reference signal. The detection signal transmission unit (130) can transmit the detection signal output from the input voltage detection unit (120) to the data storage device (200). Although not shown, the detection signal transmission unit (130) can include a logic circuit that converts the high voltage of the detection signal into a low voltage that can be received by the control unit (230) of the data storage device (200) and outputs it.

The data storage device (200) can operate using the voltage input from the power supply device (100) as the driving voltage. The data storage device (200) can communicate with the control device (300) and store data transmitted from the control device (300). That is, the data storage device (200) can communicate with the control device (300) and store a control signal received from the control device (300). For example, the data storage device (200) may be placed in a vehicle, and the control device (300) may be a vehicle control device that controls the vehicle, but is not limited thereto. The data storage device (200) according to an embodiment of the present invention may be applied to various technical fields such as electronic devices, communications, vehicles, networks, and telematics, and the control device (300) may be a device that controls a system in which the data storage device (200) according to an embodiment of the present invention is mounted.

A data storage device (200) according to an embodiment of the present invention includes a memory unit (210), a power supply unit (220), and a control unit (230). The control unit (230) controls the memory unit (210) and may be used interchangeably with a central processing unit (CPU). The control unit (230) receives an operation signal from the memory unit (210) and accesses the memory unit (210) based on the operation signal. The operation signal may be, for example, a Ready output signal and a Busy output signal.

According to an embodiment of the present invention, the memory unit (210) may be a nonvolatile memory capable of writing, erasing, and reading data. For example, the memory unit (210) may be a nonvolatile memory capable of electrically writing and erasing and not requiring a refresh function for rewriting data at regular intervals. For example, the memory unit (210) may be a NAND flash memory. The operation signal of the control unit (230) may correspond to the timing of the NAND flash memory constituting the memory unit (210). Here, the timing may be converted into different time periods depending on the operation type of the NAND flash memory. For example, the different time periods depending on the operation type of the NAND flash memory may include a time for loading data from a memory cell to a page register (read operation), a time for loading data from a page register to a memory cell (write operation), a time for erasing memory cells in block units (erase operation), etc.

Alternatively, the memory unit (210) may be a NOR (Not AND Read-Only memory) or an eMMC (embedded multimedia card) memory, and the type of memory is not limited thereto.

The power supply unit (220) of the data storage device (200) is connected to the output terminal of the conversion unit (110) to receive the output voltage of the conversion unit (110), stabilize the received output voltage, and supply a driving voltage to the memory unit (210). The power supply unit (220) may be a PMIC (power management IC) that supplies the driving voltage to the memory unit (210). The PMIC constituting the power supply unit (220) may be a power control module including a discrete power element module for power, a high-voltage power circuit, a low-voltage digital circuit, and high-voltage and low-voltage analog circuits, and may play a role in converting, distributing, charging, and controlling the input voltage input to the data storage device (200) to suit the memory unit (210).

According to an embodiment of the present invention, it is desired to obtain a data storage device capable of stable booting without data loss even in the event of a power outage or power instability.

FIG. 2 is a block diagram of a data storage device according to one embodiment of the present invention, FIG. 3 is a block diagram of a data storage device according to another embodiment of the present invention, and FIG. 4 is a flowchart of an operating method of a data storage device according to one embodiment of the present invention.

Referring to FIGS. 2 and 3, the data storage device (200) includes a memory unit (210), a power supply unit (not shown), and a control unit (230). With respect to the memory unit (210), the power supply unit (not shown), and the control unit (230), duplicate descriptions of the same contents as those described with reference to FIG. 1 will be omitted.

According to an embodiment of the present invention, the control unit (230) of the data storage device (200) includes a bootloader (231). When power is supplied to the data storage device (200), the bootloader (231) is executed, thereby allowing an operating system (OS) to be loaded.

According to an embodiment of the present invention, the memory unit (210) of the data storage device (200) includes a plurality of memory units. For convenience of explanation, the memory unit (210) is illustrated and described in this specification as including a first memory unit (211) and a second memory unit (212), but is not limited thereto, and the memory unit (210) according to an embodiment of the present invention may include two or more plurality of memory units.

As illustrated in FIG. 2, the memory unit (210) according to the embodiment of the present invention includes one NAND flash memory, and one NAND flash memory may include a plurality of dies. That is, in the embodiment of FIG. 2, the first memory unit (211) may be a first die, and the second memory unit (212) may be a second die. A die may be a basic unit for storing data and may be configured as a semiconductor chip. Each die may include a plurality of blocks. Each block is a logical unit for storing data, and although not illustrated, each block may include a plurality of pages. Data erasure may be performed in units of blocks, and data writing may be performed in units of pages. Memory addresses may be assigned in units of pages. Alternatively, in the embodiment of FIG. 2, the first memory unit (211) and the second memory unit (212) may be a first die and a second die included in one NOR memory. Alternatively, in the embodiment of FIG. 2, the first memory unit (211) and the second memory unit (212) may be the first die and the second die included in one eMMC memory.

Alternatively, as illustrated in FIG. 3, the memory unit (210) according to the embodiment of the present invention may include a plurality of NAND flash memories. That is, in the embodiment of FIG. 3, the first memory unit (211) may be used interchangeably with the first NAND flash memory, and the second memory unit (212) may be used interchangeably with the second NAND flash memory. As described above, each NAND flash memory includes a plurality of dies, each die includes a plurality of blocks, each block includes a plurality of pages, and memory addresses may be allocated in units of pages. Alternatively, in the embodiment of FIG. 3, the first memory unit (211) and the second memory unit (212) may be a first NOR memory and a second NOR memory. Alternatively, in the embodiment of FIG. 3, the first memory unit (211) and the second memory unit (212) may be a first eMMC memory and a second eMMC memory.

According to an embodiment of the present invention, a first firmware is stored in a first memory unit (211), a second firmware is stored in a second memory unit (212), and the first firmware stored in the first memory unit (211) and the second firmware stored in the second memory unit (212) contain the same data. Firmware is a program that operates on a specific hardware device and may refer to software that controls and manages the basic operation of the hardware device. Firmware may perform functions such as the operating method of the hardware device, input signal processing, data transmission, booting process, and error detection and correction. Firmware may be updated periodically or aperiodically. For example, new functions may be added to the firmware or the performance of the firmware may be improved through firmware updates. Firmware may be updated periodically or aperiodically through wired communication, wireless communication, or an external storage device of the data storage device (200). Wireless communication may be, for example, FOTA (Firmware Over The Air), and the external storage device may be, for example, a memory stick.

According to an embodiment of the present invention, when the first firmware stored in the first memory unit (211) operates as the main firmware, the second firmware stored in the second memory unit (212) can operate as the backup firmware, and when the second firmware stored in the second memory unit (212) operates as the main firmware, the first firmware stored in the first memory unit (211) can operate as the backup firmware. If the first firmware stored in the first memory unit (211) and the second firmware stored in the second memory unit (212) contain the same data, the main firmware and the backup firmware are not fixed and can be changed depending on the state of the memory unit (210). That is, the first firmware stored in the first memory unit (211) is not fixed as the main firmware, and the second firmware stored in the second memory unit (212) is not fixed as the backup firmware, but depending on the state of the memory unit (210) or the control of the control unit (230), the first firmware stored in the first memory unit (211) may operate as the main firmware, or the second firmware stored in the second memory unit (212) may operate as the main firmware. The first firmware that operated as the main firmware at the first time point may operate as the backup firmware at the second time point, and the second firmware that operated as the backup firmware at the first time point may operate as the main firmware at the second time point.

Referring to FIGS. 2 to 4, when the bootloader (231) within the control unit (230) is executed (S400), the first firmware of the first memory unit (211) is executed as the main firmware (S410). Here, the firmware is software that controls or supports a hardware device, and when the firmware is executed, the system can be booted.

If booting is successful as a result of executing the first firmware of the first memory unit (211) as the main firmware in step S410 (S420), the second firmware stored in the second memory unit (212) is updated (S430). At this time, the second firmware can be updated by referencing the data of the first firmware, which is the main firmware. The second firmware can be updated in the same way as the data of the first firmware, which is the main firmware. Accordingly, the second firmware can serve as a backup firmware.

According to an embodiment of the present invention, the update of step S430 may be performed repeatedly, periodically or aperiodically, after the successful booting of step S420. Accordingly, the first firmware stored in the first memory unit (211) and the second firmware stored in the second memory unit (212) may both contain the same latest data.

Meanwhile, if the first memory unit (211) or the first firmware of the first memory unit (211) is damaged, the booting in step S420 may fail. If the booting in step S420 fails, the second firmware in the second memory unit (212) is executed as the main firmware (S440). If the booting is successful as a result of executing the second firmware in the second memory unit (212) as the main firmware in step S440 (S450), the first firmware stored in the first memory unit (211) is recovered and updated (S460). To this end, the first firmware can be recovered and updated by referring to the data of the second firmware, which is the main firmware. Accordingly, the first firmware can serve as a backup firmware.

According to an embodiment of the present invention, the recovery and update of step S460 may be performed repeatedly, periodically or aperiodically, after the successful booting of step S450. Accordingly, the first firmware stored in the first memory unit (211) and the second firmware stored in the second memory unit (212) may both contain the same latest data.

However, if the booting of step S450 also fails, both the first firmware of the first memory unit (211) and the second firmware of the second memory unit (212) are reported as damaged, and the system may be shut down or a reboot may be attempted (S470).

In this way, if one of the first firmware of the first memory unit (211) and the second firmware of the second memory unit (212) operates as the main firmware, and the other is recovered and updated by referencing the data of the main firmware, even if one of the two memory units is damaged due to a power outage or power instability, booting and recovery are possible through the remaining memory unit, and it is possible to update the backup firmware of the second memory unit (212) without affecting the first memory unit (211) operating as the main firmware. In particular, if the first memory unit (211) and the second memory unit (212) are the first die and the second die included in one NAND flash memory, the effect of using two NAND flash memories can be obtained without adding physical space.

According to an embodiment of the present invention, when the bootloader (231) in the control unit (230) is executed, the first firmware of the first memory unit (211) or the second firmware of the second memory unit (212) is executed as the main firmware. At this time, which firmware among the first firmware of the first memory unit (211) and the second firmware of the second memory unit (212) will operate as the main firmware can be selected by a control signal.

In this specification, the control signal may mean a signal that the control unit (230) instructs the first memory unit (211) or the second memory unit (212) to determine which firmware to operate as the main firmware and which firmware to operate as the backup firmware. Alternatively, the control signal may mean a signal that the selection unit (240), the power supply unit (100), or the control unit (300) in the data storage device (200) instructs the control unit (230) to determine which firmware to operate as the main firmware and which firmware to operate as the backup firmware.

Figure 5 is a flowchart illustrating an operating method of a data storage device according to another embodiment of the present invention. For convenience of explanation, duplicate descriptions of the same content as described with reference to Figures 1 to 4 are omitted.

Referring to FIG. 5, when the bootloader (231) in the control unit (230) is executed (S500), the control unit (230) checks the settings regarding the memory unit in which the firmware to be operated as the main firmware is stored among the first memory unit (211) and the second memory unit (212) (S510). As illustrated in FIGS. 2 and 3, the control unit (230) can receive the settings regarding the memory unit in which the firmware to be operated as the main firmware is stored from the selection unit (240). At this time, the selection unit (240) is connected to the control unit (230) and can store setting information in the memory unit in which the firmware to be operated as the main firmware is stored in the control unit (230). Here, the selection unit (240) may be included in the control unit (230) but may be an external component of the bootloader (231), included in the data storage device (200) but may be an external component of the control unit (230), or may be an external component of the data storage device (200). The setting information stored in the selection unit (240) may not be fixed information. For example, the setting information stored in the selection unit (240) may be changed by the control unit (230) or by an external device (not shown). For example, the selection unit (240) may be a memory stick. The control unit (230) may transmit a control signal to the memory unit (210) for executing the main firmware and updating the backup firmware according to the setting of the selection unit (240).

If it is confirmed as a result of the verification in step S510 that the memory section storing the firmware to be operated as the main firmware is set to the first memory section (211), the first firmware of the first memory section (211) is executed as the main firmware (S520).

If booting is successful as a result of executing the first firmware of the first memory unit (211) as the main firmware in step S520 (S530), the second firmware stored in the second memory unit (212) is updated with reference to the first firmware of the first memory unit (211) (S540).

Meanwhile, if the first memory unit (211) or the first firmware of the first memory unit (211) is damaged, booting may fail in step S530. If the booting in step S530 fails, the control unit (230) modifies the setting of the selection unit (240) regarding the main firmware (S550). That is, the control unit (230) may reset the second firmware stored in the second memory unit (212) to the main firmware. At this time, the control unit (230) may also transmit a control signal to control the selection unit (240) so that the selection unit (240) resets the second firmware stored in the second memory unit (212) to the main firmware. In addition, the control unit (230) may transmit a control signal to the memory unit (210) for executing the main firmware and updating the backup firmware according to the reset.

Thereafter, the second firmware of the second memory unit (212) is executed as the main firmware (S560). If booting is successful as a result of executing the second firmware of the second memory unit (212) as the main firmware in step S560 (S570), the first firmware stored in the first memory unit (211) is recovered and updated by referring to the second firmware stored in the second memory unit (212) (S580).

However, if the booting of step S570 also fails, both the first firmware of the first memory unit (211) and the second firmware of the second memory unit (212) are reported as damaged, and the system may be shut down or a reboot may be attempted (S590).

In this way, if the setting information regarding the memory section where the firmware to be operated as the main firmware is stored is stored in advance in the selection section (240), the control section (230) can quickly execute the main firmware according to the setting information stored in advance in the selection section (240). In particular, if the setting information is reset to a memory section other than the corresponding memory section in the event of a booting failure, it is possible to quickly execute the main firmware according to the pre-stored reset information even at the next boot.

Figure 6 is a flowchart illustrating an operating method of a data storage device according to another embodiment of the present invention. For convenience of explanation, duplicate descriptions of the same content as described with reference to Figures 1 to 5 are omitted.

Referring to FIG. 6, when the bootloader (231) in the control unit (230) is executed (S600), the control unit (230) receives a control signal for the memory unit in which the firmware to be operated as the main firmware is stored among the first memory unit (211) and the second memory unit (212) (S610). Here, the control signal may be an external input signal transmitted through a GPIO (general-purpose input/output). Here, the control signal may be transmitted from the power supply unit (100) illustrated in FIG. 1, from the control device (300) illustrated in FIG. 1, or from other external devices not illustrated in FIG. 1. According to an embodiment of the present invention, a boot start address may be indicated according to the control signal transmitted through the GPIO.

Table 1 is an example of control signals via GPIO, and Table 2 is another example of control signals via GPIO.

Case 1 GPIO 0 Boot start address 1 L Address allocated to the first memory section 2 H Address allocated to the second memory area

Case 1 GPIO 0 GPIO 1 GPIO2 Boot start address 1 L L L 0 2 L L H 2048 3 L H L 4096 4 L H H 8192 5 H L L 10240 6 H L H 12288 7 H H L 14336 8 H H H 16384

Referring to Table 1, when an L signal is input through GPIO 0, booting can start with an address assigned to the first memory unit (211), and when an H signal is input through GPIO, booting can start with an address assigned to the second memory unit (212). That is, when an L signal is input through GPIO 0, the first firmware stored in the first memory unit (211) can be executed as the main firmware, and when an H signal is input through GPIO 0, the second firmware stored in the second memory unit (212) can be executed as the main firmware.

Referring to Table 2, if the memory section (210) includes eight memory sections, for example, eight dies, and a control signal is input through three GPIOs, booting can be started with an address assigned to each memory section according to the “L” and “H” combination of the three GPIOs.

To this end, for the plurality of memory units constituting the memory unit (210), the address ranges allocated to each memory unit may be set so as not to overlap with each other. For example, if the memory unit (210) is a single NAND flash memory, and the first memory unit (211) and the second memory unit (212) are different dies included in the single NAND flash memory, the address ranges allocated to each die may be set so as not to overlap with each other. For example, if the memory unit (210) is composed of a first die that is a first memory unit (211) and a second die that is a second memory unit (212), the address range allocated to the first die that is the first memory unit (211) may be 0 to 2 ^N -1, and the address range allocated to the second die that is the second memory unit (212) may be 2 ^N to 2 ^N+1 -1. Here, N may be a positive integer. For example, if the memory unit (210) is an 8-bit memory and the memory unit (210) is composed of a first die, which is a first memory unit (211), and a second die, which is a second memory unit (212), an address in the range of 0 to 2047 may be assigned to the first die, which is the first memory unit (211), and an address in the range of 2048 to 4095 may be assigned to the second die, which is the second memory unit (212). In this way, if the address ranges assigned to each die are set so as not to overlap each other, the boot start address is determined according to the control signal indicated through the GPIO, and the booting process can be sequentially performed within the corresponding address range from the boot start address. Accordingly, even if some dies are damaged due to a power outage or power instability, the other dies can quickly perform the function of the main firmware and boot.

If it is confirmed that the first firmware stored in the first memory unit (211) is set as the main firmware based on the control signal received by the control unit (230) through the GPIO in step S610, the first firmware of the first memory unit (211) is executed as the main firmware (S620). For example, referring to Table 1, if an L signal is input through GPIO 0, this may mean that the first firmware stored in the first memory unit (211) is set as the main firmware. If the memory unit (210) is an 8-bit memory and is composed of a first die, which is the first memory unit (211), and a second die, which is the second memory unit (212), booting can be performed sequentially from a boot start address of 0 among the address range of 0 to 2047 assigned to the first memory unit (211).

If booting is successful as a result of executing the first firmware of the first memory unit (211) as the main firmware in step S620 (S630), the second firmware stored in the second memory unit (212) is updated with reference to the first firmware stored in the first memory unit (211) (S640).

Meanwhile, if the first memory unit (211) or the first firmware of the first memory unit (211) is damaged, booting may fail in step S630. If the booting in step S630 fails, the control unit (230) again receives a control signal for the memory unit in which the firmware to be operated as the main firmware is stored among the first memory unit (211) and the second memory unit (212) (S650), and the second firmware of the second memory unit (212) is executed as the main firmware (S660). For example, booting may be performed sequentially from the boot start address 2048 among the address range 2048 to 4095 allocated to the second memory unit (212). In another embodiment of the present invention, step S650 may be omitted, and if the booting in step S630 fails, step S660 may be automatically executed. That is, if the booting in step S630 fails, booting may be performed sequentially from the boot start address 2048 among the address range allocated to the second memory unit (212). If booting is successful as a result of executing the second firmware of the second memory unit (212) as the main firmware in step S660 (S670), the first firmware stored in the first memory unit (211) is recovered and updated by referring to the second firmware stored in the second memory unit (212) (S680).

However, if the booting of step S670 also fails, both the first firmware of the first memory unit (211) and the second firmware of the second memory unit (212) are reported as damaged, and the system may be shut down or a reboot may be attempted (S690).

In this way, if the memory section storing the firmware that will operate as the main firmware is not fixed but varies depending on the control signals received via GPIO, even if one of the multiple memory sections is damaged, it is possible to quickly boot using the undamaged memory section and to recover and update the damaged memory section. In particular, if addresses are assigned to each die in non-overlapping sections, each die can operate as either the main firmware or the backup firmware.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims (10)

In the method of operating a data storage device, A step of receiving a control signal instructing one of the first firmware stored in the first memory unit and the second firmware stored in the second memory unit to operate as the main firmware; A step of executing the first firmware as the main firmware according to the above control signal; If booting is successful as a result of executing the first firmware as the main firmware, a step of updating the second firmware by referring to the first firmware; If the booting fails as a result of executing the first firmware as the main firmware, a step of executing the second firmware as the main firmware; and An operating method including a step of updating the first firmware by referencing the second firmware when booting is successful as a result of executing the second firmware as the main firmware. In the first paragraph, An operating method in which the first memory section and the second memory section are different dies included in one NAND flash memory. In the first paragraph, An operating method in which the address range allocated to the first memory section does not overlap with the address range allocated to the second memory section. In the third paragraph, When the above first firmware operates as the main firmware, booting is executed from the first boot start address within the address range allocated to the first memory section, An operating method in which booting is executed from a second boot start address within an address range allocated to the second memory section when the second firmware operates as the main firmware. In the third paragraph, An operating method wherein the address range allocated to the first memory section is 0 to 2 ^N -1, and the address range allocated to the second memory section is 2 ^N to 2 ^N+1 -1. In the first paragraph, An operating method in which the above control signal is received through at least one GPIO (general purpose input output). A first memory section storing the first firmware, A second memory section storing the second firmware, and Including a control unit, The above control unit, When a control signal instructing one of the first firmware and the second firmware to operate as the main firmware is received, the first firmware is executed as the main firmware according to the control signal, If booting is successful as a result of executing the above first firmware as the main firmware, the second firmware is updated with reference to the above first firmware, If booting fails when the above first firmware is executed as the main firmware, the above second firmware is executed as the main firmware. A data storage device set to update the first firmware by referencing the second firmware when booting is successful as a result of executing the second firmware as the main firmware. In paragraph 7, A data storage device in which the first memory section and the second memory section are different dies included in one NAND flash memory. In paragraph 8, A data storage device in which the address range allocated to the first memory section does not overlap with the address range allocated to the second memory section. In paragraph 9, A data storage device in which the address range allocated to the first memory section is 0 to 2 ^N -1, and the address range allocated to the second memory section is 2 ^N to 2 ^N+1 -1.