WO2025201143A1 - Signal processing method and display driver chip - Google Patents

Abstract

The present application provides a signal processing method and a display driver chip, for use in mitigating color separation during grayscale display on a display screen. The method comprises: obtaining grayscales to be displayed; and dividing a frame duration for displaying each grayscale among said grayscales into N time periods, wherein PWM signals corresponding to at least two time periods among the N time periods have effective pulse widths, and N is a positive integer greater than or equal to 2.

Description

Signal processing method and display driver chip

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 28, 2024, with application number 202410372424.4 and application name "A Signal Processing Method and Display Driver Chip", the entire contents of which are incorporated by reference into this application.

Technical Field

The present application relates to the field of display technology, and in particular to a signal processing method and a display driver chip.

Background Art

Grayscale refers to different levels of gray divided between black and white in a certain proportion. It is used to express the brightness levels that can be distinguished from darkest to brightest in black and white images. It is usually represented by binary numbers. For example, 8-bit grayscale can represent 256 different brightness levels from 0 to 255.

Micro-LED (Micro-Light Emitting Diode) displays are an emerging display technology in recent years. Micro-LEDs are current-driven devices. Using analog drive technology to adjust the current flowing through the Micro-LEDs can produce varying brightness levels, enabling grayscale display. As shown in Figure 1, some technical solutions use pulse-width modulation (PWM) signals to drive the Micro-LEDs to display grayscale. When the effective pulse width of the PWM signal is applied to the Micro-LEDs, the current flows through them, causing them to emit light. When the inactive pulse width of the PWM signal is applied to the Micro-LEDs, the current is cut off, causing them to turn off. Within a frame, the duty cycle corresponding to the effective pulse width of the PWM signal represents the grayscale level.

However, when the PWM signal drives the Micro LED display to display grayscale, visual color separation will occur when the user's line of sight moves between different positions of the Micro LED display.

Summary of the Invention

The present application provides a signal processing method and a display driver chip for alleviating the color separation phenomenon that occurs when a display screen displays grayscale.

In a first aspect, an embodiment of the present application provides a signal processing method that can be performed by a signal processing device. The signal processing device can be, for example, a display driver chip or a component in a display driver chip. For ease of description, the method is described by taking a signal processing device performing the method as an example. The method includes: obtaining a grayscale to be displayed; dividing a frame time for displaying each grayscale in the grayscale to be displayed into N time periods; wherein the PWM signal corresponding to at least two of the N time periods has a valid pulse width; and N is a positive integer greater than or equal to 2.

Considering that in the prior art, the PWM signals in a portion of the time periods within a frame time displaying the grayscale to be displayed are all valid pulse widths, while the pulse widths in another portion of the time periods are all invalid pulse widths, resulting in a visual color separation phenomenon when the user's line of sight moves between the display screen positions corresponding to these two time periods. In the embodiment of the present application, by dividing the frame time displaying each grayscale to be displayed into N time periods, the PWM signals corresponding to at least two of the N time periods have valid pulse widths. Thus, the PWM signals in at least two time periods within the frame time displaying the grayscale to be displayed can drive the grayscale display. As a result, when the user's line of sight moves between the display screen drive display positions corresponding to the at least two time periods, the color difference perceived by the user is not significant, thereby effectively alleviating the color separation phenomenon perceived by the user.

In one possible design, the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each of the N time periods is consistent. In this design, by dividing a frame time displaying grayscale into N time periods, the effective pulse width duty cycle of the PWM signal corresponding to each time period is set to be consistent, thereby making the effect of the PWM signal driving the grayscale display consistent in different time periods within the one frame time displaying grayscale, so that the display screen displays the same color in different time periods within the one frame time displaying grayscale. In this way, the color separation phenomenon visually perceived by the user when the user's line of sight moves between different positions of the display screen (for example, the display screen drive display positions corresponding to time period 1 and time period 2 in the N time periods) within the one frame time displaying grayscale can be further alleviated.

In one possible design, the PWM signal corresponding to each of the N time periods includes a first sub-signal and a second sub-signal, wherein the first sub-signal represents an effective pulse width and the second sub-signal represents an invalid pulse width. The first sub-signal is used to drive grayscale display.

In one possible design, the method further includes: generating M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; dividing the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; and obtaining the PWM signal corresponding to each time period according to the first sub-signal and/or the second sub-signal corresponding to each bit width in each time period.

Determining the PWM signal corresponding to each of the N time periods may include, but is not limited to, at least one of the following situations:

Case 1: The M bit widths include a first bit width, and the PWM signal corresponding to the first bit width has a valid pulse width and an invalid pulse width; accordingly, the PWM signal corresponding to each bit width in the M bit widths is divided into N first sub-signals and N second sub-signals, including: averaging or randomly dividing the valid pulse width of the PWM signal corresponding to the first bit width into the N first sub-signals, and averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the first bit width into the N second sub-signals; and obtaining the PWM signal corresponding to each time period according to the first sub-signal and the second sub-signal corresponding to each bit width in each time period, including: splicing the first sub-signal and the second sub-signal corresponding to the first bit width in each time period to obtain the PWM signal corresponding to the first bit width in each time period.

In case 2, the M bit widths include the second bit width, and the PWM signal corresponding to the second bit width has only a valid pulse width; accordingly, the PWM signal corresponding to each bit width in the M bit widths is divided into N first sub-signals, including: averaging or randomly dividing the effective pulse width of the PWM signal corresponding to the second bit width into the N first sub-signals; and obtaining the PWM signal corresponding to each time period based on the first sub-signal corresponding to each bit width in each time period, including: using the first sub-signal corresponding to the second bit width in each time period as the PWM signal corresponding to the second bit width in each time period.

In case 3, the M bit widths include the third bit width, and the PWM signal corresponding to the third bit width has only invalid pulse widths. Accordingly, the PWM signal corresponding to each bit width in the M bit widths is divided into N second sub-signals, including: averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the third bit width into the N second sub-signals; and obtaining the PWM signal corresponding to each time period based on the second sub-signal corresponding to each bit width in each time period, including: using the second sub-signal corresponding to the third bit width in each time period as the PWM signal corresponding to the third bit width in each time period.

Among them, any one of the first bit width, the second bit width, and the third bit width may include one or more bit widths.

In Case 1 to Case 3, multiple ways of splitting the PWM signal are provided, making the splitting of the PWM signal easy to implement.

In one possible design, the method further includes: sequentially splicing the PWM signals corresponding to each time period to obtain a sub-bit-width PWM signal within a frame time; aggregating M sub-bit-width PWM signals within the same time period to obtain a target PWM signal; and the target PWM signal is used to drive each grayscale to be displayed within N time periods.

In one possible design, the M bit widths include at least one of 16 bits, 8 bits, 4 bits, 2 bits, and 1 bit. One bit can only distinguish two grayscales (black and white), two bits can distinguish four grayscales, four bits can distinguish 16 grayscales, and eight bits can distinguish 256 grayscales. 16 bits can distinguish 65,536 grayscales.

In one possible design, the effective pulse width is a high level or a low level. In this design, the effective pulse width of the PWM signal can be set to a high level or a low level, which can achieve flexible driving of grayscale display based on the PWM signal.

In a second aspect, an embodiment of the present application provides a display driver chip, the display driver chip comprising an acquisition module and a processing module; wherein the acquisition module is used to acquire a grayscale to be displayed;

The processing module is used to divide a frame time of displaying each gray scale in the gray scale to be displayed into N time periods; wherein the pulse width modulation (PWM) signals corresponding to at least two time periods in the N time periods have effective pulse widths; and N is a positive integer greater than or equal to 2.

In a possible design, the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each of the N time periods is consistent.

In a possible design, the PWM signal corresponding to each of the N time periods includes a first sub-signal and a second sub-signal, where the first sub-signal represents a valid pulse width, and the second sub-signal represents an invalid pulse width.

In one possible design, the system further includes a PWM signal generating module; wherein the PWM signal generating module is connected to the processing module; the PWM signal generating module is used to generate M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; the processing module is further used to divide the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; and, the first sub-signal and/or the second sub-signal corresponding to each bit width in each time period are spliced to obtain the PWM signal corresponding to each time period.

In one possible design, the M bit widths include a first bit width, and the PWM signal corresponding to the first bit width has a valid pulse width and an invalid pulse width; the processing module divides the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals and N second sub-signals, including: averaging or randomly dividing the valid pulse width of the PWM signal corresponding to the first bit width into N first sub-signals, and averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the first bit width into N second sub-signals; the processing module obtains the PWM signal corresponding to each time period based on the first sub-signal and the second sub-signal corresponding to each bit width in each time period, including: splicing the first sub-signal and the second sub-signal corresponding to the first bit width in each time period to obtain the PWM signal corresponding to the first bit width in each time period.

In one possible design, the M bit widths include a second bit width, and the PWM signal corresponding to the second bit width has only a valid pulse width; the processing module divides the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals, including: averaging or randomly dividing the effective pulse width of the PWM signal corresponding to the second bit width into the N first sub-signals; the processing module obtains the PWM signal corresponding to each time period based on the first sub-signal corresponding to each bit width in each time period, including: using the first sub-signal corresponding to the second bit width in each time period as the PWM signal corresponding to the second bit width in each time period.

In one possible design, the M bit widths include a third bit width, and the PWM signal corresponding to the third bit width has only invalid pulse widths; the processing module divides the PWM signal corresponding to each bit width in the M bit widths into N second sub-signals, including: averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the third bit width into the N second sub-signals; the processing module obtains the PWM signal corresponding to each time period based on the second sub-signal corresponding to each bit width in each time period, including: using the second sub-signal corresponding to the third bit width in each time period as the PWM signal corresponding to the third bit width in each time period.

In one possible design, the processing module is further used to: sequentially splice the PWM signals corresponding to each of the N time periods to obtain a sub-bit-width PWM signal within a frame time; aggregate the M sub-bit-width PWM signals within the same time period to obtain a target PWM signal; and the target PWM signal is used to drive each grayscale to be displayed within the N time periods.

In one possible design, the effective pulse width is a high level or a low level.

In one possible design, the first sub-signal is used to drive grayscale display.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the display driver chip in the second aspect.

In a fourth aspect, an embodiment of the present application provides a signal processing device, comprising a module or unit for implementing any one of the methods described in the first aspect.

In a fifth aspect, an embodiment of the present application provides a signal processing device, comprising: a processor and a memory; the memory is used to store one or more computer programs, and the one or more computer programs include computer execution instructions. When the signal processing device is running, the processor executes the one or more computer programs stored in the memory, so that the signal processing device performs the method as described in any one of the first aspects.

In a sixth aspect, an embodiment of the present application provides a chip system, comprising: a processor and an interface, wherein the processor is configured to call and run an instruction from the interface, and when the processor executes the instruction, implements any one of the methods described in the first aspect.

In a seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store computer programs or instructions, and when the computer-readable storage medium is executed, implements any one of the methods described in the first aspect above.

In an eighth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, implements any one of the methods described in the first aspect above.

Regarding the beneficial effects of any technical solution in the above-mentioned second to eighth aspects, reference can be made to the beneficial effects discussion of the corresponding technical solution in the first aspect, and the repeated parts will not be listed here.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic diagram of PWM driving Micro LED to display grayscale;

FIG2 is a schematic diagram of RGB color display;

FIG3 is a schematic diagram of PWM driving RGB color display;

FIG4A is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

FIG4B is a schematic structural diagram of a display driver chip provided in an embodiment of the present application;

FIG5 is a flow chart of a signal processing method according to an embodiment of the present application;

FIG6 is a second flow chart of a signal processing method provided in an embodiment of the present application;

FIG7A is a schematic diagram of a segmented PWM signal according to an embodiment of the present application;

FIG7B is a second schematic diagram of a segmented PWM signal provided in an embodiment of the present application;

FIG7C is a second schematic diagram of a segmented PWM signal provided in an embodiment of the present application;

FIG8 is a schematic structural diagram of a signal processing device provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of a chip provided in an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application.

To facilitate understanding of the embodiments of the present application, the following explains the terms involved in the embodiments of the present application:

Grayscale is defined in digital imaging or display technology as a measure of the number of distinct brightness levels that an image or display can distinguish, from darkest to brightest. In a grayscale system, brightness is divided into multiple levels, each representing a grayscale, typically ranging from pure black (0% brightness) to pure white (100% brightness). In digital image processing, the specific number of grayscale levels is often associated with color depth. For example, 8-bit color depth can produce 2^8 = 256 different grayscale values, allowing each pixel to vary through 256 grayscale levels, achieving delicate transitions between light and dark. This concept applies not only to black and white images; in color images, the brightness of each pixel (usually composed of red, green, and blue sub-pixels) can also be adjusted using grayscale, ultimately determining the pixel's color representation.

There's a direct correspondence between grayscale and brightness. In digital image processing and display technology, grayscale (also known as color scale or grayscale level) refers to the number of brightness levels that an image or display can distinguish, from the darkest (usually defined as black, with a grayscale value of 0) to the brightest (usually defined as white, with a maximum grayscale value, such as 255, in an 8-bit depth system).

Each grayscale represents a specific brightness level, with higher grayscale values corresponding to greater brightness. For example, in an 8-bit grayscale image, there are 256 grayscales, with grayscale 1 being the lowest brightness, close to black, and grayscale 255 being the highest brightness, close to white. Therefore, the number of grayscales directly affects the level of light and dark detail that an image can present: more grayscales means finer brightness variations and smoother transitions, resulting in more image detail and higher visual quality.

Second, the display driver chip, in the embodiments of this application, can be understood as a chip or integrated circuit used to drive the display screen to display grayscale, and can be considered the "brain" of the display screen. The display driver chip can control the screen brightness and color of the display screen.

The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and appended claims of this application, the singular expressions "a", "an", "said", "above", "the", and "this" are intended to also include expressions such as "one or more", unless the context clearly indicates otherwise.

References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

As shown in Figure 2, Micro LED is a micron-scale LED array technology. In a Micro LED full-color display solution, each pixel is composed of three tiny red (R), green (G), and blue (B) sub-pixels for combined color display. Each sub-pixel can be independently driven and controlled in brightness level (i.e., grayscale). This independent control capability enables Micro LED to achieve full-color display and high dynamic range grayscale display. However, in a solution that uses PWM signals to drive sub-pixel display, if the grayscale of the three R, G, and B sub-pixels attenuates at different ratios, that is, when the user's line of sight moves across the Micro LED display, the grayscale changes corresponding to R, G, and B do not occur at the same ratio, which will cause the synthesized color to be distorted.

As shown in Figure 3, taking the effective pulse width as a high level as an example, the PWM signal corresponding to the R channel is PWM1, and the duty cycle of PWM1's effective pulse width within a frame is 100%; the PWM signal corresponding to the G channel is PWM2, and the duty cycle of PWM2's effective pulse width within a frame is 50%; the PWM signal corresponding to the B channel is PWM3, and the duty cycle of PWM3's effective pulse width within a frame is 25%. Accordingly, the color mixing ratios of R, G, and B within a frame are R = 100%, G = 50%, and B = 25%. However, during the time period 0-t1, the color mixing ratios of R, G, and B are R = 100%, G = 100%, and B = 100%, and the Micro LED display displays color 1. During the time period t1-t2, the color mixing ratios of R, G, and B are R = 100%, G = 33%, and B = 0%, and the Micro LED display displays color 2. Therefore, when the user moves their gaze from display position A to display position B on the Micro LED display, visual color separation occurs.

In view of this, the present application provides a signal processing method and a display driver chip for mitigating color separation when displaying grayscale. This method divides a frame time for displaying each grayscale to be displayed into N time periods, so that the PWM signals corresponding to at least two of the N time periods have valid pulse widths. Furthermore, the PWM signals of at least two time periods within a frame time for displaying the grayscale to be displayed can drive the grayscale display. As a result, when a user's line of sight moves between the display screen drive display positions corresponding to the at least two time periods, the color difference perceived by the user is minimal, thereby effectively mitigating the color separation phenomenon perceived by the user.

The technical solutions provided in the embodiments of the present application are described in detail below with reference to the specific drawings.

FIG4A shows an electronic device provided in an embodiment of the present application, wherein the electronic device 100 includes a signal processing circuit 101 and a display screen 102 .

The signal processing circuit 101 can be any chip or integrated circuit with display driving capabilities. For example, the signal processing circuit 101 can be a display driver chip. In the embodiment of the present application, the signal processing circuit 101 can be provided independently of the display screen 102, or the signal processing circuit 101 can be provided within the display screen 102.

As shown in FIG4B , the signal processing circuit 101 takes a display driver chip as an example. The display driver chip may include an acquisition module 1023, a PWM signal generation module 1021, and a processing module 1022. The PWM signal generation module 1021 is connected to the processing module 1022. The acquisition module 1023 may acquire a grayscale to be displayed. The processing module 1022 may divide a frame time of each grayscale to be displayed into N time periods. The PWM signal corresponding to at least two of the N time periods has a valid pulse width.

The PWM signal corresponding to each time period includes a first sub-signal and a second sub-signal, the first sub-signal representing a valid pulse width, and the second sub-signal representing an invalid pulse width. The PWM signal generation module 1021 can generate M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; the processing module is further used to divide the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; based on the first sub-signal and second sub-signal corresponding to each bit width in each time period, the PWM signal corresponding to each time period is obtained.

In one possible implementation, the signal processing circuit 101 may further include a memory for storing instructions and data. For example, the memory may store grayscales to be displayed, and the signal processing circuit 101 may directly obtain the grayscales to be displayed from the memory when driving the display screen 102 to dynamically display the grayscales to be displayed. This avoids repeated reception from the processor 103, reduces the waiting time of the signal processing circuit 101, thereby improving the efficiency of the system and reducing the power consumption of the electronic device 100. The signal processing circuit 101 can be used to run the code of the signal processing method provided in the embodiment of the present application to achieve grayscale display. The specific process will be described later.

In one embodiment, the electronic device 100 may further include a processor 103, and the signal processing circuit 101 may receive the grayscale to be displayed from the processor 103 and store it in its memory. In this way, when the processor cannot interact directly with the display driver chip, the processor may send the grayscale to be displayed to the display driver chip so that the display driver chip can store the grayscale to be displayed in its memory. Alternatively, the processor 103 may directly send the grayscale to be displayed to the memory of the signal processing circuit 101. In this way, the information exchange between the signal processing circuit 101 and the processor 103 may be reduced, further reducing the power consumption of the electronic device. The processor 103 may be any chip or integrated circuit with computing capabilities. For example, the processor 103 may be an application processor (AP), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), other programmable logic devices, transistor logic devices, or any combination thereof. The general-purpose processor may be a microprocessor, such as a microcontroller unit (MCU), or other conventional processors. The processor 103 may include one or more processing units, and different processing units may be independent devices or integrated into one or more processors. The processor 103 may be the nerve center and command center of the electronic device 100. The processor 103 may generate operation control signals based on instruction operation codes and timing signals to complete the control of instruction fetching and execution. For example, the processor 103 may receive user instructions and determine the display position of the grayscale to be displayed on the display screen 102.

In another case, the signal processing circuit 101 may receive the grayscale to be displayed from a processor of another electronic device and store it in its memory.

The display screen 102 may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, the electronic device 100 may include one or N display screens, where N is a positive integer greater than one.

The electronic device 100 may be a portable electronic device including functions such as a personal digital assistant and/or a music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), etc. Exemplary embodiments of portable electronic devices include but are not limited to devices equipped with Or a portable electronic device with other operating systems. The portable electronic device may also be other portable electronic devices, such as a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present application, the electronic device may not be a portable electronic device, but a desktop computer with a touch-sensitive surface (e.g., a touch panel).

In the embodiments of the present application, the number of nouns, unless otherwise specified, means "singular noun or plural noun", that is, "one or more". "At least one" means one or more, and "plural" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character "/" generally indicates that the previous and next associated objects are in an "or" relationship. For example, A/B means: A or B. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

An embodiment of the present application provides a signal processing method. The method is performed by a signal processing device. The signal processing device may be, for example, the electronic device in FIG. 4A or the display driver chip in FIG. 4B . As shown in FIG. 5 , the signal processing method includes the following steps:

S501: Obtain the grayscale to be displayed.

S502 , dividing a frame time of each gray scale to be displayed into N time periods; wherein at least two time periods in the N time periods correspond to PWM signals having valid pulse widths; and N is a positive integer greater than or equal to 2.

Optionally, the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each of the N time periods is consistent; wherein the PWM signal corresponding to each time period includes a first sub-signal and a second sub-signal, the first sub-signal representing the effective pulse width and the second sub-signal representing the invalid pulse width. The first sub-signal is used to drive grayscale display.

In the embodiment of the present application, the effective pulse width of the PWM signal can be a high level or a low level, so that the manner in which the PWM signal drives the grayscale display can be flexibly set.

In one possible embodiment, the signal processing device can generate M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; the PWM signal corresponding to each bit width in the M bit widths is divided into N first sub-signals and/or N second sub-signals; wherein, the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; and the PWM signal corresponding to each time period is obtained according to the first sub-signal and/or second sub-signal corresponding to each bit width in each time period.

In the embodiment of the present application, the grayscale to be displayed can be three grayscales of the three primary colors RGB, or can be four grayscales of RGBW. The following takes the grayscale to be displayed as three grayscales of RGB as an example to further introduce the signal processing method provided by the embodiment of the present application. As shown in Figure 6, the signal processing method provided by the embodiment of the present application may include:

S601: Obtain three grayscales corresponding to RGB.

In one possible implementation, the signal processing device receives three grayscales corresponding to RGB from an external device. In another possible implementation, the signal processing device may obtain the three grayscales corresponding to RGB from a local memory.

S602: Divide a frame time of each grayscale in the RGB grayscale into N time periods; wherein, the PWM signals corresponding to at least two time periods in the N time periods have valid pulse widths; and N is a positive integer greater than or equal to 2.

Optionally, in a further solution, the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each time period in the N time periods is consistent.

S603 , generating M PWM signals according to each of the three grayscales; wherein each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; and M is a positive integer greater than or equal to 1.

For example, the multiple bits included in the M-bit width may include, but are not limited to, one or more of 16 bits, 8 bits, 4 bits, 2 bits, or 1 bit. Among them, 1 bit can only distinguish two grayscales (black and white), 2 bits can distinguish 4 grayscales, 4 bits can distinguish 16 grayscales, 8 bits can distinguish 256 grayscales, and 16 bits can distinguish 65536 grayscales.

The size of each gray scale is represented by the duty cycle of the effective pulse widths of the M PWM signals in one frame.

S604: Divide the PWM signal corresponding to each bit width in the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals.

S605 : Obtain a PWM signal corresponding to each time period according to the first sub-signal and/or the second sub-signal corresponding to each bit width in each time period.

The specific implementation of S604-S605 may include but is not limited to at least one of the following situations:

In case 1, the M bit widths include a first bit width, and the PWM signal corresponding to the first bit width has a valid pulse width and an invalid pulse width; accordingly, the signal processing device can average or randomly divide the valid pulse width of the PWM signal corresponding to the first bit width into N first sub-signals, and average or randomly divide the invalid pulse width of the PWM signal corresponding to the first bit width into N second sub-signals; and splice the first sub-signals and the second sub-signals corresponding to the first bit width in each time period to obtain the PWM signal corresponding to the first bit width in each time period.

In case 2, the M bit widths include the second bit width, and the PWM signal corresponding to the second bit width has only a valid pulse width; accordingly, the signal processing device can evenly or randomly divide the effective pulse width of the PWM signal corresponding to the second bit width into N first sub-signals; and use the first sub-signal corresponding to the second bit width in each time period as the PWM signal corresponding to the second bit width in each time period.

In case 3, the M bit widths include the third bit width, and the PWM signal corresponding to the third bit width has only invalid pulse widths; accordingly, the signal processing device can evenly or randomly divide the invalid pulse width of the PWM signal corresponding to the third bit width into N second sub-signals; and use the second sub-signal corresponding to the third bit width in each time period as the PWM signal corresponding to the third bit width in each time period.

Among them, any one of the first bit width, the second bit width, and the third bit width may include one or more bit widths.

In Case 1 to Case 3, multiple ways of splitting the PWM signal are provided, making the splitting of the PWM signal easy to implement.

Example 1, N=10, M bit widths include a first bit width, the first bit width includes bit 0, bit 1, bit 2, and bit 3, and bit 0, bit 1, bit 2, and bit 3 all include valid pulse width and invalid pulse width; then the signal processing device divides a frame time of displaying grayscale into 10 time periods; and, the signal processing device divides the valid pulse width in the PWM signal corresponding to bit 0, bit 1, bit 2, and bit 3 into 10 first sub-signals, and divides the invalid pulse width in the PWM signal corresponding to bit 0, bit 1, bit 2, and bit 3 into 10 second sub-signals; further, the signal processing device splices the first sub-signal and the second sub-signal of bit 0, bit 1, bit 2, and bit 3 in each of the 10 time periods to obtain the PWM signal corresponding to each of the 10 time periods.

Example 2, N=10, M bit widths include a first bit width and a second bit width, the first bit width includes bit 0, bit 1, and bit 2, and bits 0, bit 1, and bit 2 all include valid pulse widths and invalid pulse widths; the second bit width includes bit 3, and bit 3 only includes a valid pulse width; then the signal processing device divides a frame time of the grayscale display into 10 time periods; and the signal processing device divides the valid pulse width in the PWM signal corresponding to each of bits 0, bit 1, bit 2, and bit 3 into 10 first sub-signals, and divides the invalid pulse width in the PWM signal corresponding to each of bits 0, bit 1, and bit 2 into 10 second sub-signals; further, the signal processing device splices the first sub-signal and the second sub-signal corresponding to each of bits 0, bit 1, and bit 2 in each of the 10 time periods to obtain a PWM signal corresponding to each of bits 0, bit 1, and bit 2 in these 10 time periods; and uses the first sub-signal corresponding to bit 3 in each of the 10 time periods as the PWM signal corresponding to bit 3 in these 10 time periods.

Example 3, N=10, M bit widths include a first bit width, a second bit width, and a third bit width, the first bit width includes bit 0 and bit 1, bit 0 and bit 1 both include a valid pulse width and an invalid pulse width; the second bit width includes bit 2, bit 2 includes only a valid pulse width; the second bit width includes bit 3, bit 3 includes only an invalid pulse width; the signal processing device divides a frame time of displaying grayscale into 10 time periods; and the signal processing device divides the valid pulse width in the PWM signal corresponding to bit 0, bit 1, and bit 2 into 10 first sub-signals, and divides the invalid pulse width in the PWM signal corresponding to bit 0, bit 1, and bit 3 into 10 first sub-signals. The effective pulse width is divided into 10 second sub-signals; further, the signal processing device splices the first sub-signal and the second sub-signal corresponding to bit 0 and bit 1 in each of the 10 time periods to obtain the PWM signal corresponding to bit 0 and bit 1 in each of the 10 time periods; and uses the first sub-signal corresponding to bit 2 in each of the 10 time periods as the PWM signal corresponding to bit 2 in each of the 10 time periods; and uses the second sub-signal corresponding to bit 3 in each of the 10 time periods as the PWM signal corresponding to bit 3 in each of the 10 time periods.

S606 : sequentially concatenate the PWM signals corresponding to each time period to obtain a sub-bit-width PWM signal within one frame time.

S607 , aggregate the M sub-bit-width PWM signals in the same time period to obtain a target PWM signal; the target PWM signal is used to drive each gray scale to be displayed in N time periods.

The duty cycle of the effective pulse width in the target PWM signal in one frame is the same as the duty cycle of the effective pulse width in the M PWM signals in one frame.

For example, M=4. FIG7A shows that the grayscale of the R channel includes 4 bits with a width of bit 0, bit 1, bit 2, and bit 3. The PWM signals corresponding to bit 0, bit 1, bit 2, and bit 3 are PWM0, PWM1, PWM2, and PWM3, respectively. The combined signal of PWM0, PWM1, PWM2, and PWM3 is PWM4. Taking the effective pulse width of the PWM signal as an example, the duty cycle of the effective pulse width corresponding to PWM0 within a frame time (1/60 second) is 1/15, the duty cycle of the effective pulse width corresponding to PWM1 within a frame time is 2/15, the duty cycle of the effective pulse width corresponding to PWM3 within a frame time is 8/15, and the duty cycle of the effective pulse width corresponding to PWM4 within a frame time is 11/15.

As shown in FIG7B , N=4, the signal processing device divides the grayscale frame time of the R channel into four time periods (i.e., 0-T1, T1-T2, T2-T3, and T3-T4), and divides the effective pulse width and the invalid pulse width of each of PWM0, PWM1, and PWM3 into four sections on average, thereby obtaining four first sub-signals (i.e., effective pulse widths) and four second sub-signals (i.e., invalid pulse widths); and divides the invalid pulse width of PWM2 into four sections on average, thereby obtaining four second sub-signals (i.e., invalid pulse widths); splices the first sub-signal and the second sub-signal corresponding to bit0 in the 0-T1 time period to obtain PWM signal 11; splices the first sub-signal and the second sub-signal corresponding to bit1 in the 0-T1 time period to obtain PWM signal 11; The second sub-signal corresponding to bit2 in the time period 0-T1 is used as PWM13; the first sub-signal and the second sub-signal corresponding to bit3 in the time period 0-T1 are concatenated to obtain PWM signal 14; similarly, the first sub-signal and the second sub-signal corresponding to bit0 in the time period T1-T2 are concatenated to obtain PWM signal 21; the first sub-signal and the second sub-signal corresponding to bit1 in the time period T1-T2 are concatenated to obtain PWM signal 22; the second sub-signal corresponding to bit2 in the time period T1-T2 is used as PWM23; the first sub-signal and the second sub-signal corresponding to bit3 in the time period T1-T2 are concatenated to obtain PWM signal 24;

The first sub-signal and the second sub-signal corresponding to bit0 in the T2-T3 time period are spliced to obtain PWM signal 31; the first sub-signal and the second sub-signal corresponding to bit1 in the T2-T3 time period are spliced to obtain PWM signal 32; the second sub-signal corresponding to bit2 in the T2-T3 time period is used as PWM33; the first sub-signal and the second sub-signal corresponding to bit3 in the T2-T3 time period are spliced to obtain PWM signal 34; the first sub-signal and the second sub-signal corresponding to bit0 in the T3-T4 time period are spliced to obtain PWM signal 41; the first sub-signal and the second sub-signal corresponding to bit1 in the T3-T4 time period are spliced to obtain PWM signal 42; the second sub-signal corresponding to bit2 in the T3-T4 time period is used as PWM43; the first sub-signal and the second sub-signal corresponding to bit3 in the T3-T4 time period are spliced to obtain PWM signal 44;

Among them, in the time periods of 0-T1, T1-T2, T2-T3, and T3-T4, the duty cycle of the effective pulse width corresponding to bit0 is 1/60, the duty cycle of the effective pulse width corresponding to bit1 is 2/60, and the duty cycle of the effective pulse width corresponding to bit3 is 8/60; further, the PWM signals corresponding to bit0 in the four time periods of 0-T1, T1-T2, T2-T3, and T3-T4 (i.e., PWM signal 11, PWM signal 21, PWM signal 31, and PWM signal 41) are spliced together to obtain sub-bit width PWM signals: PWM0-1; the PWM signals corresponding to bit1 in the four time periods of 0-T1, T1-T2, T2-T3, and T3-T4 (i.e., PWM signal 12, PWM signal 22, PWM signal 32, and PWM signal 42) are spliced together , we can respectively obtain sub-bit-width PWM signals: PWM1-1; by splicing together the PWM signals corresponding to bit2 in the four time periods of 0-T1, T1-T2, T2-T3, and T3-T4 (i.e., PWM signal 13, PWM signal 23, PWM signal 33, and PWM signal 43), we can respectively obtain sub-bit-width PWM signals: PWM2-1; by splicing together the PWM signals corresponding to bit3 in the four time periods of 0-T1, T1-T2, T2-T3, and T3-T4 (i.e., PWM signal 14, PWM signal 24, PWM signal 34, and PWM signal 44), we can respectively obtain sub-bit-width PWM signals: PWM3-1; as shown in Figure 7C, PWM0-1, PWM1-1, PWM2-1, and PWM3-1 are aggregated to obtain the target signal PWM4-1. Target signal PWM4-1, relative to signal PWM4 in FIG7A , divides a frame of grayscale display time into four time periods, and the effective pulse width duty cycle of the PWM signal corresponding to each of the four time periods is consistent. Consequently, the PWM signals driving the grayscale display effect in different time periods within a frame of grayscale display time are consistent, resulting in the display screen displaying the same color in different time periods within a frame of grayscale display time. This effectively mitigates the color separation phenomenon perceived by the user when the user's line of sight moves between different positions on the display screen (e.g., position A to position B) within a frame of grayscale display time.

Similarly, the PWM signals corresponding to bit 0, bit 1, bit 2, and bit 3 of the 4-bit G channel are synthesized into PWM5. The same operation can be performed on the PWM signals corresponding to bit 0, bit 1, bit 2, and bit 3 of the 4-bit G channel to obtain the target signal PWM5-1, which can drive the grayscale display corresponding to the G channel. The same operation can be performed on the PWM signals corresponding to bit 0, bit 1, bit 2, and bit 3 of the 4-bit B channel to obtain the target signal PWM6-1, which can drive the grayscale display corresponding to the B channel. In this way, when the RGB combined color is displayed, the PWM signals corresponding to each RGB channel are attenuated proportionally. When the user's line of sight moves to different positions on the Micro LED display, the color separation phenomenon perceived by the user can be effectively reduced.

The present invention provides a signal processing device. Please refer to Figure 8, which is a schematic diagram of the structure of a signal processing device provided in an embodiment of the present invention. The signal processing device 800 can be used to implement the signal processing method described above.

As shown in FIG8 , a signal processing device 800 includes an acquisition module 801 and a processing module 802. The acquisition module 801 and the processing module 802 can be implemented in the form of a processor calling software; for example, the device includes a processor connected to a memory storing instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or functions of each unit of the device. The processor is, for example, a general-purpose processor, such as a central processing unit (CPU) or a microprocessor, and the memory is a memory within the device or a memory outside the device. Alternatively, the acquisition module 801 and the processing module 802 can be implemented in the form of hardware circuits, and the functions of some or all of the units can be realized by designing the hardware circuits. The hardware circuits can be understood as one or more processors. For example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC), and the functions of some or all of the above units are realized by designing the logical relationship between the components in the circuit. For another example, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD). Taking a field programmable gate array (FPGA) as an example, it can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured through a configuration file to realize the functions of some or all of the above units. All units of the above devices can be implemented in the form of software called by the processor, or in the form of hardware circuits, or in part by software called by the processor, and the rest by hardware circuits.

Among them, the acquisition module 801 can be used to obtain the grayscale to be displayed; and the processing module 802 is used to divide a frame time of displaying each grayscale in the grayscale to be displayed into N time periods; wherein, the PWM signal corresponding to at least two time periods in the N time periods has a valid pulse width; N is a positive integer greater than or equal to 2.

Based on the same technical concept, an embodiment of the present application also provides a chip, as shown in FIG9 . The chip 900 includes at least one processor 901 and a communication interface 903. In an optional design, a memory 902 may also be included. In the chip 900, when the processor 901 communicates with other devices, data can be transmitted through the communication interface 903. The processor 901 in FIG9 can call computer-executable instructions stored in the memory 902, so that the chip 900 can execute any of the above-mentioned method embodiments.

In a possible implementation, the processor 901 may be coupled to the memory 902 via a communication interface 903. The embodiment of the present application does not limit the specific connection medium between the processor 901 and the memory 902. For example, the bus 904 may be used.

In another possible implementation, the chip may further directly include a memory 902 in which a computer program or computer instructions are stored. For example, the memory 902 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronized DRAM (SLDRAM), and direct rambus RAM (DR RAM).

In one possible implementation, an embodiment of the present application provides a computer-readable storage medium, which stores program code. When the program code runs on the computer, the computer executes the above method embodiment.

In a possible implementation, an embodiment of the present application provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above method embodiment.

It should be understood that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, a register, a hard disk, a mobile hard disk, a CD-ROM or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a base station or a terminal. Of course, the processor and the storage medium can also exist in a base station or a terminal as discrete components.

In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or nonvolatile storage medium, or may include both volatile and nonvolatile types of storage media.

In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and/or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

It is understood that the various numbers used in the embodiments of this application are merely for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the sequence numbers of the above-mentioned processes does not necessarily imply a specific order of execution; the order of execution of the processes should be determined by their functions and inherent logic.

Claims (24)

A signal processing method, comprising: Get the grayscale to be displayed; A frame time for displaying each grayscale in the grayscale to be displayed is divided into N time periods; wherein the pulse width modulation (PWM) signals corresponding to at least two time periods in the N time periods have effective pulse widths; and N is a positive integer greater than or equal to 2. The method according to claim 1, wherein the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each of the N time periods is consistent. The method according to claim 1 or 2, characterized in that the PWM signal corresponding to each of the N time periods includes a first sub-signal and a second sub-signal, the first sub-signal represents a valid pulse width, and the second sub-signal represents an invalid pulse width. The method according to claim 3, further comprising: Generate M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; dividing the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; A PWM signal corresponding to each time period is obtained according to the first sub-signal and/or the second sub-signal corresponding to each bit width in each time period. The method according to claim 4, wherein the M bit widths include a first bit width, and the PWM signal corresponding to the first bit width has a valid pulse width and an invalid pulse width; Dividing the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals and N second sub-signals, including: averaging or randomly dividing the effective pulse width of the PWM signal corresponding to the first bit width into the N first sub-signals, and averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the first bit width into the N second sub-signals; Obtaining a PWM signal corresponding to each time period according to the first sub-signal and the second sub-signal corresponding to each bit width in each time period, including: splicing the first sub-signal and the second sub-signal corresponding to the first bit width in each time period to obtain a PWM signal corresponding to the first bit width in each time period. The method according to claim 4 or 5, wherein the M bit widths include a second bit width, and the PWM signal corresponding to the second bit width has only a valid pulse width; Dividing the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals includes: averaging or randomly dividing the effective pulse width of the PWM signal corresponding to the second bit width into the N first sub-signals; Obtaining the PWM signal corresponding to each time period according to the first sub-signal corresponding to each bit width in each time period includes: using the first sub-signal corresponding to the second bit width in each time period as the PWM signal corresponding to the second bit width in each time period. The method according to any one of claims 4 to 6, wherein the M bit widths include a third bit width, and the PWM signal corresponding to the third bit width has only an invalid pulse width; Dividing the PWM signal corresponding to each bit width of the M bit widths into N second sub-signals, including: averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the third bit width into the N second sub-signals; Obtaining the PWM signal corresponding to each time period according to the second sub-signal corresponding to each bit width in each time period includes: using the second sub-signal corresponding to the third bit width in each time period as the PWM signal corresponding to the third bit width in each time period. The method according to any one of claims 1 to 7, further comprising: Sequentially splicing the PWM signals corresponding to each of the N time periods to obtain a sub-bit-width PWM signal within one frame time; The M sub-bit-width PWM signals in the same time period are aggregated to obtain a target PWM signal; the target PWM signal is used to drive each gray scale to be displayed in the N time periods. The method according to any one of claims 1 to 8, wherein the effective pulse width is a high level or a low level. The method according to claim 3, wherein the first sub-signal is used to drive a grayscale display. A display driver chip, characterized in that the display driver chip includes an acquisition module and a processing module; The acquisition module is used to acquire the grayscale to be displayed; The processing module is used to divide a frame time of displaying each gray scale in the gray scale to be displayed into N time periods; wherein the pulse width modulation (PWM) signals corresponding to at least two time periods in the N time periods have effective pulse widths; and N is a positive integer greater than or equal to 2. The display driver chip according to claim 11, wherein the effective pulse width duty cycle of the pulse width modulation (PWM) signal corresponding to each of the N time periods is consistent. The display driver chip according to claim 11 or 12, characterized in that the PWM signal corresponding to each of the N time periods includes a first sub-signal and a second sub-signal, the first sub-signal represents a valid pulse width, and the second sub-signal represents an invalid pulse width. The display driver chip according to claim 13, further comprising a PWM signal generating module; wherein the PWM signal generating module is connected to the processing module; The PWM signal generating module is configured to generate M PWM signals according to each grayscale; each grayscale includes M bit widths, and the M bit widths correspond one-to-one to the M PWM signals; M is a positive integer greater than or equal to 1; The processing module is further configured to divide the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals and/or N second sub-signals; wherein the N time periods correspond one-to-one to the N first sub-signals, and the N time periods correspond one-to-one to the N second sub-signals; and, according to each bit width, splice the first sub-signal and/or the second sub-signal corresponding to each time period to obtain the PWM signal corresponding to each time period. The display driver chip according to claim 14, wherein the M bit widths include a first bit width, and the PWM signal corresponding to the first bit width has a valid pulse width and an invalid pulse width; The processing module divides the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals and N second sub-signals, including: averaging or randomly dividing the effective pulse width of the PWM signal corresponding to the first bit width into the N first sub-signals, and averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the first bit width into the N second sub-signals; The processing module obtains the PWM signal corresponding to each time period based on the first sub-signal and the second sub-signal corresponding to each bit width in each time period, including: splicing the first sub-signal and the second sub-signal corresponding to the first bit width in each time period to obtain the PWM signal corresponding to the first bit width in each time period. The display driver chip according to claim 14 or 15, wherein the M bit widths include a second bit width, and the PWM signal corresponding to the second bit width has only a valid pulse width; The processing module divides the PWM signal corresponding to each bit width of the M bit widths into N first sub-signals, including: evenly or randomly dividing the effective pulse width of the PWM signal corresponding to the second bit width into the N first sub-signals; The processing module obtains the PWM signal corresponding to each time period based on the first sub-signal corresponding to each bit width in each time period, including: using the first sub-signal corresponding to the second bit width in each time period as the PWM signal corresponding to the second bit width in each time period. The display driver chip according to any one of claims 14 to 16, wherein the M bit widths include a third bit width, and the PWM signal corresponding to the third bit width has only an invalid pulse width; The processing module divides the PWM signal corresponding to each bit width of the M bit widths into N second sub-signals, including: averaging or randomly dividing the invalid pulse width of the PWM signal corresponding to the third bit width into the N second sub-signals; The processing module obtains the PWM signal corresponding to each time period according to the second sub-signal corresponding to each bit width in each time period, including: using the second sub-signal corresponding to the third bit width in each time period as the PWM signal corresponding to the third bit width in each time period. The display driver chip according to any one of claims 11 to 17, wherein the processing module is further configured to: Sequentially splicing the PWM signals corresponding to each of the N time periods to obtain a sub-bit-width PWM signal within one frame time; The M sub-bit-width PWM signals in the same time period are aggregated to obtain a target PWM signal; the target PWM signal is used to drive each gray scale to be displayed in the N time periods. The display driver chip according to any one of claims 11 to 18, wherein the effective pulse width is a high level or a low level. The display driver chip according to claim 13, wherein the first sub-signal is used to drive grayscale display. A signal processing device, comprising: An acquisition module, used to acquire the grayscale to be displayed; A processing module is used to divide a frame time of displaying each gray scale in the gray scale to be displayed into N time periods; wherein the pulse width modulation (PWM) signals corresponding to at least two time periods in the N time periods have effective pulse widths; and N is a positive integer greater than or equal to 2. An electronic device, characterized in that it includes: a processor and a memory; the memory is used to store one or more computer programs, and the one or more computer programs include computer execution instructions. When the computing device is running, the processor executes the one or more computer programs stored in the memory, so that the computing device performs the method according to any one of claims 1 to 10. A communication device, characterized in that it includes: a processor and a communication interface, the communication interface is used to receive signals from other devices outside the communication device and transmit them to the processor or send signals from the processor to other devices outside the communication device, and the processor executes code instructions through a logic circuit to implement the method described in any one of claims 1 to 10. A computer-readable storage medium, characterized in that a computer program or instruction is stored in the storage medium, and when the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 10 is executed.