WO2025180880A1

WO2025180880A1 - Reference image for distortion correction

Info

Publication number: WO2025180880A1
Application number: PCT/EP2025/054219
Authority: WO
Inventors: Johannes DIETERLE; Thomas Korb; Dmitry Klochkov
Original assignee: Carl Zeiss SMT GmbH
Current assignee: Carl Zeiss SMT GmbH
Priority date: 2024-03-01
Filing date: 2025-02-17
Publication date: 2025-09-04
Anticipated expiration: 2026-09-01
Also published as: TW202543016A

Abstract

The application relates to a method for generating distortion reduced images of a wafer having a periodic semiconductor structure. A reference image of the wafer showing a reference region of the wafer with at least one reference feature representing a part of the periodic semiconductor structure is determined and a plurality of additional images of the wafer are determined, each of the additional images showing the reference region with the at least one reference feature and a milled region obtained by milling a top surface of the wafer, wherein the plurality of additional images differ from one another by a depth of the milled region. A first position of the at least one reference feature is calculated in the reference image, and for each of the additional images, a second position of the at least one reference feature in the additional images is calculated. A transform is determined with which the second positions are matched to the first position and the transform is applied to the additional images in order to obtain the distortion reduced images in the milled region.

Description

REFERENCE IMAGE FOR DISTORTION CORRECTION

TECHNICAL FIELD

The disclosure relates to a method for operating an ion beam device and to the corresponding ion beam device.

BACKGROUND

Semiconductor structures are amongst the finest man-made structures and suffer from different imperfections. Devices for quantitative 3D-metrology, defectdetection or defect review are looking for these imperfections. Fabricated semiconductor structures are based on prior knowledge. The semiconductor structures are manufactured from a sequence of layers being parallel to a substrate. For example, in a logic type sample, metal lines are running parallel in metal layers or HAR (high aspect ratio) structures and metal vias run perpendicular to the layers. The angle between metal lines in different layers is either 0° or 90°. On the other hand, for 3D NAND type structures it is known that their cross-sections are circular on average.

A semiconductor wafer can have a diameter of 300 mm and includes a plurality of several sites, so called dies, each comprising at least one integrated circuit pattern such as for example for a memory chip or for a processor chip. During fabrication, semiconductor wafers run through about 1000 process steps, and within the semiconductor wafer, about 100 and more parallel layers are formed, comprising the transistor layers, the layers of the middle of the line, and the interconnect layers and, in memory devices, a plurality of 3D arrays of memory cells. Dimensions, shapes and placements of the semiconductor structures and patterns are subject to several influences. In manufacturing of 3D-Memory devices, the critical processes are currently etching and deposition. Other involved process steps such as the lithography exposure or implantation also have an impact on the properties of the IC-elements.

The aspect ratio and the number of layers of integrated circuits constantly increases and the structures are growing into 3^rd (vertical) dimension. The current height of the memory stacks is exceeding five microns, in future even up to dozens of microns. In contrast, the features size is becoming smaller. The minimum feature size or critical dimension is below 10nm, for example 7nm or 5nm, and is approaching feature sizes below 3 nm in near future, for 3D NANDS it is 150 nm, for vertical DRAMS around 30 nm. A semiconductor layer has a thickness around 10 nm or less. While the complexity and dimensions of the semiconductor structures are growing into the 3^rd dimension, the lateral dimensions of integrated semiconductor structures are becoming smaller. Therefore, measuring the shape, dimensions and orientation of the features and patterns in 3D and their overlay with high precision becomes challenging.

With the increasing requirement to the resolution of charged particle imaging systems in three dimensions, the inspection and 3D analysis of integrated semiconductor circuits in wafers becomes more and more challenging.

It is possible to obtain a 3D volume information of the wafer based on a single wedge-cut slice image. To this end a single wedge-cut slice image of the sample under investigation as well as a 3D-Tomo data set is required of a reference sample which contains devices fabricated with the same design and manufacturing process. The required information such as a grid parameter can be determined from the corresponding 3D-Tomo data set. This method however strongly depends on the consistency between the two data sets and the accurate determination of the grid parameters. All deviations such as imaging distortions affect the quality of the reconstruction. WO 2021/180600 A1 describes a method for reconstructing an inspection volume based on only two cross section measurements without further knowledge of the grid parameters. Accordingly, a need exists to further improve the correction of distortions in images generated from a wafer.

SUMMARY

This need is met by the features of the independent claims. Further aspects are described by the dependent claims.

According to a first aspect a method for generating distortion reduced images for a wafer is provided, wherein the data has a periodic semiconductor structure where in the method comprises the steps of determining a reference image of the wafer which shows a reference region of the wafer with at least one reference feature representing a part of the periodic semiconductor structure. Furthermore, a plurality of additional images of the wafer are determined wherein each of the additional images shows the reference region with the at least one reference feature and a milled region obtained by milling a top surface of the wafer wherein the plurality of additional images differ from one another by a depth of the milled region. A first position of the at least one reference feature is calculated in the reference image, and for each of the additional images a second position of the at least one reference feature is calculated in the additional images. A transform is determined with which the second positions are matched to the first position and the transform is applied to additional images in order to obtain the distortion reduced images in the milled region.

Furthermore, the corresponding processing device is provided comprising a memory and at least one processing unit, wherein the processing device is configured to carry out the method as discussed above or as discussed in further detail below.

The generation of the additional images of the wafer, especially when the images are used to generate a 3D tomography of the wafer is time-consuming. During this time the apparatus used for generating the images such as a dual beam device using a scanning electron microscope technology can drift. This change or any other change of the imaging apparatus during the generation of the images can be considered and removed with the use of the reference image and the reference features present in the additional image and the reference image. As both the reference image and the additional images include the reference region with the reference feature it is possible to calculate a transform to correct for the difference in distortions between images acquired at different times.

It is to be understood that the features mentioned above and those yet to be explained below may be used not only in the respective combinations indicated, but also in other combinations or in isolation without departing from the scope of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages will be or will become apparent to one with skill in the art upon examination of the following detailed description when read in conjunction with the accompanying drawings in which like reference numerals refer to like elements.

Fig. 1 shows a schematic view of an arrangement of a wafer including a reference region and a milled region which can be used to calculate distortion reduced images of the wafer.

Fig. 2 shows a schematic example of a top view reference image and an additional image including a milled region and reference features.

Fig. 3 shows a schematic view how the images of Fig. 2 with the reference features can be used to find a transform used to obtain distortion reduced images.

Fig. 4 shows a schematic more detailed view of a part of the image as shown in Fig. 3. Fig. 5 shows a schematic view how images taken of the same sample with different orientations can be used to determine a transform used to determine distortion reduced images.

Fig. 6 shows a more detailed view how channels present in the wafer are differently affected by possible distortions.

Fig. 7 shows a schematic more detailed explanation of how the different orientation is used to reduce the distortion influence.

Fig. 8 shows a further example for a different selection of sample orientation for determining distortion reduced images.

Fig. 9 shows a schematic view of a flowchart comprising the steps used for determining distortion reduced images.

Fig.10 shows a schematic view of the dual beam system with which the semiconductor structures of a wafer can be examined.

Fig. 11 shows a schematic view of channels provided in the wafer which can be used as reference features.

Fig. 12 shows a schematic view of a processing device which can determine distortion reduced images using reference features.

DETAILED DESCRIPTION

In the following, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the following description of embodiments is not to be taken in a limiting sense. The scope of the disclosure is not intended to be limited by the embodiments described hereinafter or by the drawings, which are taken to be illustrative only. The drawings are to be regarded as being schematic representations and elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to a person skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. A coupling between components may also be established over a wireless connection. Functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

Some examples of the present disclosure generally provide for a plurality of circuits or other electrical devices. All references to the circuits and other electrical devices and the functionality provided by each are not intended to be limited to encompassing only what is illustrated and described herein. While certain labels may be assigned to the various circuits or other electrical devices disclosed, such labels are not intended to limit the scope of operation for the circuits and the other electrical devices. Such circuits and other electrical devices may be combined with each other and/or separated in any manner based on the type of electrical implementation that is desired. It is recognized that any circuit or other electrical device disclosed herein may include any number of microcontrollers, a graphics processor unit (GPU), integrated circuits, memory devices (e.g., FLASH, random access memory (RAM), read only memory (ROM), electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), or other suitable variants thereof), and software which co-act with one another to perform operation(s) disclosed herein. In addition, any one or more of the electrical devices may be configured to execute a program code that is embodied in a non-transitory computer readable medium programmed to perform any number of the functions as disclosed.

In the following it will be discussed in more detail how the difference in distortion between images of a wafer acquired at different times can be corrected. The generation of the 3D-tomography using a system shown in Fig.10 may take several hours and up to a whole day. During this time the dual beam device can drift.

As will be described below the use of a top view image portion is used to determine the distortions. Based on the top view portions contained in all images a transform to correct for differences in distortions between images acquired at different times can be determined.

With reference to Fig. 10 a system is shown with which a structure of a semiconductor sample 20 can be examined and with which the images of the sample ( a wafer) can be generated that can be used to examine the distortions occurring when the images of wafer are generated . The inspection system 100 is configured for a slice and imaging method under wedge cut geometry with a dual beam device 1 . For a wafer 20, several measurement sites, comprising measurement sites 21 and 22 are defined in a location map or inspection list generated from an inspection tool or from design information. The wafer 20 is placed on a wafer support table 10. The wafer support table 10 is mounted on a stage 90 with actuators and position control. Actuators and means for precision control for a wafer stage such as Laser interferometers are known in the art. A control unit 80 configured to control the wafer stage 90 and to adjust a measurement site 21 of the wafer 20 at the intersection point 43 of the dual-beam device 1. The dual beam device 1 is comprising a FIB generating unit 50 with a FIB optical axis 48 and a charged particle beam (CPB) imaging system 40 with optical axis 42. At the intersection point 43 of both optical axes of FIB and CPB imaging system, the wafer surface is arranged at a slant angle a to the FIB axis 48. FIB axis 48 and CPB imaging system axis 42 include an angle beta, and the CPB imaging system axis forms an angle GE with normal to the wafer surface 55. In the coordinate system of figure 1 , the normal to the wafer surface 24 is given by the z-axis. The focused ion beam (FIB) 51 is generated by the FIB-generating unit 50 and is impinging under angle alpha on the surface 55 of the wafer 20. Slanted cross-section surfaces are milled into the wafer by ion beam milling at the inspection or measurement site 21 under approximately the slant or mill angle alpha (a). In the example of Fig. 10, the incidence angle alpha (a) is approximately 30°. With the charged particle beam imaging system 40, inclined under angle a to the wafer normal, images of the milled surfaces could be acquired. In the example of Figure 2, the angle GE is about 15°. However, other arrangements are possible as well, for example with GE = alpha, such that the CPB imaging system axis 42 is perpendicular to the FIB axis 48, or GE = 0°, such that the CPB imaging system axis 42 is perpendicular to the wafer surface 55.

During imaging, a beam 44 of charged particles is scanned by a scanning unit of the charged particle beam imaging system 40 along a scan path over a crosssection surface of the wafer at measurement site 21 , and secondary particles as well as scattered particles are generated. Particle detector 30 collects at least some of the secondary particles and scattered particles and communicates the particle count with a control unit 60. Other detectors for other kinds of interaction products may be present as well. Control unit 60 is in control of the charged particle beam imaging system 40, of FIB generating unit 50 and connected to a further control unit 80 to control the position of the wafer mounted on the wafer support table via the wafer stage 90. Control unit 60 communicates with operation control unit 70, which triggers placement and alignment for example of measurement site 21 of the wafer 20 at the intersection point 43 via wafer stage movement and triggers repeatedly operations of FIB milling, image acquisition and stage movements.

Each new intersection surface is milled by the FIB beam 51 and could be imaged by the charged particle imaging beam 44, which is for example scanning electron beam or a Helium-lon-beam of a Helium ion microscope (HIM).

Fig. 11 shows a schematic view of the semiconductor sample, the wafer 20 where a region of interest or measurement site 21 is examined to determine whether the desired structure of any semiconductor structure implemented in the wafer 20 is provided or not and especially how the semiconductor structure looks like. In the example shown the measurement site 21 contains several structures 81 , 82 and 83 extending in the thickness direction of the sample wherein the structures can represent channels or other high aspect ratio, HAR structures. It can be assumed that the measurement site 21 contains N different channels.

Fig. 1 shows a schematic view of the measurement site 21 . The measurement site 21 comprises a reference region 25 and a milled region 26. Ideally the reference regions 25A, 25B and 25C frame the entire milled region 26. The purpose of the reference region 25B is to a allow for an unambiguous detection of the relationship between the left 25A and right 25C banks the same measurement is done on an entirely flat area. In this case region 26 is flat.

To correct for different image distortions between images a transform between the reference portions of the image can be determined. To do so features in the reference regions such as the channels shown in Fig. 11 can be detected, by way of example using cross correlation with a template. Corresponding features in the reference regions of the images are identified. This identification is possible as the distortion between the two images is small compared to the spacing of the reference features.

Fig. 2 shows a more detailed view showing a reference image 200 of the top surface of the wafer 20 and the reference image shows the reference features 210 showing the channels of Fig. 11 in a top view. Furthermore, the channels 221-223 are shown which are located in a milled region 220 which will be generated with the ion beam device. The right part of Fig. 2 shows an additional image generated after the milling has started. In the right part of Fig. 2 the additional image also shows the reference features 310 and the channels shown by structures in the milled region 320, the channels 321 , 322 and 323. The reference image 200 and the additional image, the wedge image 300 can be scaled or sheared in a slightly different way. By superposition of the images 200 and 300 the position of the reference features, here of features 210 and 310 can be used to determine a transform which can be used to determine a distortion reduced image as shown in Fig. 3 in the lower part, the distortion reduced image 400. This transform can for example be determined by fitting an affine transform mapping the coordinates of the detected features in region 25 of the reference image to the corresponding ones in region 25 of the image taken from the measurement site 310.

Fig. 4 provides a more detailed view of reference region 25 and the milled region 26. The reference features such as the channel locations located on the top surface of the wafer can be superimposed, as shown in the left part of Fig. 4. By applying the transform based on the features 210 and 310 the position of channels 321 and 322 are transformed to new positions 32T 322’. After this transform the channel can be reconstructed. In order to determine the centroid positions of the reconstructed channel the new positions 32T 322’ are compared to the general positions to 221 and 222. Using the transform, corrected positions of the reference features 210’ and/or 310’ can be calculated and it is possible to determine a corrected position of the channel using the new positions of the channel positions 221’, 222’ and 321 ’ and 322’.

Since the 3D reconstruction based on a single wedge image is sensitive to any small scaling or shearing effect, the present procedure can be used to increase the accuracy of the reconstruction result. The co-pending application

DE 102023115975 A1 discloses the generation of a representative ground truth structure of a channel extending in the thickness direction of the wafer wherein this ground truth structure is used to determine a transformation by which the other channels can be adapted. For the reconstruction calibrated based on a reference single wedge image the single wedge image to be analyzed may be matched on the reference image of the present method. The co-pending application DE 102023115975 describes a method for obtaining measurements of semiconductor structures from a single wedge of an inspection volume. For the reconstruction based on reference coordinates directly extracted from the images as discussed in the co-pending application DE 102023120462 it is important that the relationship between the coordinates in the reference image and in the wedge image is not affected by scaling or shearing issues. For such a reconstruction or any other reconstruction, it is proposed to record reference regions for all images. It is possible to use a top view image as shown in Fig. 2 and the reconstruction of a distortion reduced image can include the following steps: in a first step a top view image such as image 200 including regions 25 used as reference region are recorded or retrieved from a database. Furthermore, the region 26 are present in the image 200 which will be later the milled region including the wedge area as shown in image 300. This image should be acquired once per sample type or a wafer type.

In a second step for each sample site such as the sites 21 and 22 shown in Fig. 10 a wedge-cut is milled and an image containing the region of interest of the wedge as well as the reference region for distortion correction is recorded resulting in image 300. The reference feature 210 and 310, here the channel representations as well as 221-223 and 321-323 are detected in a third step. In the following step the reference regions in the two images are matched and corresponding features in the two sets of images are identified. This may be accomplished by assigning the detections on each image to points in an idealized grid with a suitable defined grid origin. The detections assigned to the same grid points in the same two data sets are then considered as corresponding features.

In a further step, based on the coordinates of the corresponding features, a transform is determined. By way of example an affine transform can be fitted to convert the coordinates of the reference features 310 in image 300, the additional image to the coordinates determined for the reference image 200. This transform can then be applied to all the different additional images generated from the wafer at the different milling stages. A suitable choice of the transform such as an affine transform can also compensate for potential misorientations between the image sets. Here it is possible to detect the channel representations in image 200 and image 300. Then the coordinates of the channel positions such as the center positions can be subtracted from the channel positions determined from the additional image 300. These coordinate differences are then interpreted as the xzy-coordinates of the reconstructed channels. As in small height intervals several data points can exist for the channels the data point within the height intervals can be clustered to create a single channel as disclosed in the co-pending application DE 102023115975 A1.

In summary if the images suffer from different distortions, they can be numerically corrected as they share the same content in the outer frame, the reference regions.

As discussed in connection with Fig. 5 it is possible to remove and reduce distortions by acquiring an image with the wafer 20 having a wedge or milled region 26 using a different orientation of the wafer and the wedge part relative to the imaging system. The information of these images can then be combined in order to determine an averaged transform. As shown in Fig. 5 after a first image is taken with an orientation as shown in the left side of Fig. 5 the sample can be rotated by 180° and another image is acquired. In case a distortion occurs, which results in a shift in the right y-direction shown in Fig. 5 depending on the depth z the two images are affected differently by the distortions.

This will be explained in more detail in connection with Fig. 6. Here a first 3D representation 400 of the wafer is shown with the wedge portion or milled region 26 having a first orientation. The real sample coordinate system as shown by 410 wherein the distorted coordinate system 415 is also shown. The centroid positions of the actual channels are shown by numerals 430 and 431 wherein the distorted centroid positions of the channel are shown by 420 and 421 . The same is shown for the 3D representation with the other orientation of the sample, the data set 500 having the distorted coordinate system 515 and the real coordinate system 510. Here, the distorted centroid positions for the vertical channel are displaced to the right side in the image so that the distorted centroid position 520 or 521 is shifted to the right side in Fig. 6 by a larger extend compared to the real centroid positions 530 and 531 and the situation shown on the upper part of Fig 6 where sample has the other orientation.

This is further summarized in Fig. 7 where the channel positions 541 and 542 are shown for the top surface and the positions 551 and 552 for the wedge position without distortion whereas 561 and 562 indicate the wedge position with distortions. Accordingly, a depth dependent image shift is present as shown in the lower part of Fig. 7 providing an observed shift. When the sample orientation is changed by 180° there is the corresponding top surface position 441 and 442, the wedge position without distortion 451 and 452 and the channel position with distortions 461 and 462. The true shift of the channel in the real sample and the image shift can be calculated as follows:

The difference in the effect of the distortions is directly affecting the reconstruction result for each of the data sets. The change of the channel tilt has an opposite sign for the two data sets. Accordingly, a combination of the two data sets can be used to extract or exclude the effect of the distortion. By way of example the two data sets can be analyzed separately and later the results can be averaged. This leads to a cancellation of the distortion effect. After the reconstruction the image shift leads to an opposite tilt in the two reconstructions, whereas the real channel tile in both cases has the same direction. Thus, by averaging the image shift is removed.

For other distortions a different choice of sample orientations might be used as discussed in connection with Fig. 8. By way of example a distortion leading to changing magnification in a y-direction depending on the z-direction can be detected by two orthogonally oriented image data sets such as data sets 600 and 700 of Fig. 8. If the wedge surface is oriented in the SEM x-direction this leads to a fanning out of the sample x coordinates. Here a 90 degree rotation is considered. The geometry of the sample is not changed so that in both cases the wedge descends in the sample y-direction. Here the ideal coordinates are shown as grid lines in the right part of Fig. 8. The dashed lines show how the SEM distortions affect the coordinates in the measurement. In this case depending on z the y scaling is different while x is not affected. In the top row it is shown that this distortion leads to a curvature in the reconstructed channel in the y coordinate as shown in the right top part by the dashed line. In the bottom row the sample is rotated by 90 degrees. The image distortion is still the same. If one moves along the wedge descend from the top to the bottom, it is found that the distance between features at the same depth increases with depth.

Fig. 9 summarizes some of the steps carried out in the above discussed method in order to determine distortion reduced images.

In step S81 a reference image of the wafer is determined which can be an image of the top surface of the wafer including a reference region such as region 25 showing reference features such as the channel positions. In step S82 several additional images of the wafer are generated. These additional images also show the reference region and a milled region which was obtained by an ion beam hitting the top surface. The different images thus show the milled surface where the amount of the removed surface in the wedge part increases from image to image. These additional images also show the reference region and each of the additional images furthermore includes the milled region 26. In step S83 the first position of at least one reference feature is determined in the reference image and in step S84 the second position is determined for the reference features in the additional images. Based on the first position and the second positions it is possible to determine a transform which matches the positions in the reference regions to one another. After this determination of the transform in step S85 it is possible to apply the transform in step S86 to the additional images in order to obtain the distortion reduced images of the of the wafer and the milled region.

Fig. 12 shows a schematic architectural view of a processing device 1000 which can carry out the above discussed calculation of the transform and the application to further images. The device 1000 could be implemented in any of the entities shown in Fig. 10 such as the units or entities 60, 70 or 80, but may also be implemented as a stand alone unit. The processing device 1000 comprises an interface 1100 which is provided for transmitting data and for receiving data such as the reception of the images and the transmission of images, if necessary after application of the transform, i.e. the corrected images. The device 1000 comprises a processing unit 1200 responsible for the operation of the processing device 1000. The processing unit one 1200 comprises one or more processors and can carry out instructions stored on a memory 1300 wherein the memory may include a read-only memory, a random access memory, a mass storage, a hard disk or the like. The memory can include suitable program code to be executed by the processing unit 1200 so as to implement the above-described functionalities in which the processing device is involved. The processing device can be implemented in a single node or may be distributed over several nodes or entities in a cloud implementation.

From the above discussion several conclusions can be drawn.

The additional images might be used for a 3D tomography of the wafer and the periodic semiconductor structures can include channels extending in the wafer in the thickness direction substantially perpendicular to the surface of the wafer wherein a distortion reduced 3D tomography is determined based on the transform and wherein the distortion reduced 3D tomography is used to determine the position of the channels in the wafer.

The reference regions may be located on an upper top surface of the wafer located outside the milled region and the at least one reference feature can include representations of the channels.

Furthermore, it is possible to match a grid of the channels present in the reference region of the reference image to a grid of the channels present in the reference region of the additional images to determine the transform.

The reference image and the additional images can be generated with a dual beam device and with a scanning electron microscope technology.

The reference image and the additional images can each show at least four reference features and the at least four reference features can be distributed over the reference and the additional images such that a minimum distance between two of the reference features being located at a maximum distance relative to one another is larger than half of a diagonal of the additional images. In other words, this means that the reference features are distributed over the image so that a position dependent distortion can be determined over the complete image.

Furthermore the at least four reference features may be distributed over the reference and the additional images such that the reference features are located on both sides of the milled region.

The transform may be used to correct distortions such as an image scale, keystone distortions, shearing or anamorphoses.

Furthermore, it is possible that at least some or at least two of the additional images are generated with a different orientation of the wafer and a first distortion is determined using one of the additional images and the reference image wherein the wafer has a first orientation and the second distortion is determined using another or further of the additional images and the reference image with the wafer having another orientation different from the first orientation. An averaged transform may then be calculated based on the first and second distortion wherein the distortion reduced images are generated based on the averaged transform. This was discussed above in connection with Figures 6-8.

The orientation between the different images can differ from one another by 180° or by 90°.

Summarizing with the use of the reference images having either the same orientation or even using wafers having different orientations the imaging distortions can be extracted and can be removed so that an improved calculation of the channel positions is possible.

Claims

1. A method for generating distortion reduced images of a wafer having a periodic semiconductor structure, the method comprising at a processing device:

- determining a reference image of the wafer, the reference image showing a reference region of the wafer with at least one reference feature representing a part of the periodic semiconductor structure,

- determining a plurality of additional images of the wafer, each of the additional images showing the reference region with the at least one reference feature and a milled region obtained by milling a top surface of the wafer, wherein the plurality of additional images differ from one another by a depth of the milled region,

- calculating a first position of the at least one reference feature in the reference image,

- calculating, for each of the additional images, a second position of the at least one reference feature in the additional images,

- determining a transform with which the second positions are matched to the first position,

- applying the transform to the additional images in order to obtain the distortion reduced images in the milled region.

2. Thet method of claim 1 , wherein the additional images are used for a 3 D tomography of the wafer and the periodic semiconductor structure includes channels extending in the wafer in a thickness direction substantially perpendicular to a surface of the wafer, the method further comprising :

- determining a distortion reduced 3D tomography based on the transform,

- using the distortion reduced 3D tomography to determine a position of the channels in the wafer.

3. The method of claim 1 or 2, wherein the reference region is located on an upper top surface of the wafer located outside the milled region.

4. The method of claim 2 or 3, wherein the at least one reference feature includes representations of the channels.

5. The method of any of claims 2 to 4, wherein a grid of the channels present in the reference region of the reference image is matched to a grid of the channels present in the reference region of the additional images to determine the transform.

6. The method of any preceding claim, wherein at least 2 of the additional images are generated with a different orientation of the wafer, wherein a first distortion is determined using one of the additional images and the reference image with the wafer having a first orientation, and a second distortion is determined using a further of the additional images and the reference image with the wafer having a second orientation different from the first orientation, wherein an averaged transform is calculated based on the first and second distortion, wherein the distortion reduced images are generated based on the averaged transform.

7. The method of claim 6, wherein the first orientation of the wafer differs from the second orientation by a 180 degree rotation around an axis extending perpendicular to the reference region.

8. The method of claim 6, wherein the first orientation of the wafer differs from the second orientation by a 90 degree rotation around an axis extending perpendicular to the reference region.

9. The method of any preceding claim, wherein at least the additional images were generated with a dual beam device and with a scanning electron microscope technology .

10. The method of any preceding claim, wherein the reference image and the additional images each show at least 4 reference features, wherein the at least 4 reference features are distributed over the reference and the additional images such that a minimum distance between 2 reference features being located at maximum distance relative to one another is larger half of a diagonal of the additional images.

11. The method of any preceding claim, wherein the reference image and the additional image each show at least 4 reference features, wherein the at least 4 reference features are distributed over the reference and the additional images such that the reference features are located on both sides of the milled region.

12. The method of any preceding claims, wherein the transform is used to correct at least one of the following in the distortion reduced images:

- an image scale,

- keystone distortions,

- shearing,

- anamorphosis.

13. A processing device (1000) comprising a memory (1300) and at least one processing unit (1200), the memory comprising instructions, executable by the processing unit, wherein the instructions, when executed by the at least one processing unit cause the processing device to:

- determine a reference image of the wafer, the reference image showing a reference region of the wafer with at least one reference feature representing a part of the periodic semiconductor structure,

- determine a plurality of additional images of the wafer, each of the additional images showing the reference region with the at least one reference feature and a milled region obtained by milling a top surface of the wafer, wherein the plurality of additional images differ from one another by a depth of the milled region,

- calculate a first position of the at least one reference feature in the reference image,

- calculate, for each of the additional images, a second position of the at least one reference feature in the additional images,

- determine a transform with which the second positions are matched to the first position,

- apply the transform to the additional images in order to obtain the distortion reduced images in the milled region.

14. The processing device of claim 13, wherein the instructions, when executed by the at least one processing unit cause the processing device to carry out a method as mentioned in any of claims 1 to 12.