WO2025123629A1 - Power control method and apparatus, repeater, and storage medium - Google Patents

Abstract

The present invention relates to a power control method and apparatus, a repeater, and a storage medium. The method comprises: acquiring a gain control parameter for performing automatic gain control on a baseband signal; identifying a target time slot type corresponding to the baseband signal; on the basis of the target time slot type, determining a power statistical duration corresponding to the target time slot type; acquiring a power statistical value of the baseband signal within the power statistical duration; and performing power control on the signal on the basis of the power statistical value and the gain control parameter.

Description

Power control method, device, repeater and storage medium

This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on December 13, 2023, with application number 202311723076.2 and titled “Power Control Method, Device, Repeater and Storage Medium,” the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to a power control method, device, repeater and storage medium.

Background Art

P25 is the abbreviation of Project 25, which was developed and promoted by the Association of Public Safety Communications Officials (APCO), the National Association of State Telecommunications Directors (NASTD), federal government users and the Telecommunications Industry Association (TIA) for all radio operators to follow.

P25 signals are mainly used in private network communications. At present, there are two main modulation technologies for P25 signals, one is frequency division multiple access (FDMA) technology, and the other is time division multiple access (TDMA) technology. Due to the influence of communication environment and distance, there are differences in the signal power received and transmitted between different communication devices, so power control methods are needed to stabilize the output power and received power.

However, the power control of multi-standard P25 communication systems with coexistence of FDMA and TDMA is not perfect. Traditional power control schemes generally perform power control on signals of one standard and cannot adapt to P25 signals of different standards, thus affecting the demodulation of signals in multi-standard P25 communication systems and the output power of devices.

Summary of the invention

In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a power control method, device, repeater and storage medium.

A power control method, comprising:

Obtaining gain control parameters for automatic gain control of a baseband signal;

Identifying a target timeslot type corresponding to the baseband signal;

According to the target time slot type, determining a power statistics duration corresponding to the target time slot type;

Obtaining a power statistical value of the baseband signal during the power statistical time period;

Power control is performed on the signal based on the power statistics and the gain control parameter.

A power control device, comprising:

A parameter acquisition module, used to acquire gain control parameters for automatic gain control of a baseband signal;

A time slot identification module, used to identify the target time slot type corresponding to the baseband signal;

A duration determination module, configured to determine, according to the target time slot type, a power statistics duration corresponding to the target time slot type;

A power acquisition module, used to obtain the power statistical value of the baseband signal during the power statistical time length;

A power control module is used to perform power control on the signal based on the power statistics and the gain control parameter.

A repeater station includes a processor and a memory; the processor calls a program or instruction stored in the memory, so that the processor implements the steps of the power control method provided in any embodiment of the present disclosure.

A computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the processor implements the steps of a power control method provided in any one of the embodiments of the present disclosure.

A computer program product includes computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the processor implements the steps of the power control method provided in any one embodiment of the present disclosure.

The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic flow chart of a power control method according to one or more embodiments;

FIG2 is a schematic diagram of a time slot signal frame format according to one or more exemplary embodiments;

FIG3 is a schematic flow chart of a power control method according to one or more embodiments;

FIG4 is a schematic flow chart of a power control method according to one or more embodiments;

FIG5 is a principle block diagram of a power control method for implementing the present disclosure according to one or more exemplary embodiments;

FIG6 is a schematic diagram of a specific structure of a power control module according to one or more exemplary embodiments;

FIG7 is a schematic flow chart of a power control method according to one or more embodiments;

FIG8 is a schematic diagram of a process for identifying a time slot of a signal according to one or more exemplary embodiments;

FIG9 is a schematic diagram of a process of power control performed by a power control module according to one or more exemplary embodiments;

FIG10 is a schematic structural diagram of a power control device according to one or more embodiments.

DETAILED DESCRIPTION

In view of the fact that general power control methods cannot fully adapt to the multi-standard P25 communication system where FDMA and TDMA coexist, and P25 signals of different standards cannot stably output and receive power, affecting the demodulation of P25 signals and the dynamic range of device power output, the present disclosure provides a power control scheme to solve the problem that when power controlling multi-standard P25 signals, the signal's error vector amplitude (EVM) is poor, resulting in the signal being unable to be demodulated; in addition, the two signal modulation technologies of P25 signals are single-slot signals when using FDMA signal modulation technology, and dual-slot signals (including 2 slots, 4 slots, etc.) when using TDMA signal modulation technology. In addition, interference is also involved. Noise floor, etc., that is, in a multi-standard P25 system, the power control method must adapt to the interference noise floor, single-time slot signals and dual-time slot signals at the same time to solve the problem that the power difference between time slots of multi-time slot signals is large, resulting in a reduction in the dynamic range of the output power of the equipment. In the scheme disclosed in the present invention, the multi-standard P25 signal in which FDMA and TDMA coexist is converted into a P25 signal divided into a single-time slot signal and a multi-time slot signal. This scheme controls the power output of single-time slot signals and multi-time slot signals by identifying the time slot type of the P25 signal and selecting power control schemes with different power statistical durations. Power control can be quickly achieved for signals in different time slots without affecting signal demodulation.

The scheme disclosed in the present invention is not limited to power control between time slots, but can also be applied to power control between multiple carriers to eliminate the influence of near-far effect between carriers. For situations where the power difference between different time slots or different carriers is large, the scheme can achieve rapid attenuation of high-power time slot signals and rapid amplification of low-power time slot signals through power control, and finally output signals stably according to the set power, with fast attenuation speed and low bit error rate, thereby solving the problem of reduced dynamic range of device power output due to excessive attenuation of low-power signals when the power difference between different time slots or multiple carriers of multi-time slot signals is large, and reducing the influence of near-far effect between users.

The following uses the most commonly used single-slot signal and dual-slot signal in the multi-standard P25 signal as an example, and describes in detail the implementation of the embodiment of the present disclosure in conjunction with the accompanying drawings.

FIG1 is a flow chart of a power control method provided according to one or more embodiments. The method can be executed by a power control device provided by an embodiment of the present disclosure. The power control device can be implemented by software and/or hardware and can be integrated in an electronic device. The electronic device can be, for example, a repeater that receives signals of multiple formats. The signal received by the repeater can be a single-time slot signal or a dual-time slot signal. The present disclosure is explained below by taking the application of the power control method of the present disclosure to a repeater as an example.

As shown in FIG1 , the power control method may include the following steps:

Step 101: Obtain a gain control parameter for performing automatic gain control on a baseband signal.

The baseband signal may be a digital signal obtained by performing analog-to-digital conversion on a received analog signal.

Exemplarily, when the repeater receives an analog signal from another device, the analog signal can be converted into a digital signal. For example, the analog signal can be converted into a digital signal by an analog-to-digital conversion module of the repeater. Then, the digital signal can be automatically gain controlled by an automatic gain control (AGC) module, and the gain control parameter sent by the AGC module can be obtained.

Step 102: Identify the target time slot type corresponding to the baseband signal.

In the disclosed embodiment, after the baseband signal is obtained through analog-to-digital conversion, time slot identification may be performed on the baseband signal to determine the target time slot type corresponding to the baseband signal.

Taking the multi-standard P25 signal as an example, the P25 dual-time slot signal adopts TDMA technology, which divides time into periodic frames and then divides each frame into two time slots. For example, it can be a signal using two time slots (Dual Slot), or a signal using four time slots (Quad Slot), or a signal using other time slots. As long as it adopts TDMA technology, it can be determined as a dual-time slot type; the time slot signal frame format is shown in Figure 2, each The frame length is 60ms, and each frame is divided into two time slots, each time slot is 30ms. The two time slots can accommodate two users to communicate at the same time without affecting each other. A single time slot signal is a signal that only transmits one user within 60ms. In the disclosed embodiment, the baseband signal is first time slot identified to identify whether the baseband signal is a single time slot or a dual time slot.

As an example, when performing time slot identification, the difference between the maximum power value and the minimum power value of the digital baseband signal of a certain duration can be counted, and the difference can be compared with a preset power threshold. If the difference is less than the power threshold, the target time slot type of the signal is determined to be a single time slot, otherwise the target time slot type of the signal is determined to be a dual time slot.

In an optional implementation of the present disclosure, before performing time slot identification on a signal, the signal may be first down-converted to baseband 0 frequency, down-sampled, and filtered, and then the processed signal may be subjected to time slot identification.

Step 103: Determine the power statistics duration corresponding to the target time slot type according to the target time slot type.

In the embodiment of the present disclosure, after the target time slot type corresponding to the signal is determined, the power statistics duration corresponding to the target time slot type can be determined according to the target time slot type.

Exemplarily, different power statistics durations can be set in advance for different time slot types, for example, the power statistics duration of a single time slot is set longer than that of a double time slot, and then the corresponding power statistics duration is determined based on whether the target time slot type is a single time slot or a double time slot.

Step 104: Obtain a power statistical value of the baseband signal during a power statistical duration.

In the embodiment of the present disclosure, after the power statistics duration corresponding to the target time slot type is determined, power statistics can be performed based on the power statistics duration to obtain a power statistics value.

Exemplarily, the duration parameter of an automatic level control (ALC) circuit may be set based on a determined power statistics duration, so that the ALC circuit performs power statistics based on the power statistics duration to obtain a power statistics value, and then the power statistics value is acquired from the ALC circuit.

Step 105: Perform power control on the signal based on the power statistics and the gain control parameter.

In the embodiment of the present disclosure, after the power statistics are obtained, power control of the signal can be performed based on the power statistics and the obtained gain control parameters.

As an example, if the power statistic obtained is less than the preset power threshold value, the signal can be power controlled according to the preset coefficient, and the preset coefficient is multiplied by the signal to obtain the power-controlled signal and output to the subsequent module for processing. If the power statistic obtained is not less than the preset power threshold value, the current coefficient (initialized as the preset coefficient) and the current power value (initialized as the power statistic) can be updated according to the preset coefficient adjustment step and power adjustment step on the basis of the preset coefficient and the power statistic, respectively, until the current power value is less than the preset power threshold value, the current coefficient is no longer updated, and the gain control parameter is added to the coefficient address corresponding to the preset coefficient to obtain a new coefficient address, and the new coefficient corresponding to the new coefficient address is determined, and the signal is power controlled according to the smaller value of the new coefficient and the current coefficient. The above control process is only an example, and other power adjustment methods can also be used. The control strategy performs power control on the signal, which will be described in detail in subsequent embodiments.

In an optional implementation of the present disclosure, corresponding to at least one of down-converting the signal to baseband 0 frequency, down-sampling and filtering in the aforementioned optional implementation, in this implementation, after the signal is power controlled, the power-controlled signal may be up-sampled, up-converted, and the processed signal may be converted into an analog signal and sent to subsequent modules for processing.

The power control method of the embodiment of the present disclosure obtains the gain control parameter for automatic gain control of the baseband signal, identifies the target time slot type corresponding to the baseband signal, and then determines the power statistics duration corresponding to the target time slot type according to the target time slot type, then obtains the power statistics value of the baseband signal in the power statistics duration, and finally performs power control on the signal based on the power statistics value and the gain control parameter. The scheme of the present disclosure is adopted, by identifying the time slot type of the received signal, determining different power statistics durations according to different time slot types, and then performing subsequent power control, so that different power control schemes are selected for different time slot types for power control, and power control can be quickly achieved for signals of different time slot types without affecting the demodulation of the signal, and can be compatible with power control of different P25 standards at the same time, and the gain control parameter for automatic gain control of the signal is obtained to participate in the power control, so as to achieve the effect of attenuating large signals and amplifying small signals, and solve the problem that when the power difference of different signals is large, the attenuation of small power signals is too large and affects the power output dynamic range of the device.

In an optional implementation of the present disclosure, as shown in FIG3 , based on the embodiment shown in FIG1 , step 102 may include the following sub-steps:

Step 200: preset a noise floor address threshold and a power address threshold of a baseband signal.

In the embodiments of the present disclosure, the noise floor address threshold and the power address threshold of the baseband signal can be set according to actual needs, and the present disclosure does not limit their specific values.

Step 201, obtaining the power value of the baseband signal counted a preset number of times within a preset time period.

The preset duration and the preset number of times can be set according to actual needs. For example, the preset duration can be set to 5 ms (milliseconds) and the preset number of times can be set to 13 times.

Exemplarily, assuming that the preset duration is 5 ms and the preset number of times is 13, the power value statistics of the 5 ms digital baseband signal may be performed 13 times in total to obtain 13 power values.

Step 202: Find the power address corresponding to each power value.

Exemplarily, the power address corresponding to each power value can be found based on a preset power table, wherein the power table records the correspondence between different power addresses and power values, the power address is equivalent to the number of the corresponding power value, and one power value corresponds to a unique power address.

In the embodiment of the present disclosure, after obtaining multiple power values, a power table may be queried to determine a power address corresponding to each of the multiple power values obtained by statistics, thereby obtaining multiple power addresses.

Exemplarily, assuming that 13 power values are obtained by statistics, 13 power addresses can be determined by querying the power table and comparing the 13 power values with the power values in the power table.

Step 203: determine the address difference between the maximum power address and the minimum power address in the power addresses.

In the embodiment of the present disclosure, after a plurality of power addresses are determined, a maximum power address and a minimum power address may be determined from the plurality of power addresses, and a difference between the maximum power address and the minimum power address may be calculated to obtain an address difference.

Step 204, determining whether the power address is greater than the background noise address threshold.

In the embodiment of the present disclosure, after determining the power addresses corresponding to each power value, each power address can be compared with the background noise address threshold. If each determined power address is greater than the background noise address threshold, step 205 or step 206 is executed to determine the target time slot type of the baseband information based on the relationship between the address difference and the power address threshold. If at least one power address is not greater than the background noise address threshold, it is determined that the power address is not greater than the background noise address threshold, and step 207 is executed.

Step 205: In response to the address difference being greater than the power address threshold, determining that the target time slot type of the baseband signal is a dual time slot; wherein the target time slot type includes a dual time slot and a non-dual time slot.

Step 206: In response to the address difference being not greater than the power address threshold, determine that the target time slot type of the baseband signal is a non-double time slot; wherein the non-double time slot includes a single time slot and a background noise.

In the embodiment of the present disclosure, when each power address is greater than the background noise address threshold, it is further determined whether the address difference is greater than the power address threshold. If the address difference is greater than the power threshold address, the target time slot type of the baseband signal is determined to be a dual time slot; if the address difference is not greater than the power address threshold, the target time slot type of the baseband signal is determined to be a non-dual time slot, more specifically, the target time slot type of the baseband signal is determined to be a single time slot in a non-dual time slot.

Step 207, determining that the target time slot type corresponding to the baseband signal is a non-dual time slot; wherein the non-dual time slot includes a single time slot and a noise floor. In the disclosed embodiment, when the power address is not greater than the noise floor address threshold, the target time slot type corresponding to the baseband signal is determined to be a non-dual time slot, and more specifically, the target time slot type of the baseband signal is determined to be a noise floor in a non-dual time slot.

The power control method of the embodiment of the present disclosure presets the noise floor address threshold and the power address threshold of the baseband signal, obtains the power value of the baseband signal counted a preset number of times within a preset time length, searches for the power address corresponding to each power value, and determines the address difference between the maximum power address and the minimum power address in the power address. When the power address is greater than the noise floor address threshold, if the address difference is greater than the power address threshold, the target time slot type of the baseband signal is determined to be a dual time slot. If the address difference is not greater than the power address threshold, the target time slot type of the baseband signal is determined to be a non-dual time slot. When the power address is not greater than the noise floor address threshold, the target time slot type corresponding to the baseband signal is determined to be a non-dual time slot. Thus, the target time slot type corresponding to the signal can be accurately identified, providing conditions for subsequent accurate power control.

Further, in an optional implementation of the present disclosure, when determining the power statistics duration corresponding to the target time slot type according to the target time slot type, if the determined target time slot type is a double time slot, the corresponding power statistics duration is determined to be the first duration; if the determined target time slot type is a non-double time slot, the corresponding power statistics duration is determined to be The second duration is longer than the first duration. For example, when the target time slot type is a dual time slot, the power statistics duration can be determined to be 25μs (microseconds); when the target time slot type is a single time slot or a noise floor, the power statistics duration can be determined to be 5ms. Therefore, by setting different power statistics durations for different time slot types for power control, different power control schemes are used to control the output power for signals of different time slot types, thereby being able to adapt to P25 signals of different standards.

In an optional implementation of the present disclosure, as shown in FIG4 , based on the above-mentioned embodiment, step 105 may include the following sub-steps:

Step 301, obtaining the initial address of the coefficients of the baseband signal.

Among them, the coefficient initial address can be set according to actual needs, and the present disclosure does not limit its specific value.

Step 302: Determine candidate coefficient addresses according to power statistics.

In an optional implementation of the present disclosure, when determining the candidate coefficient address, a preset background noise power threshold can be first obtained, wherein the background noise power threshold can be set according to actual needs. Then, it can be determined whether the power statistic is less than the background noise power threshold. If the power statistic is less than the background noise power threshold, the initial address of the coefficient is determined to be the candidate coefficient address; if the power statistic is not less than the background noise power threshold, a high power threshold judgment step is performed. For example, assuming that the initial address of the coefficient is 50, if the power statistic is less than the background noise power threshold, the candidate coefficient address is determined to be 50; if the power statistic is not less than the background noise power threshold, a high power threshold judgment step is performed.

In an optional implementation of the present disclosure, the high power threshold judgment step includes: presetting a low power threshold address and a high power threshold address, wherein the specific values of the low power threshold address and the high power threshold address can be set according to actual needs, and the difference between the low power threshold address and the high power threshold address is a preset address value, which is not limited by the present disclosure. The low power threshold address refers to the power address corresponding to the low power threshold of the ALC circuit in the repeater, and the high power threshold address = low power threshold address + preset address value. Assuming that the high power threshold address is 2 greater than the low power threshold address, the address increases by 1 and the power increases by 0.5db (i.e., the power step is 0.5db), which means that the high threshold power is 1db greater than the low threshold power. Then, it can be judged whether the power statistic is greater than the high power corresponding to the high power threshold address. If the power statistic is not greater than the high power corresponding to the high power threshold address, and the power statistic is greater than the low power corresponding to the low power threshold address, the initial address of the coefficient is determined to be the candidate coefficient address.

In an optional implementation of the present disclosure, the high power threshold judgment step includes: obtaining the current coefficient address, the preset maximum value of the power threshold address and the minimum value of the coefficient address, wherein the initial value of the current coefficient address is the coefficient initial address, and the specific values of the maximum value of the power threshold address and the minimum value of the coefficient address can be set according to actual needs, and the present disclosure does not limit this. Then, it can be determined whether the power statistic is greater than the high power corresponding to the high power threshold address. If the power statistic is not greater than the high power corresponding to the high power threshold address, the low power threshold judgment step is performed. If the power statistic is greater than the high power corresponding to the high power threshold address, the current coefficient address is further compared with the minimum value of the coefficient address, and/or the current low power threshold address is compared with the maximum value of the power threshold address.

Among them, it can be understood that when the current coefficient address is compared with the minimum value of the coefficient address for the first time, The current coefficient address is the coefficient initial address. When the current low power threshold address is compared with the maximum value of the power threshold address for the first time, the current low power threshold address is the aforementioned preset low power threshold address, that is, the initial value of the current coefficient address is the coefficient initial address, and the initial value of the current low power threshold address is the preset low power threshold address. If the current coefficient address is not equal to the minimum value of the coefficient address and the current low power threshold address is not equal to the maximum value of the power threshold address, the current coefficient address and the high power threshold address are updated; in response to the current coefficient address being equal to the minimum value of the coefficient address, and/or the current low power threshold address being equal to the maximum value of the power threshold address, the current coefficient address is determined as a candidate coefficient address.

In an optional implementation of the present disclosure, when updating the current coefficient address and the high power threshold address, the current coefficient address can be stepped by a first preset value, and the high power threshold address can be stepped by a second preset value to obtain an updated current coefficient address and an updated high power threshold address, and then return to the above-mentioned high power threshold judgment step to continue to judge whether the power statistic is greater than the high power corresponding to the updated high power threshold address. The first preset value and the second preset value can be set according to actual needs. For example, the first preset value can be set to -1 and the second preset value can be set to +1.

In an optional implementation of the present disclosure, the low power threshold determination step includes: obtaining a preset maximum value of the coefficient address, wherein the maximum value of the coefficient address can be pre-set according to actual needs, determining whether the power statistic is greater than the low power corresponding to the low power threshold address, and if the power statistic is not greater than the low power corresponding to the low power threshold address, further comparing the current coefficient address with the maximum value of the coefficient address, and/or determining whether the current low power threshold address is 0. It can be understood that when the current coefficient address is compared with the maximum value of the coefficient address for the first time, the current coefficient address is the coefficient initial address, and when it is determined for the first time whether the current low power threshold address is 0, the current low power threshold address is the aforementioned preset low power threshold address, that is, the initial value of the current coefficient address is the coefficient initial address, and the initial value of the current low power threshold address is the preset low power threshold address. If the current coefficient address is not equal to the maximum value of the coefficient address and the current low power threshold address is not 0, the current coefficient address and the low power threshold address are updated; in response to the current coefficient address being equal to the maximum value of the coefficient address, and/or the current low power threshold address being 0, the current coefficient address is determined as a candidate coefficient address.

In an optional implementation of the present disclosure, when updating the current coefficient address and the low power threshold address, the current coefficient address can be stepped to a third preset value, and the low power threshold address can be stepped to a fourth preset value to obtain an updated current coefficient address and a low power threshold address, and then the low power threshold determination step is returned to continue to determine whether the power statistic is greater than the low power corresponding to the updated low power threshold address. The third preset value and the fourth preset value can be set according to actual needs, for example, the third preset value can be set to +1, and the fourth preset value can be set to -1.

Step 303, determining the target coefficient address according to the candidate coefficient address, the coefficient initial address and the gain control parameter.

In an optional implementation of the present disclosure, the maximum post-amplification threshold address of the baseband signal can be obtained, the sum of the coefficient initial address and the gain control parameter is calculated, the smaller value of the candidate coefficient address and the sum is determined as the new coefficient address, and finally the new coefficient address is compared with the maximum post-amplification threshold address, and the new coefficient address is compared with the maximum post-amplification threshold address. The smaller value in the value threshold address is determined as the target coefficient address. Among them, the post-release value is the gain released in the ALC module after the AGC module attenuates the gain, which can be understood as the gain attenuated in the analog domain before analog-to-digital conversion and the gain released in the digital domain after analog-to-digital conversion; the maximum post-release value threshold address is the address corresponding to the maximum value in the post-release value threshold.

Step 304: Power control the baseband signal based on the target coefficient address.

In an exemplary embodiment, when power control is performed on a baseband signal based on a target coefficient address, a preset coefficient table may be queried first, and a target coefficient corresponding to the target coefficient address may be determined based on the coefficient table.

Among them, the coefficient table is pre-set, and the coefficient table records the correspondence between different coefficients and coefficient addresses. The coefficient address is equivalent to the number of the corresponding coefficient. One coefficient corresponds to a unique coefficient address. The coefficient is the attenuation value for attenuating the baseband signal or the amplification value for amplifying the baseband signal.

Then, after the target coefficient is determined, the power of the baseband signal can be controlled based on the target coefficient. Thus, the rapid attenuation of high-power time slot signals and the rapid amplification of low-power time slot signals are achieved through power control, thereby solving the problem of reduced power output dynamic range of the device when the power difference between time slots is large, and reducing the impact of the near-far effect between users.

In an optional implementation of the present disclosure, a switch can be used to control whether to use the power control scheme provided by the present scheme for power control. If the switch is turned on, the present scheme is used for power control, and the baseband signal is power controlled using a determined target coefficient address. If the switch is turned off, the baseband signal is power controlled using a fixed coefficient.

The power control method of the disclosed embodiment obtains the initial address of the coefficient of the baseband signal, determines the candidate coefficient address according to the power statistics, and determines the target coefficient address based on the candidate coefficient address, the initial address of the coefficient and the gain control parameter, and then performs power control on the baseband signal based on the target coefficient address. Thus, the rapid attenuation of high-power time slot signals and the rapid amplification of low-power time slot signals are achieved through power control, thereby solving the problem of reduced power output dynamic range of the device when the power difference between time slots is large, and reducing the influence of the near-far effect between users.

FIG5 is a block diagram of a power control method according to one or more exemplary embodiments. As shown in FIG5, the power control method of the present invention mainly includes an analog-to-digital conversion module, an automatic gain control module (hereinafter referred to as AGC), a downsampling module, a filtering module, a time slot identification module, a power control module, an upsampling module, and a digital-to-analog conversion module. Among them, the analog-to-digital conversion module is used to convert the received analog RF signal into a digital signal. The function of the automatic gain control module is to control the signal gain of the input analog-to-digital converter to prevent the signal from overflowing due to excessive signal size and causing signal abnormality. When the input signal is too large, the AGC can automatically attenuate to the set gain, and transmit the attenuation value to the subsequent power control module for signal output power processing. The function of the downsampling module is to convert the high sampling rate signal to a preset sampling rate, and the function of the upsampling module is to convert the low sampling rate signal to a preset sampling rate for signal processing. The function of the filtering module is to filter out unwanted interference signals outside the passband. The function of the time slot identification module is to identify the time slot type of the received signal, which is used to perform the aforementioned steps 200-207. The function of the power control module is to control the stable output of the received signal at the power value set by the user. The specific structure of the power control module is shown in Figure 6. The power control module includes a power statistics unit 1, a power statistics unit 2, a coefficient determination unit, and an attenuation and amplification unit, wherein the power statistics unit 1 and the power statistics unit 2 are respectively used for power statistics of different time slot types; the coefficient determination unit is used to determine the target coefficient according to the power statistics value obtained by the power statistics unit 1 and the power statistics unit 2; the attenuation and amplification unit is used to attenuate or amplify the signal according to the target coefficient. The function of the digital-to-analog conversion module is to convert the digital signal into an analog signal.

FIG7 is a flow chart of a power control method according to one or more embodiments. As shown in FIG7, for the received analog signal, the received analog signal is first converted into a digital signal by an analog-to-digital conversion module, and then the signal is automatically gain controlled according to the size of the input signal by an automatic gain control module, and the gain control parameter is input into the power control module. Next, the digital signal is down-converted to baseband 0 frequency, and the down-sampling module is used to down-sample the converted signal. The sampling rate can be selected according to the size of the signal bandwidth. This scheme reduces the signal sampling rate to 0.48Msps. Next, the down-sampled signal is filtered by a filter module to filter out unwanted spurious signals outside the passband. The filtered signal is identified by a time slot identification module, and a corresponding power control scheme is selected according to the identification result, that is, a corresponding power statistics duration is selected to perform power statistics for power control. The specific identification process is shown in FIG8. The specific power control process is performed by the power control module, and the power control process is shown in FIG9. After the power of the signal is controlled within the user-set value through the power control module, the signal is upsampled through the upsampling module, and then the signal is up-converted to the required frequency point. Finally, the digital signal is converted into an analog signal through the digital-to-analog conversion module and sent to the subsequent modules for processing.

As shown in FIG8 , the specific steps of performing time slot identification on a signal include:

Step 61, setting the background noise address threshold G0 and the power address threshold G1;

Step 62: Count the power value of the 5 ms digital baseband signal for 13 times to obtain 13 power values;

Step 63: Compare the 13 statistical power values with the power table to obtain 13 power addresses R;

Step 64: Select the maximum power address RM and the minimum power address RI from the 13 addresses;

Step 65: Calculate RM-RI to obtain the address difference, and assign the calculation result to M;

Step 66: Determine whether R<G0 and M<G1; if so, execute step 67-1, otherwise execute step 67-2;

Step 67-1: Determine that the signal is background noise and assign H=0;

Step 67-2: Determine whether R>G0 and M<G1; if yes (R>G0 and M<G1), execute step 68-1; if no, execute step 68-2;

Step 68-1: Determine that the signal is a full time slot and assign H=1;

Step 68-2: Determine whether R>G0 and M>G1; if so (R>G0 and M>G1), determine that the signal is a non-full time slot and assign H=2, otherwise determine that the signal is a full time slot and assign H=1 to complete the time slot identification.

In the embodiment shown in FIG8 , a full time slot is a single time slot, and a non-full time slot is a double time slot. When H=0 or H=1, it can be determined that the signal is not a double time slot (bottom noise or single time slot signal), and when H=2, it is determined that the signal is a double time slot. Through the time slot identification process shown in FIG8 , it is possible to identify whether the currently received signal is a background noise, a single time slot signal, or a dual time slot signal, thereby achieving accurate distinction between different time slot types.

As shown in FIG9 , the specific steps of the power control module for performing power control include:

Step 71: Set the low power threshold address, high power threshold address, maximum power threshold address, noise floor power threshold PB, maximum post-release threshold address R1, coefficient initial address R0=50, coefficient address minimum value RMI, coefficient address maximum value RMA of ALC, where the high power threshold address == low power threshold address+2;

Step 72: Determine whether the time slot type is a double time slot (ie, H=2); if so, set the first ALC power statistics duration to 25us, otherwise set the second ALC power statistics duration to 5ms;

Step 73: assign the power statistical value collected by ALC in the corresponding statistical time period to a variable P;

Step 74: Determine whether P<PB, if yes, execute step 79; otherwise, execute step 75;

Step 75: Determine whether P>PH, if yes, execute step 76, otherwise execute step 77, wherein PH is the high power corresponding to the high power threshold address;

Step 76: Determine whether R=RMI and/or the low power threshold address=the maximum power threshold address. If yes, execute step 79; otherwise, execute step 76-1; wherein the initial value of R is the coefficient initial address R0;

Step 76-1: Update R and the low power threshold address, the updating method is that the updated current coefficient address R = the current coefficient address R-1, the updated low power threshold address = the current low power threshold address + 1, and the high power threshold address is updated synchronously, the updated high power threshold address = the updated low power threshold address + 2, and return to step 75;

Step 77: Determine whether P≤PL, if yes, execute step 78, otherwise execute step 79, wherein PL is the low power corresponding to the low power threshold address;

Step 78: Determine whether R=RMA and/or the low power threshold address=0. If yes, execute step 79, otherwise execute step 78-1; wherein the initial value of R is the coefficient initial address R0;

Step 78-1: Update R and the low power threshold address, the updating method is that the updated current coefficient address R = the current coefficient address R + 1, the updated low power threshold address = the current low power threshold address - 1, and return to step 77;

Step 79: R and PL keep their current values and are no longer updated, and continue to execute step 710;

Step 710: determine whether the candidate coefficient address R>R0+RA; if so, R=R0+RA; otherwise, R keeps the current value unchanged; wherein RA is the gain control parameter passed in by the AGC module;

Step 711: determine whether R>R1, if yes, R=R1; otherwise, R keeps the current value unchanged;

Step 712: According to the R value, query the coefficient table to obtain the target coefficient COE, wherein the target coefficient COE is the attenuation value for attenuating the baseband signal or the amplification value for amplifying the baseband signal;

Step 713: Determine whether switch EN=1. If so, multiply the target coefficient COE by the baseband signal, otherwise multiply the fixed coefficient 4096 by the baseband signal; wherein, 4096 is determined by assuming that the signal is truncated to 12 bits during signal processing. If it is truncated to 13 bits, the fixed coefficient is 8192. The fixed coefficient can be determined based on the actual truncation of the signal processing. 4096 is only an example. Multiplying the baseband signal by the fixed coefficient is equivalent to neither attenuation nor amplification of the signal.

Step 714: Complete signal power control and output the signal to the next module.

Through the power control process shown in FIG. 9 , stable power output of single-time slot signals and dual-time slot signals is achieved without affecting signal demodulation.

In order to implement the above embodiments, the present disclosure further provides a power control device, which can be implemented by software and/or hardware and can be integrated in a repeater.

Figure 10 is a structural diagram of a power control device provided according to one or more embodiments. As shown in Figure 10, the power control device 80 may include: a parameter acquisition module 810, a time slot identification module 820, a duration determination module 830, a power acquisition module 840 and a power control module 850.

The parameter acquisition module 810 is used to acquire the gain control parameters for performing automatic gain control on the baseband signal;

A time slot identification module 820, used to identify a target time slot type corresponding to a baseband signal;

The duration determination module 830 is used to determine the power statistics duration corresponding to the target time slot type according to the target time slot type;

A power acquisition module 840 is used to obtain a power statistical value of a baseband signal during a power statistical duration;

The power control module 850 is used to perform power control on the signal based on the power statistics and the gain control parameter.

Optionally, the time slot identification module 820 includes:

A setting unit, used for presetting a noise floor address threshold and a power address threshold of a baseband signal;

A power statistics unit, used to obtain a power value of a baseband signal counted a preset number of times within a preset time period;

A power address determination unit, used to find the power address corresponding to each power value;

A calculation unit, used to determine the address difference between the maximum power address and the minimum power address in the power address;

A judging unit, used to judge whether the power address is greater than the background noise address threshold;

The time slot type determination unit is used to determine that the target time slot type of the baseband signal is a dual time slot in response to the address difference being greater than the power address threshold when the power address is greater than the background noise address threshold; wherein the target time slot type includes dual time slot and non-dual time slot.

Optionally, the time slot type determination unit is further configured to:

In response to the address difference being not greater than the power address threshold, determining that the target time slot type corresponding to the baseband signal is a non-double time slot; wherein the non-double time slot includes a single time slot and a background noise.

Optionally, the time slot type determination unit is further configured to:

In response to the power address being not greater than the noise floor address threshold, determining that the target time slot type corresponding to the baseband signal is a non-double time slot; wherein the non-double time slot includes a single time slot and a noise floor.

Optionally, the duration determination module 830 is further configured to:

In response to the target time slot type being a dual time slot, determining the power statistics duration to be a first duration;

In response to the target time slot type being a non-double time slot, determining the power statistics duration to be a second duration, wherein the second duration is greater than the first duration.

Optionally, the power control module 850 includes:

An acquisition unit, used for acquiring an initial address of a coefficient of a baseband signal;

A first determining unit, configured to determine a candidate coefficient address according to a power statistic;

A second determining unit, configured to determine a target coefficient address according to the candidate coefficient address, the coefficient initial address and the gain control parameter;

A control unit is used to perform power control on a baseband signal based on a target coefficient address.

Optionally, the first determining unit is further configured to:

Get the preset noise floor power threshold;

Determine whether the power statistics value is less than the noise floor power threshold;

If so, the initial address of the coefficient is determined to be the candidate coefficient address;

If the power statistics value is not less than the noise floor power threshold, the high power threshold determination step is performed.

Optionally, the high power threshold determination step includes:

Preset low power threshold address and high power threshold address;

Determine whether the power statistics value is greater than the high power corresponding to the high power threshold address;

If the power statistic is not greater than the high power of the high power threshold address, and the power statistic is greater than the low power corresponding to the low power threshold address, the coefficient initial address is determined to be the candidate coefficient address;

The difference between the low power threshold address and the high power threshold address is a preset address value.

Optionally, the high power threshold determination step includes:

Obtaining a current coefficient address, a preset maximum value of a power threshold address, and a minimum value of a coefficient address, wherein an initial value of the current coefficient address is the coefficient initial address;

Determine whether the power statistics value is greater than the high power corresponding to the high power threshold address;

If not, proceed to the low power threshold determination step;

If yes, compare the current coefficient address with the minimum value of the coefficient address, and/or compare the current low power threshold address with the maximum value of the power threshold address;

In response to the current coefficient address being equal to the minimum value of the coefficient address, and/or the current low power threshold address being equal to the maximum value of the power threshold address, determining the current coefficient address as a candidate coefficient address;

In response to the current coefficient address being unequal to the minimum value of the coefficient address, and the current low power threshold address being unequal to the maximum value of the power threshold address, the current coefficient address and the high power threshold address are updated.

Optionally, the first determining unit is further configured to:

Stepping the current coefficient address by a first preset value and the high power threshold address by a second preset value to obtain an updated current coefficient address and an updated high power threshold address;

Return to the high power threshold determination step to continue determining whether the power statistics value is greater than the high power corresponding to the updated high power threshold address.

Optionally, the low power threshold determination step includes:

Get the preset maximum value of the coefficient address;

Determine whether the power statistics value is greater than the low power corresponding to the low power threshold address;

If not, compare the current coefficient address with the maximum value of the coefficient address, and/or determine whether the current low power threshold address is 0;

In response to the current coefficient address being equal to the maximum coefficient address, and/or the current low power threshold address being 0, determining the current coefficient address as a candidate coefficient address;

In response to the current coefficient address being unequal to the maximum coefficient address, and the current low power threshold address being not 0, the current coefficient address and the low power threshold address are updated.

Optionally, the first determining unit is further configured to:

The current coefficient address steps to a third preset value, and the low power threshold address steps to a fourth preset value, to obtain updated current coefficient address and low power threshold address;

Return to the low power threshold determination step to continue determining whether the power statistics value is greater than the low power corresponding to the updated low power threshold address.

Optionally, the second determining unit is further configured to:

Get the maximum post-amplification threshold address of the baseband signal;

Calculate the sum of the coefficient initial address and the gain control parameter;

Determine the smaller value between the candidate coefficient address and the sum value as the new coefficient address;

The smaller value between the new coefficient address and the maximum post-release threshold address is determined as the target coefficient address.

The power control device applicable to a repeater provided in the embodiment of the present disclosure can execute the power control method provided in the embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method. The contents not described in detail in the embodiment of the device of the present disclosure can refer to the description in any method embodiment of the present disclosure.

The embodiment of the present disclosure also provides a repeater device, including a processor and a memory; the processor calls the program or instructions stored in the memory to execute the steps of each embodiment of the power control method as described in the above embodiments, which will not be repeated here to avoid repeated description.

The embodiment of the present disclosure also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the steps of each embodiment of the power control method as described in the above embodiments are implemented. To avoid repeated description, they are not repeated here.

The embodiments of the present disclosure further provide a computer program product, including computer-readable instructions, which, when executed by a processor, implement the steps of each embodiment of the power control method as described in the aforementioned embodiments. To avoid repeated description, they are not repeated here.

Industrial Applicability

The power control scheme provided by the present invention selects different power control schemes for different time slot types to perform power control. Power control can be quickly implemented for signals of different time slot types without affecting the demodulation of the signals. It can be compatible with power control of different P25 standards at the same time. The gain control parameters of the automatic gain control of the acquired signal are involved in the power control, thereby achieving the effect of attenuating large signals and amplifying small signals.

Claims (16)

A power control method, the method comprising: Obtaining gain control parameters for automatic gain control of a baseband signal; Identifying a target timeslot type corresponding to the baseband signal; According to the target time slot type, determining a power statistics duration corresponding to the target time slot type; Obtaining a power statistical value of the baseband signal during the power statistical time period; Power control is performed on the baseband signal based on the power statistics and the gain control parameter. According to the power control method of claim 1, the identifying the target time slot type corresponding to the baseband signal comprises: Presetting a noise floor address threshold and a power address threshold of the baseband signal; Obtaining a power value of the baseband signal counted a preset number of times within a preset time length; Find the power address corresponding to each power value; Determine an address difference between a maximum power address and a minimum power address in the power addresses; Determine whether the power address is greater than the background noise address threshold; If so, in response to the address difference being greater than the power address threshold, determining that the target time slot type of the baseband signal is a dual time slot; wherein the target time slot type includes a dual time slot and a non-dual time slot. The power control method according to claim 2, further comprising: If the power address is not greater than the background noise address threshold, it is determined that the target time slot type corresponding to the baseband signal is a non-double time slot; wherein the non-double time slot includes a single time slot and background noise. The power control method according to claim 2, further comprising: If the address difference is not greater than the power address threshold, determine that the target time slot type of the baseband signal is a non-double time slot; wherein the non-double time slot includes a single time slot and a background noise. According to the power control method according to any one of claims 2 or 4, determining the power statistics duration corresponding to the target time slot type according to the target time slot type comprises: In response to the target time slot type being a dual time slot, determining the power statistics duration to be a first duration; In response to the target time slot type being a non-double time slot, the power statistics duration is determined to be a second duration, wherein the second duration is greater than the first duration. According to any one of claims 1 to 5, the power control method of the baseband signal based on the power statistic and the gain control parameter comprises: Obtaining an initial address of a coefficient of the baseband signal; Determine a candidate coefficient address according to the power statistics; Determine a target coefficient address according to the coefficient initial address, the candidate coefficient address and the gain control parameter; The baseband signal is power controlled based on the target coefficient address. According to the power control method of claim 6, the determining the target coefficient address according to the coefficient initial address, the candidate coefficient address and the gain control parameter comprises: Obtaining a maximum post-amplification threshold address of the baseband signal; Calculating the sum of the coefficient initial address and the gain control parameter; Determine a smaller value between the candidate coefficient address and the sum value as a new coefficient address; The smaller value between the new coefficient address and the maximum post-playback threshold address is determined as the target coefficient address. According to the power control method of claim 6 or 7, determining the candidate coefficient address according to the power statistics comprises: Get the preset noise floor power threshold; Determine whether the power statistic value is less than the noise floor power threshold; If yes, determining the coefficient initial address as a candidate coefficient address; If the power statistic is not less than the noise floor power threshold, a high power threshold determination step is performed. According to the power control method of claim 8, the high power threshold determination step comprises: Preset low power threshold address and high power threshold address; Determine whether the power statistic is greater than the high power corresponding to the high power threshold address; If the power statistic is not greater than the high power of the high power threshold address, and the power statistic is greater than the low power corresponding to the low power threshold address, determining the coefficient initial address as a candidate coefficient address; Wherein, the difference between the low power threshold address and the high power threshold address is a preset address value. According to the power control method of claim 8, the high power threshold determination step comprises: Obtaining a current coefficient address, a preset maximum value of a power threshold address, and a minimum value of a coefficient address, wherein an initial value of the current coefficient address is the coefficient initial address; Determine whether the power statistic is greater than the high power corresponding to the high power threshold address; If not, proceed to the low power threshold determination step; If yes, compare the current coefficient address with the minimum value of the coefficient address, and/or compare the current low power threshold address with the maximum value of the power threshold address; In response to the current coefficient address being equal to the minimum value of the coefficient address, and/or the current low power threshold address being equal to the maximum value of the power threshold address, determining the current coefficient address as a candidate coefficient address; In response to the current coefficient address being unequal to the minimum value of the coefficient address, and the current low power threshold address being unequal to the maximum value of the power threshold address, the current coefficient address and the high power threshold address are updated. According to the power control method of claim 10, the updating of the current coefficient address and the high power threshold address comprises: The current coefficient address steps to a first preset value, and the high power threshold address steps to a second preset value to obtain a more The new current coefficient address and the updated high power threshold address; Return to the high power threshold determination step to continue determining whether the power statistic is greater than the high power corresponding to the updated high power threshold address. According to the power control method of claim 10, the low power threshold determination step comprises: Get the preset maximum value of the coefficient address; Determine whether the power statistic is greater than the low power corresponding to the low power threshold address; If not, compare the current coefficient address with the maximum value of the coefficient address, and/or determine whether the current low power threshold address is 0; In response to the current coefficient address being equal to the maximum value of the coefficient address, and/or the current low power threshold address being 0, determining the current coefficient address as a candidate coefficient address; In response to the current coefficient address being not equal to the maximum value of the coefficient address, and the current low power threshold address being not 0, the current coefficient address and the low power threshold address are updated. According to the power control method of claim 10, the updating of the current coefficient address and the low power threshold address comprises: The current coefficient address steps to a third preset value, and the low power threshold address steps to a fourth preset value, to obtain an updated current coefficient address and a low power threshold address; Return to the low power threshold determination step to continue determining whether the power statistic is greater than the low power corresponding to the updated low power threshold address. A power control device, characterized in that the device comprises: A parameter acquisition module, used to acquire gain control parameters for automatic gain control of a baseband signal; A time slot identification module, used to identify the target time slot type corresponding to the baseband signal; A duration determination module, configured to determine, according to the target time slot type, a power statistics duration corresponding to the target time slot type; A power acquisition module, used to obtain the power statistical value of the baseband signal during the power statistical time length; A power control module is used to perform power control on the baseband signal based on the power statistics and the gain control parameter. A repeater station includes a processor and a memory; The processor is used to execute the power control method according to any one of claims 1 to 13 by calling the program or instruction stored in the memory. A computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the power control method according to any one of claims 1 to 13 is implemented.