WO2024185540A1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to the present invention comprises: a semiconductor chip having a first main surface and a second main surface on a side reverse from the first main surface; and a trench-type IGBT structure formed on the first main surface of the semiconductor chip. The IGBT structure includes a trench formed in the first main surface of the semiconductor chip, an insulation film formed on the side surfaces of the trench, and an embedded conductor embedded inside the trench with the insulation film therebetween. A recess that is recessed toward the side surface side of the trench is formed at an open end of the trench, and the width of the recess is 1350 Å or greater.

Description

Semiconductor Device Related Applications

This application corresponds to Patent Application No. 2023-036385 filed with the Japan Patent Office on March 9, 2023, the entire disclosure of which is incorporated herein by reference.

This disclosure relates to a semiconductor device with a trench-type IGBT structure.

Patent document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device.

International Publication No. 2020/080476

One embodiment of the present disclosure provides a semiconductor device that can improve dielectric breakdown resistance.

One embodiment of the present disclosure provides a semiconductor device that includes a semiconductor chip having a first main surface and a second main surface opposite the first main surface, and a trench-type IGBT structure formed on the first main surface of the semiconductor chip, the IGBT structure including a trench formed on the first main surface of the semiconductor chip, an insulating film formed on a side surface of the trench, and an embedded conductor embedded inside the trench via the insulating film, and a recess is formed at the opening end of the trench that recesses into the side surface of the trench, and the width of the recess is 1350 Å or more.

According to one embodiment of the present disclosure, a semiconductor device can be provided that can improve the dielectric breakdown resistance.

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a plan view showing an example of the layout of a plurality of IGBT regions, boundary regions, gate electrodes, and emitter electrodes. FIG. 3 is a plan view showing an example of the layout of gate wiring, boundary well regions, and peripheral well regions. FIG. 4 is an enlarged view of a portion enclosed by a dashed line IV in FIG. FIG. 5 is an enlarged view of a portion surrounded by a dashed line V in FIG. FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is an enlarged view of a portion surrounded by a dashed line VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. FIG. 10 is an enlarged view of the portion surrounded by the dashed line X in FIG. FIG. 11 is an enlarged view of a portion surrounded by a dashed line XI in FIG. 12A is a cross-sectional view taken along line XIIA-XIIA shown in FIG. FIG. 12B is an enlarged view of the portion surrounded by the dashed line XIIB in FIG. FIG. 13 is a schematic cross-sectional view for explaining the curvature index. 14A and 14B are diagrams showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 15A and 15B are diagrams showing the next steps of FIGS. 14A and 14B, respectively. 16A and 16B are diagrams showing the next steps of FIGS. 15A and 15B, respectively. 17A and 17B are diagrams showing the next steps of FIGS. 16A and 16B, respectively. 18A and 18B are diagrams showing the next steps of FIGS. 17A and 17B, respectively. 19A and 19B are diagrams showing the next steps of FIGS. 18A and 18B, respectively. 20A and 20B are diagrams showing the next steps of FIGS. 19A and 19B, respectively. 21A and 21B are diagrams showing the next steps of FIGS. 20A and 20B, respectively. 22A and 22B are diagrams showing the next steps of FIGS. 21A and 21B, respectively. FIG. 23 is a diagram for explaining a patterning mask. FIG. 24 is a graph showing the relationship between the chamfer width and the curvature index of the patterning mask. FIG. 25 is a diagram showing the test results when an electrostatic breakdown resistance test (ESD resistance test) was performed on Example 1, Example 2, and Reference Examples 1 to 4. 26A to 26C are diagrams showing test results when a time-zero dielectric breakdown withstand test (TZBD withstand test) was performed on Reference Examples 1 to 3, respectively. 27A to 27C are diagrams showing test results when electrostatic breakdown resistance tests were performed on Reference Example 4, Example 1, and Example 2, respectively. FIG. 28 is a graph showing the relationship between the TCE treatment time and the amount of side etching of the trench. 29A to 29C are diagrams showing test results when a time zero dielectric breakdown withstand test (TZBD withstand test, 78 V) was performed on Reference Example 5, Example 3, and Example 4. 30A and 30B are diagrams showing test results when a time zero dielectric breakdown withstand test (TZBD withstand test, 84 V) was performed on Reference Example 5, Example 3, and Example 4. 31A and 31B are diagrams showing test results when a time zero dielectric breakdown withstand test (TZBD withstand test, 86 V) was performed on Reference Example 5, Example 3, and Example 4. FIG. 32 corresponds to FIG. 5 and is a cross-sectional view for explaining a modified example of the present disclosure.

FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is a plan view showing an example layout of a plurality of IGBT regions 6, a boundary region 7, a gate electrode 71, and an emitter electrode 75. FIG. 3 is a plan view showing an example layout of a gate wiring 40, a boundary well region 50, and a peripheral well region 56. FIG. 4 is an enlarged view of a portion surrounded by a dashed line IV in FIG. 2. FIG. 5 is an enlarged view of a portion surrounded by a dashed line V in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is an enlarged view of a portion surrounded by a dashed line VIII in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5. FIG. 10 is an enlarged view of a portion surrounded by a dashed line X in FIG. 7. FIG. 11 is an enlarged view of a portion surrounded by a dashed line XI in FIG. 2. FIG. 12A is a cross-sectional view taken along line XIIA-XIIA in FIG. 11. FIG. 12B is an enlarged view of the portion surrounded by the dashed line XIIB in FIG. 11. FIG. 13 is a schematic plan view for explaining the curvature index CI.

The semiconductor device 1 is an IGBT semiconductor device equipped with an IGBT (Insulated Gate Bipolar Transistor).

As shown in Figures 1 to 3, the semiconductor device 1 includes a semiconductor chip 2 having a rectangular parallelepiped shape. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The normal direction Z is also the thickness direction of the semiconductor chip 2.

The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The semiconductor chip 2 has a single-layer structure made of a silicon single crystal substrate.

The semiconductor chip 2 is, for example, square in plan view. The size of the semiconductor chip 2 is, for example, 0.5 mm square or more and 20 mm square or less. A chip size of "X mm square" may mean that the length of one side of the square semiconductor chip 2 is X mm.

As shown in Figures 2 and 3, the semiconductor device 1 includes a plurality of IGBT regions 6 formed at intervals in the second direction Y on the first main surface 3. Each IGBT region 6 includes a trench-type IGBT structure (transistor structure) Tr. The IGBT region 6 may be referred to as an "active region." The plurality of IGBT regions 6 include a first IGBT region 6A and a second IGBT region 6B.

As shown in Figures 2 and 3, the first IGBT region 6A is formed in a region on the first side surface 5A side of a line that crosses the center of the first main surface 3 in the first direction X. The second IGBT region 6B is formed in a region on the second side surface 5B side of a line that crosses the center of the first main surface 3 in the first direction X. In this embodiment, the multiple IGBT regions 6 are each formed in a quadrangular ring shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

As shown in Figures 2 and 3, the semiconductor device 1 further includes a boundary region 7 formed in a region between the multiple IGBT regions 6. Specifically, the boundary region 7 is provided in a band shape extending in the first direction X in the region between the first IGBT region 6A and the second IGBT region 6B. In the example of Figures 2 and 3, the boundary region 7 is located on a straight line that crosses the center of the first main surface 3 in the first direction X.

As shown in Figures 2 and 3, the boundary region 7 includes a first boundary region 8 having a relatively large width in the second direction Y, and a second boundary region 9 having a width in the second direction Y smaller than that of the first boundary region 8. The first boundary region 8 is provided in an area on one side in the first direction X (the third side surface 5C side) as a portion that supports the terminal electrode. The first boundary region 8 may also be referred to as a "pad region," a "wide region," or a "terminal support region."

In this embodiment, the first boundary region 8 is located on a straight line that crosses the center of the first main surface 3 in the first direction X in a plan view, and is provided in a rectangular shape near the center of the third side surface 5C. The width of the first boundary region 8 may be 100 μm or more and 800 μm or less. It is preferable that the width of the first boundary region 8 is 200 μm or more and 600 μm or less. In this embodiment, the width of the first boundary region 8 is set in the range of 350 μm or more and 450 μm or less.

The second boundary region 9 is formed in the region on the other side in the first direction X (the fourth side surface 5D side) of the first boundary region 8 as a portion that supports the wiring. The second boundary region 9 is located on a straight line that crosses the center of the first main surface 3 in the first direction X, and is pulled out in a strip shape from the first boundary region 8 toward the center of the fourth side surface 5D. The second boundary region 9 may also be called a "street region," a "narrow width region," or a "wiring support region."

As shown in Figures 2 and 3, the semiconductor device 1 further includes a peripheral region 10. The peripheral region 10 collectively surrounds the multiple IGBT regions 6. The peripheral region 10 is a quadrangular ring extending along the first to fourth side surfaces 5A to 5D. The peripheral region 10, together with the boundary region 7, forms an inactive region. In this embodiment, the IGBT structure Tr, which will be described later, is not formed in the boundary region 7 and the peripheral region 10.

As shown in Figures 6, 7 and 12A, the semiconductor device 1 includes an n-type (first conductivity type) drift region 11. The drift region 11 is formed throughout the interior of the semiconductor chip 2. In this embodiment, the semiconductor chip 2 is made of an n-type semiconductor substrate, and the drift region 11 is formed using this semiconductor substrate.

As shown in Figures 6, 7 and 12A, the semiconductor device 1 further includes an n-type buffer region 12 formed in a surface layer portion of the second main surface 4. In this embodiment, the buffer region 12 is formed in a layer extending along the second main surface 4 over the entire area of the second main surface 4. The buffer region 12 has a higher n-type impurity concentration than the drift region 11. The presence or absence of the buffer region 12 is optional, and a configuration without the buffer region 12 may be adopted.

As shown in Figures 6, 7 and 12A, the semiconductor device 1 includes a p-type (second conductivity type) collector region 13 formed in a surface layer portion of the second main surface 4. In this embodiment, the collector region 13 is formed in a surface layer portion on the second main surface 4 side of the buffer region 12. In this embodiment, the collector region 13 is formed in a layer shape extending along the second main surface 4 over the entire area of the second main surface 4. The collector region 13 is exposed from the second main surface 4 and parts of the first to fourth side surfaces 5A to 5D.

As shown in Figures 2 and 4, the semiconductor device 1 further includes a plurality of trench isolation structures 20 formed in the first main surface 3 so as to separate the multiple IGBT regions 6. A gate potential is applied to the multiple trench isolation structures 20. The trench isolation structures 20 may also be referred to as "trench gate isolation structures" or "trench gate connection structures." The multiple trench isolation structures 20 include a first trench isolation structure 20A and a second trench isolation structure 20B.

As shown in Figures 2 and 4, the first trench isolation structure 20A surrounds the first IGBT region 6A and separates the first IGBT region 6A from the boundary region 7 and the outer peripheral region 10. In this embodiment, the first trench isolation structure 20A is formed in a polygonal ring shape having four sides parallel to the periphery of the semiconductor chip 2 in a plan view. The first trench isolation structure 20A has a bent portion that separates the first boundary region 8 and the second boundary region 9 of the boundary region 7 in a plan view.

As shown in Figures 2 and 4, the second trench isolation structure 20B surrounds the second IGBT region 6B and separates the second IGBT region 6B from the boundary region 7 and the outer peripheral region 10. In this embodiment, the second trench isolation structure 20B is formed in a polygonal ring shape having four sides parallel to the periphery of the semiconductor chip 2 in a plan view. The second trench isolation structure 20B has a bent portion that separates the first boundary region 8 and the second boundary region 9 of the boundary region 7 in a plan view.

As shown in Figures 2, 4 and 11, each trench isolation structure 20A, 20B includes at least two first direction portions 20X extending in a first direction X and at least two second direction portions 20Y extending in a second direction Y. The ends of the first direction portions 20X and the ends of the second direction portions 20Y are mechanically and electrically connected. The ends of the first direction portions 20X and the ends of the second direction portions 20Y intersect in an L-shape to form corners of the polygonal ring-shaped trench isolation structures 20A, 20B.

Below, the configuration of one trench isolation structure 20 will be described. In describing the trench isolation structure 20, both Fig. 8 and Fig. 9 show a cross section of the trench isolation structure 20. Fig. 8 is a cross section perpendicular to the longitudinal direction of the trench isolation structure 20, and Fig. 9 is a cross section intersecting a T-shaped intersection 91P (described later) of the trench isolation structure 20.

As shown in Figures 7 to 9, the trench isolation structure 20 includes an isolation trench 21 (first trench), an isolation insulating film 22, and an isolation buried electrode (buried conductor) 23. The isolation trench 21 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surface of the trench isolation structure 20.

The isolation trench 21 is formed in the first main surface 3. The isolation trench 21 is formed in a vertical shape in a cross-sectional view. The isolation trench 21 includes a pair of side surfaces 21a, 21b facing each other, and a bottom surface 21c connecting the pair of side surfaces 21a, 21b. The bottom surface 21c has a rounded shape that bulges toward the second main surface 4 in a cross-sectional view.

8, the isolation trench 21 has a first width _W1 . The first width _W1 is the width (maximum value) in a direction perpendicular to the direction in which the isolation trench 21 extends. The first width _W1 is preferably less than the width of the second boundary region 9. The first width _W1 is preferably not less than 0.5 μm and not more than 2.0 μm. More specifically, the first width _W1 may be 1.0 μm.

The isolation trench 21 has a first depth _D1 . The first depth _D1 may be 1 μm or more and 30 μm or less. The first depth _D1 is preferably 4 μm or more and 15 μm or less. The first depth _D1 is particularly preferably 6 μm or more and 10 μm or less. The isolation trench 21 may be formed in a tapered shape in which the width decreases toward the second main surface 4 in a cross-sectional view. The bottom surface 21c may be a flat surface parallel to the first main surface 3.

As shown in FIG. 8 and FIG. 9, a first recess 96 recessed toward the side surfaces 21a and 21b of the isolation trench 21 is formed at the opening ends 21d and 21e of the isolation trench 21. The cross-sectional shape of the first recess 96 is an arc recessed toward the side surfaces 21a and 21b of the isolation trench 21. The first recess 96 has a third width _W3 . The third width _W3 is the width in the second direction Y between the point where the extension of the side surfaces 21a and 21b intersects with the first main surface 3 and the end of the first recess 96. The third width _W3 is 1350 Å or more and 2000 Å or less. The first recess 96 has a third depth _D3 . The third depth _D3 is greater than the third width _W3 . The third depth _D3 is 1850 Å or more. The ratio (W ₃ /W ₁ ) of the third width W ₃ to the first width W ₁ of the isolation trench 21 is not less than 0.14 and not more than 0.2.

As shown in Figures 7 to 9, the isolation insulating film 22 is formed in the form of a film along the side surfaces 21a, 21b of the isolation trench 21. The isolation insulating film 22 defines a recess space within the isolation trench 21. The isolation insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. It is preferable that the isolation insulating film 22 has a single-layer structure made of a single insulating film. It is particularly preferable that the isolation insulating film 22 includes a silicon oxide film made of an oxide of the semiconductor chip 2.

As shown in Figures 7 to 9, the isolated buried electrode 23 is buried in the isolation trench 21 with the isolation insulating film 22 in between. In this embodiment, the isolated buried electrode 23 is made of conductive polysilicon. A gate potential is applied to the isolated buried electrode 23.

Below, the structure within the multiple IGBT regions 6 will be described. The structure on the second IGBT region 6B side is substantially the same as the structure on the first IGBT region 6A side. Specifically, the structure on the second IGBT region 6B side is linearly symmetrical to the structure on the first IGBT region 6A side with respect to the boundary region 7. Below, the structure on the first IGBT region 6A side will be described. The explanation of the structure on the second IGBT region 6B side will be omitted, as the explanation of the structure on the first IGBT region 6A side applies.

As shown in Figures 6 and 7, the semiconductor device 1 includes a p-type base region 25 formed in the surface layer of the first main surface 3 in the first IGBT region 6A. The base region 25 may also be called a "body region" or a "channel region." The base region 25 is formed at a depth shallower than the trench isolation structure 20, and has a bottom located closer to the first main surface 3 than the bottom wall of the trench isolation structure 20. The base region 25 extends in a layered manner along the first main surface 3, and is connected to the inner peripheral wall of the trench isolation structure 20.

As shown in Figures 2 and 4, the semiconductor device 1 includes a plurality of trench structures 30. A gate potential is applied to the plurality of trench structures 30. The plurality of trench structures 30 penetrate the base region 25 and reach the drift region 11. The plurality of trench structures 30 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of trench structures 30 are arranged in a stripe shape extending in the second direction Y.

As shown in Figures 4 and 11, the multiple trench structures 30 each have a first end 30A on the boundary region 7 side and a second end 30B on the outer periphery region 10 side in the longitudinal direction (second direction Y). The first end 30A and the second end 30B are mechanically and electrically connected to the trench isolation structure 20. In other words, the multiple trench structures 30 and the trench isolation structure 20 form a ladder-shaped trench gate structure. The connection portion between the trench structure 30 and the trench isolation structure 20 may be considered as part of the trench isolation structure 20 or may be considered as part of the trench structure 30.

The configuration of one trench structure 30 is described below.

As shown in Figures 6 and 10, the trench structure 30 includes a gate trench 31 (second trench), a gate insulating film 32, and a gate buried electrode (buried conductor) 33. The gate trench 31 is dug down from the first main surface 3 toward the second main surface 4, and defines the wall surface of the trench structure 30.

The gate trench 31 is formed in the first main surface 3. The gate trench 31 is formed in a vertical shape in a cross-sectional view. The gate trench 31 includes a pair of side surfaces 31a, 31b facing each other and a bottom surface 31c connecting the pair of side surfaces 31a, 31b. The bottom surface 31c has a rounded shape that bulges toward the second main surface 4 in a cross-sectional view. In this embodiment, the gate trench 31 is connected to the separation trench 21 at both ends (first end 30A and second end 30B) in the second direction Y. Specifically, the side wall of the gate trench 31 is connected to the side wall of the separation trench 21, and the bottom wall of the gate trench 31 is connected to the bottom wall of the separation trench 21.

As shown in FIG. 6, the multiple gate trenches 31 are arranged at a constant pitch P in the first direction X. The pitch P of the multiple gate trenches 31 is preferably less than the width of the second boundary region 9 of the boundary region 7. The pitch P of the multiple gate trenches 31 may be 5 μm or more and 30 μm or less. The pitch P of the multiple gate trenches 31 is preferably 10 μm or more and 20 μm or less. The pitch P of the multiple gate trenches 31 is preferably 15 μm.

10, the gate trench 31 has a second width _W2 . The second width _W2 is the width (maximum value) in a direction perpendicular to the direction in which the gate trench 31 extends. The second width _W2 is preferably 0.5 μm or more and 2.0 μm or less. More specifically, the second width _W2 may be 1.0 μm. The second width _W2 may be approximately equal to the first width _W1 .

10, the gate trench 31 has a second depth _D2 . The second depth _D2 may be 1 μm or more and 30 μm or less. The second depth _D2 is preferably 4 μm or more and 15 μm or less. The second depth _D2 is particularly preferably 6 μm or more and 10 μm or less. The second depth _D2 is preferably approximately equal to the first depth _D1 . The gate trench 31 may be formed in a tapered shape in which the width decreases toward the second main surface 4 in a cross-sectional view. The bottom surface 31c may be a flat surface parallel to the first main surface 3.

As shown in FIG. 10, a second recess 97 recessed toward the side surfaces 31a and 31b of the gate trench 31 is formed at the opening ends 31d and 31e of the gate trench 31. The cross-sectional shape of the second recess 97 is an arc recessed toward the side surfaces 31a and 31b of the gate trench 31. The second recess 97 has a fourth width _W4 . The fourth width _W4 is the width in the first direction X between the point where the extension line of the side surfaces 31a and 31b intersects with the first main surface 3 and the end of the second recess 97. The fourth width _W4 is 1350 Å or more and 2000 Å or less. The second recess 97 has a fourth depth _D4 . The fourth depth _D4 is greater than the fourth width _W4 . The fourth depth _D4 is 1850 Å or more. The ratio ( _W4 / _W2 ) of the fourth width _W4 to the second width _W2 of the gate trench 31 is 0.14 or more and 0.2 or less. The ratio ( _W4 /P) of the fourth width _W4 to the pitch P (described later) of the multiple gate trenches 31 is 0.009 or more and 0.0133 or less. The ratio ( _W4 /W5) of the fourth width _W4 to the fifth width _W5 (described later) of the mesa portion 90 (described later) is 0.011 or more and _0.017 or less.

As shown in FIG. 6 and FIG. 10, the gate insulating film 32 is formed in the form of a film along the wall surface of the gate trench 31. The gate insulating film 32 defines a recess space within the gate trench 31. The thickness of the gate insulating film 32 is, for example, 50 nm or more and 200 nm or less.

The gate insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The gate insulating film 32 preferably has a single-layer structure made of a single insulating film. It is particularly preferable that the gate insulating film 32 includes a silicon oxide film made of an oxide of the semiconductor chip 2. In this embodiment, the gate insulating film 32 is made of the same insulating film as the isolation insulating film 22. The gate insulating film 32 is connected to the isolation insulating film 22 at the communicating portion between the isolation trench 21 and the gate trench 31.

As shown in FIG. 6 and FIG. 10, the gate buried electrode 33 is buried in the gate trench 31 with the gate insulating film 32 sandwiched therebetween. In this embodiment, the gate buried electrode 33 is made of conductive polysilicon. A gate potential is applied to the gate buried electrode 33. The gate buried electrode 33 is connected to the isolation buried electrode 23 at the communicating portion between the isolation trench 21 and the gate trench 31.

As shown in Figures 4 and 6, the semiconductor device 1 further includes a plurality of n-type emitter regions 35 formed in a surface layer portion of the base region 25. Each of the plurality of emitter regions 35 has a higher n-type impurity concentration than the drift region 11. The plurality of emitter regions 35 are formed on both sides of the plurality of trench structures 30. The plurality of emitter regions 35 are each formed in a band shape extending along the plurality of trench structures 30 in a planar view. Of course, the plurality of emitter regions 35 may be formed at intervals along the plurality of trench structures 30 in a planar view.

As shown in FIG. 6, the semiconductor device 1 further includes a plurality of n-type carrier storage regions 36 formed in the semiconductor chip 2 in the region directly below the base region 25. The plurality of carrier storage regions 36 suppress the discharge of carriers (positive holes) into the base region 25 and promote the accumulation of carriers (positive holes) in the region directly below the plurality of trench structures 30. In other words, the plurality of carrier storage regions 36 promote low on-resistance and low on-voltage from within the semiconductor chip 2.

The carrier storage regions 36 are arranged on both sides of the trench structures 30, and are formed in a strip shape extending along the trench structures 30 in a plan view. The carrier storage regions 36 are formed in the region between the bottom of the base region 25 and the bottom wall of the trench structure 30 in the thickness direction of the semiconductor chip 2. The carrier storage regions 36 are preferably spaced apart from the bottom wall of the trench structure 30 toward the base region 25. The bottoms of the carrier storage regions 36 are preferably located closer to the bottom wall of the trench structure 30 than the middle part of the trench structure 30. The carrier storage regions 36 have a higher n-type impurity concentration than the drift region 11. The n-type impurity concentration of the carrier storage regions 36 is preferably lower than that of the emitter region 35. The presence or absence of the carrier storage regions 36 is optional. Therefore, a configuration without the carrier storage regions 36 may be adopted.

As shown in FIG. 6, the semiconductor device 1 includes a plurality of contact holes 37 formed in the first main surface 3 to expose the emitter regions 35. The plurality of contact holes 37 are formed on both sides of the plurality of trench structures 30 at intervals in the first direction X from the plurality of trench structures 30. As shown in FIG. 6, the plurality of contact holes 37 may each be formed in a tapered shape in which the opening width narrows from the opening toward the bottom wall.

As shown in FIG. 6, the multiple contact holes 37 may be spaced from the bottom of the emitter region 35 toward the first main surface 3 so as not to reach the base region 25. Of course, the multiple contact holes 37 may penetrate the emitter region 35 so as to reach the base region 25. The multiple contact holes 37 are each formed in a band shape extending along the multiple trench structures 30 in a plan view. In the longitudinal direction (second direction Y), the multiple contact holes 37 are shorter than the multiple trench structures 30.

As shown in FIG. 6, the semiconductor device 1 includes a plurality of p-type contact regions 38 formed in a region different from the plurality of emitter regions 35 in the surface layer portion of the base region 25. The plurality of contact regions 38 are each formed in a strip shape extending along the corresponding contact hole 37 in a plan view. The bottoms of the plurality of contact regions 38 are each formed in a region between the bottom wall of the corresponding contact hole 37 and the bottom of the base region 25. The plurality of contact regions 38 have a higher p-type impurity concentration than the base region 25.

In this way, the base region 25, the multiple trench structures 30, the multiple emitter regions 35, the multiple carrier storage regions 36, the multiple contact holes 37 and the multiple contact regions 38 are included in the IGBT structure Tr (see Figures 2 and 4).

As shown in FIG. 4, the semiconductor device 1 includes a plurality of mesa portions 90 defined in the first IGBT region 6A. The plurality of mesa portions 90 are defined by gate trenches 31. Each mesa portion 90 is defined in a region between a pair of gate trenches 31 adjacent to each other in the first direction X. The mesa portion 90 is made up of a part of the semiconductor chip 2. The plurality of mesa portions 90 each extend in a band shape extending in the second direction Y, and are defined at intervals in the first direction X. In other words, the plurality of mesa portions 90 are formed in a stripe shape extending in the second direction Y.

As shown in Fig. 4, the mesa portion 90 has a fifth width _W5 . The fifth width _W5 is the width (maximum value) in a direction perpendicular to the direction in which the mesa portion 90 extends. The fifth width _W5 is preferably less than the width of the second boundary region 9. The fifth width _W5 may be 11 µm or more and 21 µm or less. It is preferable that the fifth width W5 is 11 µm or more and 16 µm or less. It is preferable that the fifth width _W5 is 14 µm.

As shown in Figures 3 and 4, the semiconductor device 1 includes a p-type boundary well region 50 formed in the surface layer of the first main surface 3 in the boundary region 7. In this embodiment, the boundary well region 50 has a higher p-type impurity concentration than the multiple base regions 25. Of course, the boundary well region 50 may have a lower p-type impurity concentration than the multiple base regions 25. The boundary well region 50 is formed in a region sandwiched between the first trench isolation structure 20A and the second trench isolation structure 20B. The boundary well region 50 extends in the first direction X along the boundary region 7 in a plan view.

As shown in FIG. 3, the boundary well region 50 includes a first boundary well region 51 formed in the first boundary region 8 of the boundary region 7, and a second boundary well region 52 formed in the second boundary region 9 of the boundary region 7. The first boundary well region 51 has a relatively large region width in the second direction Y. The first boundary well region 51 is formed in a quadrangular shape in a plan view. It is preferable that the first boundary well region 51 is formed over the entire area of the first boundary region 8.

As shown in Figures 3 and 4, the second boundary well region 52 has a width in the second direction Y that is smaller than the width of the first boundary well region 51, and is pulled out in a strip shape from the first boundary well region 51 toward the second boundary region 9. In this embodiment, the second boundary well region 52 is located on a straight line that crosses the center of the first main surface 3 in the first direction X.

As shown in FIG. 7, the boundary well region 50 is formed deeper than the base region 25. The boundary well region 50 is preferably formed deeper than the multiple trench isolation structures 20. As shown in FIG. 4, in this embodiment, the boundary well region 50 has a width in the second direction Y that is greater than the width of the boundary region 7, and is pulled out from the boundary region 7 into the multiple IGBT regions 6.

As shown in FIG. 7, the boundary well region 50 is connected to multiple trench isolation structures 20 adjacent in the second direction Y. The boundary well region 50 has a portion that covers the bottom walls of the multiple trench isolation structures 20. The boundary well region 50 has a portion that crosses the multiple trench isolation structures 20 and covers the bottom walls of the multiple trench structures 30.

As shown in FIG. 7, the boundary well region 50 covers the sidewalls of the trench isolation structure 20 in each IGBT region 6. Although not shown, the boundary well region 50 covers the sidewalls of multiple trench structures 30 in each IGBT region 6. As shown in FIGS. 4 and 7, the boundary well region 50 is connected to each base region 25 in the surface layer of the first main surface 3.

As shown in Figures 3 and 11, the semiconductor device 1 includes a p-type peripheral well region 56 formed in the surface layer of the first main surface 3 in the peripheral region 10. In this embodiment, the peripheral well region 56 has a higher p-type impurity concentration than the multiple base regions 25. Of course, the peripheral well region 56 may have a lower p-type impurity concentration than the multiple base regions 25. It is preferable that the p-type impurity concentration of the peripheral well region 56 is approximately equal to the p-type impurity concentration of the boundary well region 50.

As shown in Figures 3 and 12A, the peripheral well region 56 is formed in a layer extending along the first main surface 3 and is exposed from the first main surface 3. The peripheral well region 56 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The peripheral well region 56 is formed in a band shape extending along the multiple IGBT regions 6 in a planar view. In this embodiment, the peripheral well region 56 is formed in a ring shape surrounding the multiple IGBT regions 6 in a planar view. Specifically, the peripheral well region 56 is formed in a quadrangular ring shape having four sides parallel to the periphery of the first main surface 3.

As shown in FIG. 12A, the peripheral well region 56 is formed deeper than the multiple base regions 25. It is particularly preferable that the peripheral well region 56 is formed deeper than the multiple trench isolation structures 20 (multiple trench structures 30). In this embodiment, the peripheral well region 56 has a depth approximately equal to that of the boundary well region 50.

As shown in FIG. 12A, the peripheral well region 56 is connected to the multiple trench isolation structures 20. The peripheral well region 56 has a portion that covers the bottom walls of the multiple trench isolation structures 20. The peripheral well region 56 is extended from the peripheral region 10 into each IGBT region 6 (see FIG. 3). The peripheral well region 56 has a portion that crosses the multiple trench isolation structures 20 and covers the bottom walls of the multiple trench structures 30.

As shown in FIG. 4 and FIG. 11, the IGBT structure Tr includes a plurality of T-shaped intersections 91P formed at the connection portion between the trench isolation structure 20 and the trench structure 30. The plurality of T-shaped intersections 91P include a plurality of first T-shaped intersections 91PA (FIG. 4) formed at the connection portion between the first end portion 30A of the trench structure 30 and the first direction portion 20X on the boundary region 7 side of the trench isolation structure 20, and a plurality of second T-shaped intersections 91PB (FIG. 11) formed at the connection portion between the second end portion 30B of the trench structure 30 and the first direction portion 20X on the peripheral region 10 side of the trench isolation structure 20.

As shown in FIG. 4, the first T-shaped intersections 91PA face the boundary wiring 42 and boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2. As shown in FIG. 11, the second T-shaped intersections 91PB face the first peripheral wiring 43 and peripheral well region 56 in the thickness direction of the semiconductor chip 2.

5, the T-shaped intersection 91P has two corners 92P. The curvature index CI _P of each corner 92P is equal to or greater than 1.5 μm and equal to or less than 2.4 μm. The curvature index CI _P is the curvature index CI of the corner 92P (see FIG. 13).

As shown in FIG. 13, the curvature index CI is an index for defining the curvature of the corners (corner 92P, corner 92Q). The corners (corner 92P, corner 92Q) are formed by a first side 93 and a second side 94. Specifically, the curvature index CI is the shortest distance between the intersection point P1 of an extension line E1 of the first side 93 that forms the corner (corner 92P, corner 92Q) and an extension line E2 of the second side 94 that is perpendicular to the extension line E1 and forms the corner (corner 92P, corner 92Q), and the corner (corner 92P, corner 92Q). In other words, it is the shortest distance between the intersection point P1 and a tangent line TL of the corner (corner 92P, corner 92Q) that intersects both the extension line E1 and the extension line E2 at 45°.

At the T-shaped intersection 91P, the ratio (CI _P /W ₁ ) of the curvature index CI _P of the corner 92P to the first width W ₁ of the isolation trench 21 is 1.5 or more and 2.4 or less. At the T-shaped intersection 91P, the ratio (CI P /W ₂ ) of the curvature index CI _P of the corner 92P to the second width W ₂ of the multiple gate trenches 31 is 1.5 or more and 2.4 or less. At the T-shaped intersection 91P, the ratio (CI _P /P) of the curvature index CI _P of the corner 92P to the pitch P of the multiple gate _trenches 31 is 0.1 or more and 0.16 or less. At the T-shaped intersection 91P, the ratio (CI _P /W ₅ ) of the curvature index CI _P of the corner 92P to the fifth width W ₅ of the mesa portion 90 is not less than 0.11 and not more than 0.17.

11, the IGBT structure Tr includes a plurality of L-shaped intersections 91Q formed at the connection between the first direction portion 20X of the trench isolation structure 20 and the second direction portion 20Y of the trench isolation structure 20. The plurality of L-shaped intersections 91Q include a plurality of first L-shaped intersections 91 (not shown) formed at the connection between the first direction portion 20X and the second direction portion 20Y on the boundary region 7 side of the trench isolation structure 20, and a plurality of second L-shaped intersections 91QB formed at the connection between the first direction portion 20X and the second direction portion 20Y on the peripheral region 10 side of the trench isolation structure 20.

The multiple first L-shaped intersections 91 (not shown) face the boundary wiring 42 and boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2. The multiple second L-shaped intersections 91QB face the first peripheral wiring 43 and peripheral well region 56 in the thickness direction of the semiconductor chip 2.

12B, the L-shaped intersection 91Q has one corner 92Q. The curvature index of the corner 92Q is 1.5 μm or more and 2.4 μm or less. The curvature index CI _P is the curvature index CI of the corner 92Q (see FIG. 13).

At the L-shaped intersection 91Q, a ratio (CI _Q /W ₁ ) of the curvature index CI _Q of the corner 92Q to the first width W ₁ of the isolation trench 21 is 1.5 or more and 2.4 or less. At the L-shaped intersection 91Q, a ratio (CI _Q /W ₂ ) of the curvature index CI _Q of the corner 92Q to the second width W ₂ of the multiple gate trenches 31 is 1.5 or more and 2.4 or less. At the L-shaped intersection 91Q, a ratio (CI _Q /P) of the curvature index CI _Q of the corner 92P to the pitch P of the multiple gate trenches 31 is 0.1 or more and 0.16 or less. In the L-shaped intersection 91Q, the ratio (CI _Q /W ₅ ) of the curvature index CI _Q of the corner 92Q to the fifth width W ₅ of the mesa portion 90 is not less than 0.11 and not more than 0.17.

As shown in Figures 6, 7, and 12A, the semiconductor device 1 includes a main surface insulating film 39 that covers the first main surface 3. The thickness of the main surface insulating film 39 is, for example, 50 nm or more and 200 nm or less.

The main surface insulating film 39 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. It is preferable that the main surface insulating film 39 has a single-layer structure made of a single insulating film. It is particularly preferable that the main surface insulating film 39 includes a silicon oxide film made of an oxide of the semiconductor chip 2. In this embodiment, the main surface insulating film 39 is made of the same insulating film as the gate insulating film 32.

As shown in Figures 6, 7 and 12A, the main surface insulating film 39 extends in the form of a film along the first main surface 3 so as to cover the multiple IGBT regions 6, the boundary region 7 and the peripheral region 10. The main surface insulating film 39 may be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the semiconductor chip 2.

As shown in Figures 6 and 7, the main surface insulating film 39 covers the first main surface 3 so as to expose the multiple trench isolation structures 20 and the multiple trench structures 30. Specifically, the main surface insulating film 39 is connected to the isolation insulating film 22 and the gate insulating film 32, and exposes the isolation buried electrode 23 and the gate buried electrode 33.

As shown in FIG. 7, the semiconductor device 1 includes a gate wiring 40 disposed on the first main surface 3 of the semiconductor chip 2. Specifically, the gate wiring 40 is disposed in the form of a film on the main surface insulating film 39. In this embodiment, the gate wiring 40 is made of a conductive polysilicon film.

As shown in FIG. 3, the gate wiring 40 is routed at least in the boundary region 7. In this embodiment, the gate wiring 40 is routed in the boundary region 7 and the outer peripheral region 10 in an arbitrary layout. Specifically, the gate wiring 40 includes a pad wiring 41, a boundary wiring 42, a first outer peripheral wiring 43, and a second outer peripheral wiring 44. The pad wiring 41 is disposed on the first boundary region 8 of the boundary region 7, and has a relatively large first wiring width in the second direction Y. In this embodiment, the pad wiring 41 is formed in a quadrangular shape in a plan view. The pad wiring 41 has a width in the second direction Y that is larger than the width of the boundary region 7 (the width of the first boundary region 8). The pad wiring 41 is drawn out from above the boundary region 7 onto a plurality of trench isolation structures 20 adjacent in the second direction Y.

As shown in FIG. 3, in this embodiment, the pad wiring 41 is drawn out from above the boundary region 7 onto the multiple IGBT regions 6. As a result, the pad wiring 41 is mechanically and electrically connected to the isolated buried electrode 23 and the multiple gate buried electrodes 33, and transmits the gate potential to the isolated buried electrode 23 and the gate buried electrode 33. In this embodiment, the pad wiring 41 is formed integrally with the isolated buried electrode 23 and the multiple gate buried electrodes 33.

As shown in Figures 3 and 4, the boundary wiring 42 is drawn from the pad wiring 41 onto the second boundary region 9 of the boundary region 7, and has a second wiring width in the second direction Y that is smaller than the first wiring width of the pad wiring 41. The boundary wiring 42 is formed in a band shape extending in the first direction X. In this embodiment, the boundary wiring 42 crosses the center of the semiconductor chip 2. The boundary wiring 42 has a width in the second direction Y that is larger than the width of the boundary region 7 (the width of the second boundary region 9). The boundary wiring 42 is drawn from above the boundary region 7 onto a plurality of trench isolation structures 20 adjacent in the second direction Y.

As shown in FIG. 4, in this embodiment, the boundary wiring 42 is drawn from above the boundary region 7 to above the multiple IGBT regions 6 so as to cover the first ends 30A of the multiple trench structures 30. As a result, the boundary wiring 42 is mechanically and electrically connected to the isolated buried electrode 23 and the multiple gate buried electrodes 33, and transmits the gate potential to the isolated buried electrode 23 and the gate buried electrode 33. In this embodiment, the boundary wiring 42 is formed integrally with the isolated buried electrode 23 and the multiple gate buried electrodes 33.

As shown in FIG. 3, the first peripheral wiring 43 is pulled out from the pad wiring 41 onto the peripheral region 10 and is formed in a band extending along the first side surface 5A and the third side surface 5C. The first peripheral wiring 43 may have a portion that extends in a band along the fourth side surface 5D. The first peripheral wiring 43 has a portion that is pulled out from above the peripheral region 10 onto the first trench isolation structure 20A in the portion that extends along the first side surface 5A. As shown in FIG. 11, in this embodiment, the first peripheral wiring 43 also covers the second ends 30B of the multiple trench structures 30 in the first IGBT region 6A.

As a result, the first peripheral wiring 43 is mechanically and electrically connected to the isolated buried electrode 23 and the multiple gate buried electrodes 33. In this embodiment, the first peripheral wiring 43 is formed integrally with the isolated buried electrode 23 and the multiple gate buried electrodes 33. The first peripheral wiring 43 transmits the gate potential from the peripheral region 10 side to the isolated buried electrode 23 and the gate buried electrode 33.

As shown in FIG. 3, the second peripheral wiring 44 is pulled out from the pad wiring 41 onto the peripheral region 10 and is formed in a band extending along the second side surface 5B and the third side surface 5C. The second peripheral wiring 44 may have a portion that extends in a band along the fourth side surface 5D. The second peripheral wiring 44 has a portion that is pulled out from above the peripheral region 10 onto the second trench isolation structure 20B in the portion that extends along the second side surface 5B. Although not shown, in this embodiment, the second peripheral wiring 44 also covers the second ends 30B of the multiple trench structures 30 in the second IGBT region 6B.

As a result, the second peripheral wiring 44 is mechanically and electrically connected to the isolated buried electrode 23 and the multiple gate buried electrodes 33. In this embodiment, the second peripheral wiring 44 is formed integrally with the isolated buried electrode 23 and the multiple gate buried electrodes 33. The second peripheral wiring 44 transmits the gate potential from the peripheral region 10 side to the isolated buried electrode 23 and the gate buried electrode 33.

The semiconductor device 1 further includes an interlayer insulating film 60 that covers the main surface insulating film 39. The interlayer insulating film 60 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film. The interlayer insulating film 60 may include at least one of an NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film, which are examples of silicon oxide films. The interlayer insulating film 60 may have a single-layer structure made of a single insulating film, or a layered structure including multiple insulating films. The interlayer insulating film 60 has a thickness that exceeds the thickness of the main surface insulating film 39. The thickness of the interlayer insulating film 60 is, for example, 1.0 μm or more and 2.5 μm or less.

As shown in Figures 6, 7 and 12A, the interlayer insulating film 60 may extend in a layered manner along the first main surface 3 and be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the semiconductor chip 2. The interlayer insulating film 60 selectively covers the multiple IGBT regions 6, the boundary region 7 and the peripheral region 10. The interlayer insulating film 60 covers the main surface insulating film 39, the multiple trench isolation structures 20 and the multiple trench structures 30 in each IGBT region 6. The interlayer insulating film 60 covers the main surface insulating film 39 and the gate wiring 40 in the boundary region 7 and the peripheral region 10.

As shown in FIG. 6, the interlayer insulating film 60 has a plurality of contact openings 61 that expose a plurality of emitter regions 35 in each IGBT region 6. In this embodiment, the plurality of contact openings 61 are formed in a one-to-one correspondence with the plurality of contact holes 37, and each communicates with the corresponding contact hole 37. The plurality of contact openings 61 are each formed in a band shape extending along the corresponding contact hole 37 in a plan view.

The interlayer insulating film 60 includes at least one gate opening that selectively exposes the gate wiring 40 in the boundary region 7 and/or the peripheral region 10. In this embodiment, the gate opening may expose the boundary wiring 42, the first peripheral wiring 43, and the second peripheral wiring 44. FIG. 12A shows only the gate opening 62 that exposes the first peripheral wiring 43.

12A, the interlayer insulating film 60 includes at least one (in this embodiment, multiple) first well openings 63 that selectively expose the inner edge of the peripheral well region 56 in the peripheral region 10. Specifically, the multiple first well openings 63 expose the inner edge of the peripheral well region 56 in the region between the multiple trench isolation structures 20 and the gate wiring 40.

As shown in FIG. 12A, the interlayer insulating film 60 includes at least one (one in this embodiment) second well opening 64 that selectively exposes the outer edge of the peripheral well region 56 in the peripheral region 10. Specifically, the second well opening 64 exposes the outer edge of the peripheral well region 56 in a region closer to the peripheral side of the first main surface 3 than the gate wiring 40. The second well opening 64 is formed in a band shape extending along the multiple IGBT regions 6. In this embodiment, the second well opening 64 is formed in a square ring shape surrounding the multiple IGBT regions 6.

As shown in FIG. 7, the interlayer insulating film 60 includes at least one (two in this embodiment) boundary gate opening 81 (see also FIG. 4) that exposes the boundary wiring 42 of the gate wiring 40. In this embodiment, the multiple boundary gate openings 81 are each formed in a strip extending in the first direction X and are formed at intervals in the second direction Y. The planar shape of the boundary gate opening 81 is arbitrary. The boundary gate opening 81 may be formed in a circular, elliptical, rectangular or polygonal shape in a planar view. The multiple boundary gate openings 81 may be arranged at intervals in the first direction X. In addition, the number of boundary gate openings 81 is arbitrary.

As shown in Figures 4, 6 and 12A, the semiconductor device 1 includes a plurality of via electrodes 70 embedded in the interlayer insulating film 60 so as to be electrically connected to the plurality of emitter regions 35. Specifically, the plurality of via electrodes 70 are embedded in a plurality of contact openings 61 in the interlayer insulating film 60. The plurality of via electrodes 70 include a portion in contact with the semiconductor chip 2 and a portion in contact with the interlayer insulating film 60. The plurality of via electrodes 70 are electrically connected to the emitter regions 35 and the contact regions 38 in the portion in contact with the semiconductor chip 2.

Each via electrode 70 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The Ti-based metal may include at least one of a pure Ti film (a Ti film having a purity of 99% or more) and a Ti alloy film. The Ti alloy film may be a TiN film. The W-based metal may include at least one of a pure W film (a W film having a purity of 99% or more) and a W alloy film. The Al-based metal may include at least one of a pure Al film (an Al film having a purity of 99% or more) and an Al alloy film. The Al alloy film may include at least one of an AlCu alloy, an AlSi alloy, and an AlSiCu alloy. The Cu-based metal may include at least one of a pure Cu film (a Cu film having a purity of 99% or more) and a Cu alloy film. Each via electrode 70 may have a layered structure including a Ti-based metal film and a W-based metal film.

7, the semiconductor device 1 includes a plurality of gate via electrodes 82 embedded in a plurality of boundary gate openings 81 so as to be mechanically and electrically connected to the boundary wiring 42. Each gate via electrode 82 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. Each gate via electrode 82 may have a layered structure including a Ti-based metal film and a W-based metal film, similar to the via electrode 70. The multiple gate via electrodes 82 preferably face the gate wiring 40 (boundary wiring 42) and the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2.

As shown in FIG. 1 and FIG. 2, the semiconductor device 1 includes a gate electrode 71 disposed on the interlayer insulating film 60 so as to be electrically connected to the gate wiring 40. The gate electrode 71 is made of a conductive material different from that of the gate wiring 40. In this embodiment, the gate electrode 71 is made of a metal film and has a lower resistance value than the gate wiring 40. The gate electrode 71 may be referred to as a "gate metal." The gate electrode 71 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The gate electrode 71 may have a layered structure including a Ti-based metal film and an Al-based metal film.

As shown in Figures 1 and 3, the gate electrode 71 is disposed directly above the gate wiring 40. The gate electrode 71 can be routed in any layout to any of the multiple IGBT regions 6, the boundary region 7, and the peripheral region 10 depending on the layout of the gate wiring 40. In this embodiment, the gate electrode 71 includes a gate pad electrode 72, a first gate finger electrode 73, a second gate finger electrode 74, and a boundary gate finger electrode 83.

For example, a capacitor is formed by a gate electrode 71 and an IGBT structure Tr facing the gate electrode 71 via an interlayer insulating film 60. The capacitance of the capacitor as a whole gate (gate capacitance) is 300 pF or less.

As shown in Figures 1 and 3, the gate pad electrode 72 is disposed directly above the pad wiring 41 of the gate wiring 40. The gate pad electrode 72 enters the gate opening (not shown) from above the interlayer insulating film 60 and is electrically connected to the pad wiring 41. In this embodiment, the gate pad electrode 72 is formed in a rectangular shape in a plan view.

As shown in Figures 1 and 3, the gate pad electrode 72 faces the first boundary well region 51 of the boundary well region 50 in the thickness direction of the semiconductor chip 2. The gate pad electrode 72 is preferably formed spaced apart from the trench isolation structure 20 and the multiple trench structures 30 in a plan view. The gate pad electrode 72 preferably has a planar area smaller than the planar area of the first boundary well region 51 of the boundary well region 50. It is particularly preferable that the gate pad electrode 72 has a planar area smaller than the planar area of the pad wiring 41.

As shown in Figures 1 and 3, the first gate finger electrode 73 is drawn out from the gate pad electrode 72 directly above the first outer peripheral wiring 43. The first gate finger electrode 73 is formed in a band shape extending along the first outer peripheral wiring 43. In this embodiment, the first gate finger electrode 73 extends in a band shape along the first side surface 5A and the third side surface 5C.

As shown in FIG. 12A, the first gate finger electrode 73 enters the gate opening 62 from above the interlayer insulating film 60 and is electrically connected to the first peripheral wiring 43. The first gate finger electrode 73 faces the peripheral well region 56 in the thickness direction of the semiconductor chip 2. The first gate finger electrode 73 is preferably formed at a distance from the trench isolation structure 20 and the multiple trench structures 30 in a plan view.

As shown in Figures 1 and 3, the second gate finger electrode 74 is drawn out from the gate pad electrode 72 directly above the second peripheral wiring 44. The second gate finger electrode 74 is formed in a band shape extending along the second peripheral wiring 44. In this embodiment, the second gate finger electrode 74 extends in a band shape along the second side surface 5B and the third side surface 5C.

The second gate finger electrode 74 is electrically connected to the second peripheral wiring 44 through a gate opening (not shown) from above the interlayer insulating film 60. If a via electrode similar to the via electrode 70 is embedded in the gate opening, the second gate finger electrode 74 may be electrically connected to the second peripheral wiring 44 through the via electrode.

The second gate finger electrode 74 faces the peripheral well region 56 in the thickness direction of the semiconductor chip 2. It is preferable that the second gate finger electrode 74 is formed at a distance from the trench isolation structure 20 and the multiple trench structures 30 in a plan view.

As shown in Figures 1 and 3, the boundary gate finger electrode 83 is drawn out from the gate pad electrode 72 directly above the boundary wiring 42. The boundary gate finger electrode 83 is formed in a strip shape extending along the boundary wiring 42 so as to cover the multiple gate via electrodes 82.

As shown in FIG. 7, the boundary gate finger electrode 83 is electrically connected to the boundary wiring 42 through a plurality of gate via electrodes 82. The boundary gate finger electrode 83 faces the gate wiring 40 (boundary wiring 42) and the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2.

As shown in Figures 4 and 7, in the second direction Y, the boundary gate finger electrode 83 has a width smaller than the width of the boundary well region 50, and has a periphery located on the boundary region 7 side of the periphery of the boundary well region 50. Specifically, the boundary gate finger electrode 83 has a width smaller than the width of the boundary wiring 42, and has a periphery located on the boundary region 7 side of the periphery of the boundary wiring 42. In this embodiment, the boundary gate finger electrode 83 has a width smaller than the width of the boundary region 7, and has a periphery located inward from the periphery of the boundary region 7.

As shown in FIG. 4, the boundary gate finger electrode 83 is disposed only directly above the boundary region 7 in a plan view, and is not disposed above each IGBT region 6. Specifically, the boundary gate finger electrode 83 is disposed above the boundary region 7 at a distance from the multiple trench structures 30 of the first IGBT region 6A and the multiple trench structures 30 of the second IGBT region 6B in a plan view. The boundary gate finger electrode 83 is disposed above the boundary region 7 at a distance from the first trench isolation structure 20A and the second trench isolation structure 20B in a plan view.

Referring to FIG. 1, the semiconductor device 1 includes an emitter electrode 75 disposed on the interlayer insulating film 60 at a distance from the gate wiring 40. The emitter electrode 75 is made of a conductive material different from that of the gate wiring 40. In this embodiment, the emitter electrode 75 is made of a metal film. The emitter electrode 75 may be referred to as an "emitter metal." The emitter electrode 75 may include at least one of a Ti-based metal film, a W-based metal film, an Al-based metal film, and a Cu-based metal film. The emitter electrode 75 may have a layered structure including a Ti-based metal film and an Al-based metal film.

As shown in Figures 6, 7 and 12A, the emitter electrode 75 is disposed on the interlayer insulating film 60 so as to cover the multiple IGBT regions 6. The emitter electrode 75 collectively covers the multiple via electrodes 70, and is electrically connected to the multiple emitter regions 35 via the multiple via electrodes 70. In this embodiment, the emitter electrode 75 has a portion that covers the boundary wiring 42 of the gate wiring 40 with the interlayer insulating film 60 in between. In other words, the emitter electrode 75 has a portion that faces the gate wiring 40 (boundary wiring 42) and the boundary well region 50 in the thickness direction of the semiconductor chip 2.

As shown in Figures 1 and 2, in this embodiment, the emitter electrode 75 includes an emitter pad electrode 76 and an emitter finger electrode 77. The emitter pad electrode 76 covers the multiple IGBT regions 6 and the boundary region 7.

As shown in FIG. 6, the emitter pad electrode 76 faces the gate wiring 40 across the interlayer insulating film 60, and is electrically connected to the multiple emitter regions 35 through multiple via electrodes 70. As shown in FIG. 12A, the emitter pad electrode 76 extends into the first well opening 63 from above the interlayer insulating film 60. The emitter pad electrode 76 is electrically connected to the inner edge of the outer periphery well region 56 within the first well opening 63.

As shown in Figures 1 and 2, the emitter finger electrode 77 is drawn out from the emitter pad electrode 76 to the region between the periphery of the first main surface 3 and the gate electrode 71, and extends in a strip shape along the gate electrode 71. In this embodiment, the emitter finger electrode 77 is formed in a square ring shape surrounding the gate electrode 71 and the emitter pad electrode 76. As shown in Figure 11A, the emitter finger electrode 77 extends from above the interlayer insulating film 60 into the second well opening 64. The emitter finger electrode 77 is electrically connected to the outer edge of the second well opening 64.

As shown in Figures 1 and 4, in this embodiment, the emitter electrode 75 has a cutout portion 84 that extends in a band shape along the boundary gate finger electrode 83 in a plan view. The cutout portion 84 defines a slit 85 that extends in a band shape along the boundary gate finger electrode 83 between the emitter electrode 75 and the boundary gate finger electrode 83. The slit 85 is formed directly above the boundary well region 50 in a plan view. It is preferable that the slit 85 is formed directly above the boundary region 7 in a plan view.

As shown in FIG. 4, in this embodiment, the slit 85 is formed on the boundary region 7 at a distance from the multiple trench structures 30 of the first IGBT region 6A and the multiple trench structures 30 of the second IGBT region 6B. The slit 85 is also formed on the boundary region 7 at a distance from the first trench isolation structure 20A and the second trench isolation structure 20B in a plan view. The slit 85 may face the boundary well region 50 (second boundary well region 52) in the thickness direction of the semiconductor chip 2.

As shown in Figures 6, 7 and 12A, the semiconductor device 1 includes a collector electrode 80 covering the second main surface 4. The collector electrode 80 is electrically connected to the collector region 13 exposed from the second main surface 4. The collector electrode 80 forms an ohmic contact with the collector region 13. The collector electrode 80 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the semiconductor chip 2.

The collector electrode 80 may include at least one of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film. The collector electrode 80 may have a single film structure including a Ti film, a Ni film, an Au film, an Ag film, or an Al film. The collector electrode 80 may have a laminated structure in which at least two of a Ti film, a Ni film, a Pd film, an Au film, an Ag film, and an Al film are laminated in any manner. The collector electrode 80 preferably includes at least a Ti film that directly covers the second main surface 4. The collector electrode 80 may have a laminated structure including, for example, a Ti film, a Ni film, a Pd film, and an Au film laminated in this order from the second main surface 4 side.

FIGS. 14A to 22A and 14B to 22B are diagrams showing a part of the manufacturing process of semiconductor device 1 in the order of steps. FIG. 23 is a diagram for explaining the patterning mask PM. FIGS. 14A to 22A are longitudinal cross-sectional views of a portion corresponding to FIG. 8. FIGS. 14B to 22B are longitudinal cross-sectional views of a portion corresponding to FIG. 9. Note that, among the reference symbols shown in FIGS. 8 and 9, only the reference symbols of the configurations necessary for explaining the manufacturing process of semiconductor device 1 are shown in FIGS. 14A to 22A and 14B to 22B, and other reference symbols are omitted.

14A and 14B, in manufacturing the semiconductor device 1, first, an n ^- type semiconductor wafer 101 is prepared. The semiconductor wafer 101 has a first wafer main surface 103. The first wafer main surface 103 of the semiconductor wafer 101 corresponds to the first main surface 3 of the semiconductor chip 2.

Next, as shown in Figures 14A and 14B, a p-type boundary well region 50 is formed on the first wafer main surface 103. A p-type peripheral well region 56 (see Figure 11) may be formed simultaneously with the boundary well region 50.

Next, as shown in Figures 15A, 15B, 16A and 16B, isolation trenches 21 and gate trenches 31 are formed in the first wafer main surface 103. In this process, first, as shown in Figures 15A and 15B, resist 104 is applied onto the first wafer main surface 103 of the semiconductor wafer 101, and a patterning mask (virtual figure) PM is placed on the resist 104. The patterning mask PM has a predetermined opening pattern OP.

23, the opening pattern OP of the patterning mask PM includes a first linear portion 98 and a second linear portion 99 which are perpendicular to each other, and a chamfered portion 100 which is inclined at an angle of 45° with respect to the first linear portion 98 and the second linear portion 99. The chamfered portion 100 has a predetermined chamfer width _WF .

The straight line portion 98 corresponds to the first side 93 (see FIG. 13) of the corner (corner 92P of the T-shaped intersection 91P, corner 92Q of the L-shaped intersection 91Q). The straight line portion 99 corresponds to the second side 94 (see FIG. 13) of the corner (corner 92P, corner 92Q).

There is a correlation between the chamfer width _WF of the patterning mask PM and the curvature indices CI (curvature indices CI _P and CI _Q ) of the corners (92P and 92Q) formed using the patterning mask PM.

For example, a chamfer width W _F =0.4 μm corresponds to a curvature index CI=1.45 μm, a chamfer width W _F =0.5 μm corresponds to a curvature index CI=1.73 μm, and a chamfer width W _F =0.7 μm corresponds to a curvature index CI=2.44 μm.

The resist 104 is exposed to light (e.g., ultraviolet light) through the patterning mask PM, and the portions of the resist 104 exposed through the opening pattern OP are removed. As a result, as shown in Figures 16A and 16B, a second resist mask 105 is formed having openings 105a in the same pattern as the opening pattern OP of the patterning mask PM. The openings 105a of the second resist mask 105 are openings that expose the regions where the isolation trench 21 and the gate trench 31 are to be formed. After the resist 104 is removed, the patterning mask PM is retracted from above the first wafer main surface 103 of the semiconductor wafer 101.

Next, as shown in Figures 17A and 17B, unnecessary portions of the semiconductor wafer 101 are removed by etching through the second resist mask 105. The etching may be a wet etching method. As a result, the isolation trench 21 and the gate trench 31 are formed in the semiconductor wafer 101. Thereafter, the second resist mask 105 is removed.

Next, as shown in Figures 18A and 18B, a first recess 96 and a second recess 97 are formed at the opening ends 21d, 21e of the isolation trench 21 and the opening ends 31d, 31e of the gate trench 31, respectively. In this process, a third resist mask 106 having a predetermined pattern is first formed on the first wafer main surface 103. The third resist mask 106 has a number of openings 106a that expose the regions in which the first recess 96 and the second recess 97 are to be formed.

Next, unnecessary portions of the semiconductor wafer 101 are removed by etching via the third resist mask 106 (TCE process (Top Corner Etching process)). The etching process may be a dry etching process. By the TCE process, a first recess 96 and a second recess 97 are formed in the isolation trench 21 and the gate trench 31, respectively. The TCE process time is preferably 30 minutes or more. The process time of the TCE process is set so that the third width W ₃ (see FIG. 8) of the first recess 96 of the isolation trench 21 and the fourth width W ₄ (see FIG. 10) of the gate trench 31 and the second recess 97 are sufficiently wide. After completion of the TCE process, the third resist mask 106 is removed.

Next, as shown in Figures 19A and 19B, a p-type boundary well region 50 is diffused into the semiconductor wafer 101. The boundary well region 50 is diffused to a depth position that covers the bottom wall of the isolation trench 21.

Next, as shown in Figures 19A and 19B, the isolation insulating film 22, the gate insulating film 32, and the main surface insulating film 39 are formed on the first wafer main surface 103. The isolation insulating film 22, the gate insulating film 32, and the main surface insulating film 39 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (e.g., a thermal oxidation treatment method).

Next, as shown in Figures 19A, 19B, 20A and 20B, the isolation buried electrode 23, the boundary wiring 42 and the gate buried electrode 33 are formed. First, the base electrode layer 107 is deposited on the first wafer main surface 103. The base electrode layer 107 includes conductive polysilicon. The base electrode layer 107 may be formed by a CVD method.

Next, as shown in Figures 20A and 20B, unnecessary portions of the base electrode layer 107 are removed. In this process, a resist mask (not shown) having a predetermined pattern is first formed. The resist mask covers the areas where the boundary wiring 42 and the buried gate electrode 33 are to be formed, and has openings that expose areas other than these areas. Next, the unnecessary portions of the base electrode layer 107 are removed by etching through the resist mask. The etching method may be wet etching. As a result, the boundary wiring 42 and the buried gate electrode 33 are formed.

Next, as shown in Figures 21A and 21B, n-type impurities are introduced into the semiconductor wafer 101 through an ion introduction mask, and thus, a plurality of carrier storage regions 36 are formed in the surface layer portion of the semiconductor wafer 101. The ion introduction mask is then removed. Next, p-type impurities are introduced into the first wafer main surface 103 of the semiconductor wafer 101 through the ion introduction mask. As a result, a plurality of base regions 25 are formed in the surface layer portion of the semiconductor wafer 101. The ion introduction mask is then removed. Next, n-type impurities are introduced into the first wafer main surface 103 of the semiconductor wafer 101 through the ion introduction mask. As a result, a plurality of emitter regions 35 are formed in the surface layer portion of the semiconductor wafer 101. The ion introduction mask is then removed.

Next, as shown in Figures 22A and 22B, an interlayer insulating film 60 is formed on the first wafer main surface 103. Thereafter, a gate electrode 71, an emitter electrode 75, and the like are formed on the first wafer main surface 103. Through the process including the above, a semiconductor device 1 is obtained.

Next, the first destructive test will be described. As the semiconductor device 1 to be tested in the first destructive test, the following Examples 1 and 2 and Reference Examples 1 to 4 were adopted.
<Examples 1 and 2>
The semiconductor device 1 shown in Figures 1 to 3 was manufactured by the manufacturing method shown in Figures 14A to 22A and Figures 14B to 22B. In Examples 1 and 2, the chamfer width WF of the patterning mask PM used to manufacture the corner _92P (see Figure 5) of the T-shaped intersection 91P and the corner 92Q (see Figure 12B) of the L-shaped intersection 91Q was 0.4 μm (Example 1) and 0.5 μm (Example 2). When the chamfer width _WF is 0.4 μm, the curvature index CI (see Figure 13) is 1.45 μm. When the chamfer width _WF is 0.5 μm, the curvature index CI is 1.73 μm.

In Examples 1 and 2, the first width W ₁ (see FIG. 8 ) of the isolation trench 21 is 1.0 μm, and the second width W ₂ (see FIG. 10 ) of the gate trench 31 is 1.0 μm. The first recess 96 (see FIG. 8 ) is not formed at the opening ends 21 d, 21 e of the isolation trench 21. The second recess 97 (see FIG. 10 ) is not formed at the opening ends 31 d, 31 e of the gate trench 31.
<Reference Examples 1 to 4>
In Reference Examples 1 to 4, the chamfer width _WF of the patterning mask PM used in the manufacture of the semiconductor device 1 was set to 0.0 μm (Reference Example 1), 0.1 μm (Reference Example 2), 0.2 μm (Reference Example 3), and 0.3 μm (Reference Example 4). When the chamfer width _WF is 0.0 μm, the patterning mask PM is not chamfered. When the chamfer width _WF is 0.0 μm, the curvature index CI (see FIG. 13) is 0.76 μm. That is, even if the patterning mask PM is not chamfered, the corners (corner 92P, corner 92Q) (see FIG. 5 and FIG. 12B) of the T-shaped intersections 91P, 91Q are rounded. If the patterning mask PM is chamfered, the curvature of the corners (corner 92P, corner 92Q) becomes gentle. When the chamfer width _WF is 0.1 μm, the curvature index CI is 0.86 μm. When the chamfer width _WF is 0.2 μm, the curvature index CI is 1.02 μm. When the chamfer width _WF is 0.3 μm, the curvature index CI is 1.20 μm.

From the above, the graph of Fig. 23 is obtained as a relationship between the chamfer width _WF of the patterning mask PM and the curvature index CI. From Fig. 23, it can be seen that by increasing the chamfer width _WF of the patterning mask PM, the curvature index CI also increases quadratically. In other words, by appropriately adjusting the chamfer width _WF of the patterning mask PM, the curvature index CI of the corner 92P of the T-shaped intersection 91P and the corner 92Q of the L-shaped intersection 91Q can be freely changed.

Next, as a first breakdown test, an electrostatic breakdown withstand test (ESD test) to measure electrostatic breakdown withstand capability (ESD withstand capability) and a time-zero dielectric breakdown withstand test (TZDB test) to measure time-zero dielectric breakdown withstand capability were performed on Examples 1 and 2 and Reference Examples 1 to 4.

In the electrostatic breakdown resistance test (ESD test), three samples each corresponding to Examples 1 and 2 and Reference Examples 1 to 4 were prepared, and the breakdown voltage BV was measured for each. The breakdown voltage is the voltage at which the semiconductor device 1 breaks down, and is measured by increasing the collector voltage from 0V to the voltage at which the semiconductor device 1 breaks down, with the emitter voltage at 0V and the gate voltage at 0V. In this embodiment, the electrostatic breakdown resistance test is an HBM (Human Body Model) test. The electrostatic breakdown resistance of the semiconductor device 1 is measured when a charged human body comes into contact with the semiconductor device 1 used as the sample for this test.

The results of the electrostatic breakdown resistance test are shown in Figure 25. In Figure 25, the breakdown voltage value is expressed as a relative value when the reference voltage value is set to 1. In Figure 25, Samples 1 to 3 correspond to Reference Example 1, Samples 4 to 6 correspond to Reference Example 2, Samples 7 to 9 correspond to Reference Example 3, and Samples 10 to 12 correspond to Reference Example 4. Also in Figure 25, Samples 13 to 15 correspond to Example 1, and Samples 16 to 18 correspond to Example 2.

From the test results shown in FIG. 25, it can be seen that Examples 1 and 2 have higher breakdown voltage values than Reference Examples 1 to 4. In other words, it can be seen that Examples 1 and 2 have high electrostatic breakdown resistance. This shows that when the curvature index CI (see FIG. 13) is 1.5 μm or more, the electrostatic breakdown resistance of the semiconductor device 1 is high.

In the time-zero dielectric breakdown test (TZDB test), the measurement targets were semiconductor devices 1 arranged at various locations on the surface of a circular wafer W. The applied voltage (V _ge ) during the measurement was 80 V. The semiconductors measured were Examples 1 and 2 and Reference Examples 1 to 4.

The test results of the time-zero dielectric strength breakdown test are shown in Figures 26A to 26C and 27A to 27C. In Figures 26A to 26C and 27A to 27C, the parts of the wafer W where chips through which leakage currents larger than the reference value flow are present are shown as solid rectangles (destructive areas), and the parts of the wafer W where chips through which leakage currents smaller than the reference value flow are present are shown as open rectangles. In the chips present in the parts shown as solid rectangles, it is believed that the semiconductor device experienced dielectric breakdown during the time-zero dielectric strength breakdown test.

The test results shown in Figures 26A to 26B and Figures 27A to 27C show that Examples 1 and 2 have high dielectric breakdown resistance. This shows that when the curvature index CI of the semiconductor device 1 is 1.5 μm or more, the dielectric breakdown resistance is high.

Next, the second destructive test will be described. As the semiconductor device 1 to be tested in the second destructive test, the following examples 3 and 4 and reference example 5 were adopted.
<Examples 3 and 4>
1 to 3 were fabricated by the manufacturing process shown in Figures 14A to 22A and 14B to 22B. In Examples 1 and 2, the processing time of the TCE treatment was 30 seconds (Example 3) and 45 seconds (Example 4), respectively. When the processing time of the TCE treatment was 30 seconds, the third width W ₃ of the first recess 96 (see Figure 8) and the fourth width W ₄ of the second recess 97 (see Figure 10) were 1368 Å.

At this time, the third depth _D3 (see FIG. 8) and the fourth depth _D4 (see FIG. 10) are 1838 Å. When the processing time of the TCE processing is 45 seconds, the third width _W3 and the fourth width _W4 are 2176 Å. At this time, the third depth _D3 and the fourth depth _D4 are 2849 Å.

From the above, the graph in Fig. 28 is obtained as a relationship between the processing time of the TCE process and the amount of side etching of the trench. It can be seen from Fig. 28 that by increasing the processing time of the TCE process, the amount of side etching and the depth of the recess at the opening end of the trench also increase proportionally. In other words, by appropriately adjusting the processing time of the TCE process, the third width _W3 and the third depth _D3 of the first recess 96 and the fourth width _W4 and the fourth depth _D4 of the second recess 97 can be freely changed.

In Examples 3 and 4, the first width W ₁ (see FIG. 8) of the isolation trench 21 is 1.0 μm, and the second width W ₂ (see FIG. 10) of the gate trench 31 is 1.0 μm. The pitch P (see FIG. 6) is 15 μm. The width W ₅ (see FIG. 4) of the mesa portion 90 is 10 μm. The curvature index CI (see FIG. 13) of the corners (corner 92P, corner 92Q) is 0.76 μm (corresponding to a chamfer width W _F =0.0 μm).
<Reference Example 5>
In Reference Example 5, the processing time of the TCE processing was 15 seconds. When the processing time of the TCE processing was 15 seconds, the third width W ₃ of the first recess 96 (see FIG. 8 ) and the fourth width W ₄ of the second recess 97 (see FIG. 10 ) were 532 Å. At this time, the third depth D ₃ (see FIG. 8 ) and the fourth depth D ₄ (see FIG. 10 ) were 828 Å.

Next, a time-zero dielectric breakdown test (TZDB test) for measuring the time-zero dielectric breakdown resistance was carried out as a second breakdown test for Examples 3 and 4 and Reference Example 5. The applied voltage (Vge) was started from 78 V and gradually increased. In Reference Example 5, breakdown started at an applied voltage _Vge of 80 V, so no measurement was performed at voltages higher than this.

The test results of the time-zero dielectric breakdown test (TZDB test) are shown in Figures 29A to 29C, 30A, 30B, 31A, and 31B.

29A to 29C show the test results when the applied voltage _Vge is 80 V. Figures 30A to 30C show the test results when the applied voltage _Vge is 84 V. Figures 31A to 31C show the test results when the applied voltage _Vge is 86 V.

In Figures 29A to 29C, 30A, 30B, 31A and 31B, the parts of the wafer W where chips through which leakage currents larger than the reference value flow are shown as solid rectangles (destructive areas), and the parts of the wafer W where chips through which leakage currents smaller than the reference value flow are shown as open rectangles (non-destructive areas). In the chips that exist in the parts shown as solid rectangles, it is believed that the semiconductor device experienced dielectric breakdown during the time-zero dielectric strength breakdown test.

29 to 31 show that the dielectric breakdown resistance is high in Examples 3 and 4. This shows that the dielectric breakdown resistance is high when the third width W ₃ (see FIG. 8) and the fourth width W ₄ (see FIG. 10) are 1350 Å or more.

The IGBT structure Tr includes many T-shaped intersections 91P. Electric fields tend to concentrate at the T-shaped intersections 91P. As a result, the semiconductor chip 2 may be destroyed starting from the T-shaped intersections 91P. For this reason, the semiconductor device 1 is required to have high electrostatic discharge (ESD) resistance.

In general, as the chip size of the semiconductor chip 2 increases or as the gate capacitance increases, the electrostatic breakdown resistance tends to increase. However, regardless of the chip size or gate capacitance of the semiconductor chip 2, a high electrostatic breakdown resistance is now required of the semiconductor device 1. Furthermore, the semiconductor device 1 is required to have not only a high electrostatic breakdown resistance but also a high dielectric breakdown.

According to this embodiment, the curvature index CI _P of the corner 92P of the T-shaped intersection 91P is 1.5 μm or more. Therefore, it is possible to reduce the occurrence of electric field concentration at the corner 92P of the T-shaped intersection 91P and to suppress the current concentration at the corner 92P of the T-shaped intersection 91P. This makes it possible to suppress the occurrence of breakdown at the T-shaped intersection 91P.

In addition, the curvature index CI _P of the corner 92P of the T-shaped intersection 91P is 2.4 μm or less. Therefore, the embeddability of the isolation buried electrode 23 in the isolation trench 21 and the embeddability of the gate buried electrode 33 in the gate trench 31 are not impaired. In other words, the occurrence of destruction at the T-shaped intersection 91P can be suppressed without impairing the embeddability of the buried electrodes 23, 33.

In addition, the curvature index CI _Q of the corner 92Q of the L-shaped intersection 91Q is 1.5 μm or more. This can reduce the occurrence of electric field concentration at the corner 92Q of the L-shaped intersection 91Q. This can prevent current from concentrating at the corner 92Q of the L-shaped intersection 91Q. This can prevent breakdown at the L-shaped intersection 91Q.

In addition, the curvature index _CIQ of the corner 92Q of the L-shaped intersection 91Q is 2.4 μm or less. Therefore, the embeddability of the isolated buried electrode 23 in the isolation trench 21 is not impaired. In other words, the occurrence of destruction at the L-shaped intersection 91Q can be suppressed without impairing the embeddability of the isolated buried electrode 23.

Therefore, the electrostatic breakdown resistance and dielectric breakdown resistance of the semiconductor device 1 can be improved. This makes it possible to avoid thickening of the gate insulating film 32, main surface insulating film 39, and interlayer insulating film 60 as a countermeasure against dielectric breakdown. As a result, the gate capacitance of the semiconductor device 1 can be reduced.

Furthermore, according to this embodiment, the first recess 96 is formed at the opening ends 21d, 21e of the isolation trench 21. Since the third width _W3 of the first recess 96 is 1350 Å or more, it is possible to mitigate the occurrence of electric field concentration at the opening ends 21d, 21e of the isolation trench 21. Therefore, it is possible to suppress the current concentration at the opening ends 21d, 21e of the isolation trench 21. As a result, it is possible to suppress the occurrence of breakdown in the isolation trench 21.

Furthermore, since the third width _W3 of the first recess 96 is 2000 Å or less, it does not adversely affect the function of the isolation trench 21. In other words, it is possible to suppress the occurrence of breakdown in the isolation trench 21 without adversely affecting the function of the isolation trench 21.

In addition, a second recess 97 is formed at the opening ends 31d, 31e of the gate trench 31. Since the fourth width _W4 of the second recess 97 is 1350 Å or more, it is possible to mitigate the occurrence of electric field concentration at the opening ends 31d, 31e of the gate trench 31. Therefore, it is possible to suppress the concentration of current at the opening ends 31d, 31e of the gate trench 31. This makes it possible to suppress the occurrence of breakdown at the opening ends 31d, 31e of the gate trench 31.

In addition, since the fourth width _W4 of the second recess 97 is 2000 Å or less, there is no adverse effect on the function of the gate trench 31. In other words, the occurrence of breakdown in the gate trench 31 can be suppressed without adversely affecting the function of the gate trench 31.

As a result, the electrostatic breakdown resistance and dielectric breakdown resistance of the semiconductor device 1 can be further improved.

The above describes an embodiment of the present disclosure, but the semiconductor device 1 of the present disclosure can be embodied in other forms.

For example, in the above-described embodiment, the semiconductor device 1 was an IGBT discrete device in which an IGBT was mounted alone as a functional element, but it may also be an RC-IGBT (Reverse-Conducting Insulated Gate Bipolar Transistor) in which an IGBT and a diode are mixed.

32, the IGBT structure Tr may include a cross-shaped intersection 91R where two trenches 202, 203 cross each other. The cross-shaped intersection 91R has four corners 92R. The curvature index CI _R of each corner 92R may be 1.5 μm or more and 2.4 μm or less.

In each of the above-mentioned embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. In other words, the p-type portion may be formed as n-type, and the n-type portion may be formed as p-type.

The following features can be extracted from the description in this specification and the drawings.

[Appendix 1-1]
A semiconductor chip (2) having a first main surface (3) and a second main surface (4) opposite thereto;
a trench-type IGBT structure (Tr) formed on the first main surface (3) of the semiconductor chip (2);
The IGBT structure (Tr) is
A trench (21, 31) extending in multiple directions is formed on the first main surface (3) of the semiconductor chip (2);
an insulating film (22, 32) formed on the side surface (21a, 21b, 31a, 31b) of the trench (21, 31);
a buried conductor (23, 33) buried inside the trench (21, 31) via the insulating film (22, 32);
The trenches (21, 31) extend in a plurality of directions, and the trenches (21, 31) intersect at the intersections (91P, 91Q, 91R),
The semiconductor device (1, 201) has a curvature index (CIP, CIQ) of a corner (92P, 92Q) of the intersection (91P, 91Q, 91R) of 1.5 μm or more.

According to this configuration, the curvature index (CI _P , CI _Q ) of the corners (92P, 92Q) of the intersections (91P, 91Q, 91R) of the trenches (21, 31) is 1.5 μm or more, so that the occurrence of electric field concentration at the corners (92P, 92Q) of the trenches (21, 31) can be mitigated. Therefore, the concentration of current at the corners (92P, 92Q) of the trenches (21, 31) can be suppressed. This makes it possible to suppress the occurrence of breakdown in the trenches (21, 31). Therefore, the dielectric breakdown resistance can be improved.

[Appendix 1-2]
The semiconductor device (1, 201) according to Appendix 1-1, wherein a chamfer width (W _F ) of a virtual figure formed by extension lines (E1, E2) of two sides forming the corners (92P, 92Q) of the intersections (91P, 91Q, 91R) is 0.4 μm or more.

[Appendix 1-3]
The semiconductor device (1, 201) according to appendix 1-1 or 1-2, wherein the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) is 2.4 μm or less.

[Appendix 1-4]
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-3, wherein a ratio (CI/W ₁ , CI/W ₂ ) of the curvature index (CI _P , CI _Q ) of the corner (92P, 92Q) of the intersection (91P, 91Q, 91R) to a width (W ₁ , W ₂ ) of the trench (21, 31) is 1.5 or more.

[Appendix 1-5]
The semiconductor device (1, 201) according to appendix 1-4, wherein the ratio (CI/W ₁ , CI/W ₂ ) of the curvature index (CI _P , CI _Q ) of the corner (92P, 92Q) of the intersection (91P, 91Q, 91R) to the width (W ₁ , W ₂ ) of the trench (21, 31) is 2.4 or less.

[Appendix 1-6]
The trenches (21, 31) extending in multiple directions include a first trench (21) and a plurality of second trenches (31) intersecting the first trench (21) at the intersections (91P, 91Q, 91R), the plurality of second trenches (31) being arranged in a stripe pattern spaced apart from one another;
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-5, wherein a ratio (CI P / _P , CI _Q /P) of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) to a pitch (P) of the multiple second trenches (31) is 0.1 or more.

[Appendix 1-7]
The semiconductor device (1, 201) according to appendix 1-6, wherein the ratio (CI P /P, CI Q /P) of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion ( _91P , 91Q, _91R ) to the pitch (P) of the plurality of second trenches (31) is 0.16 or less.

[Appendix 1-8]
The trenches (21, 31) extending in multiple directions include a first trench (21) and a plurality of second trenches (31) intersecting the first trench (21) at the intersections (91P, 91Q, 91R), the plurality of second trenches (31) being arranged in a stripe pattern spaced apart from one another;
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-7, wherein a ratio (CI _P /W ₅ , CI _Q /W ₅ ) of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) to a width (W ₅ ) of the mesa portion (90) defined between the plurality of second trenches (31) is 0.11 or more.

[Appendix 1-9]
The semiconductor device (1, 201) according to appendix 1-8, wherein the ratio (CI P /W 5 , CI Q /W ₅ ) of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion ( _91P , _91Q , 91R) to the width (W ₅ ) of the mesa portion ₍ 90) is 0.17 or less.

[Appendix 1-10]
The buried conductor (23, 33) includes a gate buried electrode (33) that controls a channel of the IGBT structure (Tr),
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-9, further comprising a drawn-out portion (40) that is integrally drawn out from the buried gate electrode (33) onto the first main surface (3) and covers the corner portions (92P, 92Q) of the intersection portions (91P, 91Q, 91R).

[Appendix 1-11]
The trenches (21, 31) extending in multiple directions are arranged in a stripe pattern spaced apart in a first direction, and include a plurality of gate trenches (31) each extending in a second direction, and a connection trench (21) extending in the first direction, connecting ends of the plurality of gate trenches (31) in the second direction to each other, and forming the T-shaped intersections (91P, 91Q, 91R) at connection portions with each of the gate trenches (31),
The buried conductor (23, 33) is integrally buried in the gate trench (31) and the connection trench (21);
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-3, further comprising an extension portion (40) that is extended from the embedded conductor (23, 33) onto the first main surface (3) and covers the corner portions (92P, 92Q) of the intersection portions (91P, 91Q, 91R).

[Appendix 1-12]
The gate trench (31) and the connection trench (21) have equal widths;
The semiconductor device (1, 201) according to appendix 1-11, wherein a ratio of the curvature index (CIP, CIQ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) to a width of the gate trench (31) and the connection trench (21) is 1.5 or more and 2.4 or less.

[Appendix 1-13]
The semiconductor device (1, 201) according to appendix 1-11 or appendix 1-12, wherein a ratio of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) to a pitch (P) of the multiple gate trenches (31) is 0.1 or more and 0.16 or less.

[Appendix 1-14]
The semiconductor device (1, 201) according to any one of Appendices 1-11 to 1-13, wherein a ratio of the curvature index (CI _P , CI _Q ) of the corner portion (92P, 92Q) of the intersection portion (91P, 91Q, 91R) to a width of the mesa portion (90) defined between the multiple gate trenches (31) is 0.11 or more and 0.17 or less.

[Appendix 1-15]
The semiconductor device (1, 201) according to any one of Supplementary Notes 1-11 to 1-14, comprising a gate finger electrode (83) extending in the second direction through a region above the connection trench (21) and connected to the lead-out portion (40).

[Appendix 1-16]
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-15, wherein the size of the semiconductor chip (2) is 0.5 mm square or more and 20 mm square or less.

[Appendix 1-17]
The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-16, wherein the gate capacitance value of the semiconductor chip (2) is 300 pF or less.

[Appendix 1-18]
The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-9, wherein the intersection portion (91P, 91Q, 91R) includes a T-shaped intersection portion (91P) where the trenches (21, 31) extending in the multiple directions intersect in a T shape.

[Appendix 1-19]
The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-10, wherein the intersection portion (91P, 91Q, 91R) includes an L-shaped intersection portion (91Q) where the trenches (21, 31) extending in the multiple directions intersect in an L shape.

[Appendix 1-20]
The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-10, wherein the intersection portion (91P, 91Q, 91R) includes a cross-shaped intersection portion (91R) where the trenches (21, 31) extending in the multiple directions intersect in a cross shape.

[Appendix 2-1]
A semiconductor chip (2) having a first main surface (3) and a second main surface (4) opposite thereto;
a trench-type IGBT structure (Tr) formed on the first main surface (3) of the semiconductor chip (2);
The IGBT structure (Tr) is
A trench (21, 31) formed in the first main surface (3) of the semiconductor chip (2);
an insulating film (22, 32) formed on the side surface (21a, 21b, 31a, 31b) of the trench (21, 31);
a buried conductor (23, 33) buried inside the trench (21, 31) via the insulating film (22, 32);
A recess (96, 97) recessed toward a side surface (21a, 21b, 31a, 31b) of the trench (21, 31) is formed at an opening end (21d, 21e, 31d, 31e) of the trench (21, 31),
A semiconductor device (1, 201), wherein the width (W ₃ , W ₄ ) of the recess (96, 97) is 1350 Å or more.

According to this configuration, recesses (96, 97) are formed at the opening ends (21d, 21e, 31d, 31e) of the trenches (21, 31). Since the widths ( _W3 , _W4 ) of the recesses (96, 97) are 1350 Å or more, the occurrence of electric field concentration at the opening ends (21d, 21e, 31d, 31e) of the trenches (21, 31) can be mitigated. Therefore, the concentration of current at the opening ends (21d, 21e, 31d, 31e) of the trenches (21, 31) can be suppressed. This makes it possible to suppress the occurrence of breakdown in the trenches (21, 31). Therefore, the dielectric breakdown resistance can be improved.

[Appendix 2-2]
The semiconductor device (1, 201) according to appendix 2-1, wherein the depth (D ₃ , D ₄ ) of the recess (96, 97) is 1850 Å or more.

[Appendix 2-3]
The semiconductor device (1, 201) according to appendix 2-1 or appendix 2-2, wherein the width (W ₃ , W ₄ ) of the recess (96, 97) is 2000 Å or less.

[Appendix 2-4]
The semiconductor device ( ₁ , 201) according to any one of Appendices 2-1 to _2-3 , wherein a ratio ( _W3 / _W1 , _W4 / _W2 ) of the width ( _W3 , _W4 ) of the recess (96, 97) to the width (W1, W2) of the trench (21, 31) is 0.14 or more.

[Appendix 2-5]
The semiconductor device ( ₁ , 201) according to appendix 2-4, wherein the ratio (W ₃ /W ₁ , W ₄ /W ₂ ) of the width (W ₃ , W ₄ ) of the recess (96, 97) to the width (W 1 , W ₂ ) of the trench (21, 31) is 0.2 or less.

[Appendix 2-6]
The trenches (31) are arranged in a stripe pattern at intervals from each other,
The semiconductor device (1, 201) according to any one of Appendices 2-1 to 2-5, wherein a ratio (W 4 /P) of the width (W ₄ ) of the recess (97) to the pitch ₍ P) of the plurality of trenches (31) is 0.009 or more.

[Appendix 2-7]
The semiconductor device (1, 201) according to appendix 2-6, wherein the ratio (W ₄ /P) of the width (W ₄ ) of the recess (97) to the pitch (P) of the plurality of trenches (31) is 0.0133 or less.

[Appendix 2-8]
The trenches (31) are arranged in a stripe pattern at intervals from each other,
The semiconductor device (1, 201) according to any one of Appendices 2-1 to 2-7, wherein a ratio (W ₄ /W _{5 ) of a width (W 4 )} of the recess (97) to a width (W ₅ ) of a mesa portion (90) defined between the plurality of trenches (31) is 0.011 or more.

[Appendix 2-9]
The semiconductor device (1, 201) according to appendix 2-8, wherein the ratio (W 4 /W _{5 ) of the width (W 4 )} of the recess ( ₉₇ ) to the width (W ₅ ) of the mesa portion (90) is 0.017 or less.

[Appendix 2-10]
The buried conductor (23, 33) includes a gate buried electrode (33) that controls a channel of the IGBT structure (Tr),
The semiconductor device (1, 201) according to any one of Supplementary Notes 2-1 to 2-9, further comprising a drawn-out portion (40) that is integrally drawn out from the buried gate electrode (33) onto the first main surface (3) and covers the recesses (96, 97).

[Appendix 2-11]
the trenches (21, 31) are formed by a plurality of gate trenches (31) arranged in a stripe pattern at intervals in a first direction and each extending in a second direction, and a connection trench (21) extending in the first direction, connecting ends of the plurality of gate trenches (31) in the second direction to each other, and forming T-shaped intersections (91P, 91Q, 91R) at connection portions with each of the gate trenches (31);
The recesses (96, 97) are formed at the intersections (91P, 91Q, 91R) of the trenches (21, 31),
The buried conductor (23, 33) is integrally buried in the gate trench (31) and the connection trench (21);
The semiconductor device (1, 201) according to any one of Appendices 2-1 to 2-3, further comprising an extension portion (40) that is extended from the embedded conductor (23, 33) onto the first main surface (3) and covers the recesses (96, 97) of the intersections (91P, 91Q, 91R).

[Appendix 2-12]
The gate trench (31) and the connection trench (21) have equal widths;
The semiconductor device (1, 201) according to appendix 2-11, wherein a ratio of the width of the recess (96, 97) to the width of the gate trench (31) and the connection trench (21) is 0.14 or more and 0.2 or less.

[Appendix 2-13]
The semiconductor device (1, 201) according to appendix 2-11 or appendix 2-12, wherein a ratio of the width of the recesses (96, 97) to a pitch (P) of the multiple gate trenches (31) is 0.009 or more and 0.0133 or less.

[Appendix 2-14]
The semiconductor device (1, 201) according to any one of Appendices 2-11 to 2-13, wherein a ratio of a width of the recess (96, 97) to a width (W ₅ ) of a mesa portion (90) defined between the multiple gate trenches (31) is 0.011 or more and 0.017 or less.

[Appendix 2-15]
The semiconductor device (1, 201) according to any one of Supplementary Notes 2-11 to 2-14, comprising a gate finger electrode (83) extending in the second direction through a region above the connection trench (21) and connected to the lead-out portion (40).

[Appendix 2-16]
The semiconductor device (1, 201) according to any one of Appendices 2-1 to 2-15, wherein the cross-sectional shape of the recess (96, 97) is an arc recessed toward the side surface (21a, 21b, 31a, 31b) of the trench (21, 31).

[Appendix 2-17]
The semiconductor device (1, 201) according to any one of Appendix 2-1 to Appendix 2-16, wherein the depth (D ₃ , D ₄ ) of the recess (96, 97) is greater than the width (W ₃ , W ₄ ) of the recess (96, 97).

[Appendix 2-18]
The semiconductor device (1, 201) according to appendix 2-17, wherein a ratio (W ₃ /D ₃ , W ₄ /D ₄ ) of the width (W ₃ , W ₄ ) of the recess (96, 97) to a depth (D ₃ , D ₄ ) of the recess (96, 97) is 0.6 or more and less than 0.9.

[Appendix 2-19]
The semiconductor device (1, 201) according to any one of Appendix 2-1 to Appendix 2-18, wherein the size of the semiconductor chip (2) is 0.5 mm square or more and 20 mm square or less.

[Appendix 2-20]
The semiconductor device (1, 201) according to any one of Appendices 2-1 to 2-19, wherein the gate capacitance value of the semiconductor chip (2) is 300 pF or less.

1: Semiconductor device 2: Semiconductor chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: IGBT region 6A: First IGBT region 6B: Second IGBT region 7: Boundary region 8: First boundary region 9: Second boundary region 10: Periphery region 11: Drift region 12: Buffer region 13: Collector region 20: Trench isolation structure 20A: First trench isolation structure 20B: Second trench isolation structure 20X: First direction portion 20Y: Second direction portion 21: Isolation trench 21a: Side surface 21b: Side surface 21c: Bottom surface 21d: Opening end 21e: Opening end 22: Isolation insulating film 23: Isolation buried electrode 25: Base region 30: Trench structure 30A : first end 30B : second end 31 : gate trench 31a : side surface 31b : side surface 31c : bottom surface 31d : opening end 31e : opening end 32 : gate insulating film 33 : gate buried electrode 35 : emitter region 36 : carrier storage region 37 : contact hole 38 : contact region 39 : main surface insulating film 40 : gate wiring 41 : pad wiring 42 : boundary wiring 43 : first peripheral wiring 44 : second peripheral wiring 50 : boundary well region 51 : first boundary well region 52 : second boundary well region 56 : peripheral well region 60 : interlayer insulating film 61 : contact opening 62 : gate opening 63 : first well opening 64 : second well opening 70 : via electrode 71 : gate electrode 72 : gate pad electrode 73 : first gate finger electrode 74 : second gate finger electrode 75 : emitter electrode 76 : emitter pad electrode 77 : emitter finger electrode 80 : collector electrode 81 : boundary gate opening 82 : gate via electrode 83 : boundary gate finger electrode 84 : notch 85 : slit 90 : mesa portion 91 : first L-shaped intersection 91P : T-shaped intersection 91PA : first T-shaped intersection 91PB : second T-shaped intersection 91Q : L-shaped intersection 91QB : second L-shaped intersection 91R : cross-shaped intersection 92P : corner 92Q : corner 92R : corner 93 : first side 94 : second side 96 : first recess 97 : second recess 98 : first straight portion 99 : second straight portion 100 : chamfered portion 101 : semiconductor wafer 103 : first wafer main surface 104 : Resist 105 : Second resist mask 105a : Opening 106 : Third resist mask 106a : Opening 107 : Base electrode layer 201 : Semiconductor device 202 : Trench 203 : Trench CI _P : Curvature index CI _Q : Curvature index D ₁ : First depth D ₂ : Second depth D ₃ : Third depth D ₄ : Fourth depth E 1 : Extension line E 2 : Extension line OP : Opening pattern P : Pitch P 1 : Intersection point PM : Patterning mask TL : Tangent line Tr : IGBT structure W ₁ : First width W ₂ : Second width W ₃ : Third width W ₄ : Fourth width W ₅ : Fifth width X : First direction Y : Second direction Z : Normal direction

Claims (20)

a semiconductor chip having a first major surface and an opposite second major surface;
a trench-type IGBT structure formed on the first main surface of the semiconductor chip,
The IGBT structure is
a trench formed in the first main surface of the semiconductor chip;
an insulating film formed on a side surface of the trench;
a buried conductor buried inside the trench via the insulating film,
A recess is formed at an opening end of the trench, the recess being recessed toward a side surface of the trench,
The semiconductor device, wherein the recess has a width of 1350 Å or more. The semiconductor device according to claim 1, wherein the depth of the recess is 1850 Å or more. The semiconductor device according to claim 1 or 2, wherein the width of the recess is 2000 Å or less. The semiconductor device according to any one of claims 1 to 3, wherein the ratio of the width of the recess to the width of the trench is 0.14 or more. The semiconductor device of claim 4, wherein the ratio of the width of the recess to the width of the trench is 0.2 or less. The trenches are arranged in a stripe pattern at intervals from one another,
6. The semiconductor device according to claim 1, wherein a ratio of a width of said recess to a pitch of said plurality of trenches is 0.009 or more. The semiconductor device of claim 6, wherein the ratio of the width of the recess to the pitch of the trenches is 0.0133 or less. The trenches are arranged in a stripe pattern at intervals from one another,
8. The semiconductor device according to claim 1, wherein a ratio of a width of said recess to a width of a mesa portion defined between said plurality of trenches is 0.011 or more. The semiconductor device according to claim 8, wherein the ratio of the width of the recess to the width of the mesa is 0.017 or less. the buried conductor includes a buried gate electrode that controls a channel of the IGBT structure;
10. The semiconductor device according to claim 1, further comprising a lead portion that is integrally led out from said buried gate electrode onto said first main surface and covers said recess. the trench is formed by a plurality of gate trenches arranged in a stripe pattern at intervals in a first direction and each extending in a second direction, and a connection trench extending in the first direction, connecting ends of the plurality of gate trenches in the second direction to each other, and forming a T-shaped intersection at a connection portion with each of the gate trenches;
the recess is formed at the intersection of the trenches,
the buried conductor is integrally buried in the gate trench and the connection trench;
4. The semiconductor device according to claim 1, further comprising an extension portion extending from said buried conductor onto said first main surface and covering said recessed portion of said intersection portion. the gate trench and the connection trench have equal widths;
The semiconductor device according to claim 11 , wherein a ratio of a width of the recess to a width of the gate trench and a width of the connection trench is not less than 0.14 and not more than 0.2. The semiconductor device according to claim 11 or 12, wherein the ratio of the width of the recess to the pitch of the gate trenches is 0.009 or more and 0.0133 or less. The semiconductor device according to any one of claims 11 to 13, wherein the ratio of the width of the recess to the width of the mesa portion defined between the multiple gate trenches is 0.011 or more and 0.017 or less. The semiconductor device according to any one of claims 11 to 14, comprising a gate finger electrode extending in the second direction through the region above the connection trench and connected to the lead-out portion. The semiconductor device according to any one of claims 1 to 15, wherein the cross-sectional shape of the recess is an arc recessed toward the side surface of the trench. The semiconductor device according to any one of claims 1 to 16, wherein the depth of the recess is greater than the width of the recess. The semiconductor device of claim 17, wherein the ratio of the width of the recess to the depth of the recess is greater than or equal to 0.6 and less than 0.9. The semiconductor device according to any one of claims 1 to 18, wherein the size of the semiconductor chip is 0.5 mm square or more and 20 mm square or less. The semiconductor device according to any one of claims 1 to 19, wherein the gate capacitance value of the semiconductor chip is 300 pF or less.

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