WO2020206719A1 - Display panel and method for manufacturing same - Google Patents

Abstract

A display panel (20) and a method for manufacturing same. The display panel (20) comprises a display area (200), and the display area (200) is provided with a light emitting area (201); the light emitting area (201) comprises a substrate (21), a buffer layer (23), an interlayer insulating layer (24), a passivation layer (25), a planarization layer (210), and a metal trace (211), the buffer layer (23) is provided with a first slotted hole (231), and the first slotted hole (231) passes through the buffer layer (23) and corresponds to the light emitting area (201); the degree of planarization of the planarization layer (210) can be improved, and the thickness of the planarization layer (210) can be reduced.

Description

Display panel and preparation method thereof Technical field

The present invention relates to the technical field of liquid crystal display, in particular to a display panel and a preparation method thereof.

Background technique

The current display types mainly include liquid crystal display (Liquid Crystal Display, LCD), organic light-emitting diode display (Organic Light-Emitting Diode, OLED), Plasma Display Panel (PDP) and electronic ink display, etc. Among them, OLED displays are recognized by the industry as the third-generation display technology after LCD displays for their light and thin, active light-emitting, fast response speed, wide viewing angle, rich color, high brightness, low power consumption, high and low temperature resistance, etc. , Can be widely used in terminal products such as smart phones, tablet computers, and TVs.

To prepare OLED devices by inkjet printing process, the flatter the surface of the light-emitting area, the better, so that the OLED layer can have a uniform film thickness, but usually there are various traces and vias when the substrate is made, which will cause The ups and downs of the layer structure. As shown in Figure 1, the usual TFT substrate will make a planarization layer. For inkjet printing technology that requires a high level of flatness, the planarization layer needs to be thick and uneven. On the one hand, material is wasted and the other is On the one hand, the exposure process is more difficult to control if the material is too thick, resulting in uneven thicknesses between layers in the entire light-emitting area, increasing the impurity content of the material, and affecting the performance of the array substrate.

technical problem

The purpose of the present invention is to provide a display panel and a manufacturing method thereof, which can effectively solve the problems of poor flatness of the light-emitting area and thicker thickness of the flat layer.

Technical solutions

In order to solve the above technical problems, the present invention provides a display panel, which is characterized by comprising a display area, the display area has a light-emitting area; the light-emitting area includes: a substrate; a buffer layer with a first slot, the The first slot penetrates the buffer layer and corresponds to the light-emitting area; an interlayer insulating layer is filled in the first slot and covers the buffer layer, the interlayer insulating layer has a first groove, so The first groove is located on a side of the interlayer insulating layer away from the buffer layer and corresponds to the first slot; a passivation layer is filled in the first groove and covers the interlayer dielectric On the layer, the passivation layer has a second groove, and the second groove is located on a side of the passivation layer away from the interlayer dielectric layer and corresponds to the first groove; the planarization layer, Filling and covering the inter-dielectric layer; metal traces are provided on the planarization layer and correspond to the light-emitting area.

Further, the depth of the second groove is less than or equal to the depth of the first slot; the depth of the first slot is 100-500 nm.

Further, the thickness of the interlayer insulating layer is 200 to 1000 nm; the thickness of the passivation layer is 100 to 500 nm; and the thickness of the planarization layer is 0.5 to 2 nm.

Further, the interlayer insulating layer is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and a silicon nitride composite layer; the passivation layer is a silicon oxide layer, a silicon nitride layer, silicon oxide and One of the silicon nitride composite layers; the material used for the planarization layer is a photoresist material.

The metal wiring is an anode wiring, and in the light-emitting area, the display panel further includes a pixel definition layer covering the planarization layer, which has a slot penetrating the pixel definition layer and corresponding to the pixel definition layer. The anode wiring, the anode wiring is exposed in the slot; the light-emitting layer is arranged on the anode in the slot.

Further, in the display area, the display panel further includes a semiconductor layer covering a side of the buffer layer away from the substrate; the semiconductor layer has a source region and a drain region; a gate insulating layer , Covering the buffer layer and the semiconductor layer; a gate metal layer, covering the gate insulating layer; source and drain wiring, covering the interlayer insulating layer, the source and drain The traces are correspondingly connected to the source region and the drain region; the interlayer insulating layer covers the gate metal layer; the anode traces are correspondingly connected to the source and drain traces.

Further, the material used for the semiconductor layer is indium gallium zinc oxide, indium zinc tellurium oxide or indium gallium zinc tellurium oxide; the gate insulating layer material is silicon oxide or silicon nitride; the gate The metal layer material is molybdenum, aluminum, copper or tellurium.

Another object of the present invention is to provide a method for manufacturing a display panel, which is characterized by including the steps of: providing a substrate; forming a buffer layer on the substrate; etching a first slot on the buffer layer, and The first slot penetrates the buffer layer and corresponds to the light-emitting region; the material used for the interlayer insulating layer is simultaneously deposited on the buffer layer and in the first slot to form the interlayer insulating layer, and A first groove is formed at the position of the interlayer insulating layer corresponding to the first slot, wherein the first groove is located on the side of the interlayer insulating layer away from the buffer layer; the passivation layer is used Material is simultaneously deposited in the interlayer insulating layer and the first groove to form the passivation layer, and a second groove is formed at the position of the passivation layer corresponding to the first groove, wherein the The second groove is located on the side of the passivation layer away from the interlayer insulating layer; the material used for the planarization layer is deposited in the passivation layer and the second groove to form the planarization layer ; Forming metal traces on the planarization layer, the metal traces corresponding to the light-emitting area.

Further, the metal wiring is an anode wiring. After the metal wiring is formed on the planarization layer, the method further includes forming a pixel definition layer on the planarization layer in the light-emitting area; A slot penetrating the pixel defining layer is etched to expose the metal trace in the slot; a light-emitting layer is formed on the anode in the slot.

Further, before the step of forming the interlayer insulating layer, the method further includes: forming a semiconductor layer on the buffer layer; forming a gate insulating layer on the semiconductor layer; forming a gate metal layer on the On the gate insulating layer, and a patterned gate formed by etching the gate metal layer; then, according to the patterned gate, the gate insulating layer is etched; plasma treatment of the semiconductor layer, the The entire surface of the gate insulating layer and the gate metal layer.

Beneficial effect

The present invention provides a display panel and a preparation method thereof. A slot is etched in a buffer layer by yellow light, and the position of the through hole is opposite to the position of the light-emitting area; and then the device layer of the OLED is prepared in the buffer layer and the groove position, In this way, the flatness of the planarization layer and the anode layer of the obtained display panel can be improved, and the thickness of the planarization layer can be reduced, thereby reducing material waste.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a schematic diagram of the structure of a display panel in the prior art;

2 is a schematic diagram of the structure of the display panel provided by the present invention;

3 is a schematic diagram of the structure of the substrate, the light shielding layer and the buffer layer provided by the present invention;

4 is a schematic diagram of the structure of a first slot, a semiconductor layer, a gate metal layer, and a gate insulating layer provided by the present invention;

5 is a schematic diagram of the structure of the first groove provided by the present invention;

6 is a schematic diagram of the structure of the source and drain traces etched through holes provided by the present invention;

Fig. 7 is a schematic structural diagram of a second groove provided by the present invention;

Fig. 8 is a structural schematic diagram of the slot provided by the present invention.

Embodiment of the invention

The following is the description of each embodiment with reference to the attached drawings to illustrate specific embodiments in which the present invention can be implemented. The terms of direction mentioned in the present invention, such as up, down, front, back, left, right, inside, outside, side, etc., are only directions with reference to the drawings. The component names mentioned in the present invention, such as first, second, etc., only distinguish different components and can be better expressed. In the figures, units with similar structures are indicated by the same reference numerals.

The embodiments of the present invention will be described in detail herein with reference to the accompanying drawings. The present invention can be manifested in many different forms, and the present invention should not only be interpreted as the specific embodiments set forth herein. The embodiments of the present invention are provided to explain the practical application of the present invention, so that other skilled in the art can understand various embodiments of the present invention and various modifications suitable for specific anticipated applications.

As shown in FIG. 2, the present invention provides a display panel 20, which is characterized in that it includes a display area 200, the display area 200 has a light-emitting area 201; the light-emitting area 201 includes: a substrate 21, a buffer layer 23, a layer The inter-insulating layer 24, the passivation layer 25, the planarization layer 210, and the metal wiring 211.

Wherein, the buffer layer 23 has a first slot 231 (refer to FIG. 4), the first slot 231 penetrates the buffer layer 23 and corresponds to the light-emitting region 201; the interlayer insulating layer 24 is filled in the The first slot 231 covers the buffer layer 23, the interlayer insulating layer 24 has a thickness of 200-1000 nm, and the interlayer insulating layer 24 has a first groove 241 (refer to FIG. 5). The first groove 241 is located on the side of the interlayer insulating layer 24 away from the buffer layer 23 and corresponds to the first slot 231; the passivation layer 25 is filled in the first groove 241 and Covering the interlayer dielectric layer, the passivation layer 25 has a thickness of 100 to 500 nm, and the passivation layer 25 has a second groove 251 (refer to FIG. 7), and the second groove 251 is located The passivation layer 25 is away from the side of the interlayer dielectric layer and corresponds to the first groove 241; the depth of the second groove 251 is less than or equal to the depth of the first slot 231, which is In an embodiment, the thickness of the buffer layer 23 is 100~500nm, the depth of the first slot 231 is 100~500nm, for example, the thickness of the buffer layer 23 is 300nm, the depth of the first slot 231 If it is 300 nm, the depth of the second groove 251 may be 300 nm or less than 300 nm. When it is less than 300 nm, it may be 200 nm or 250 nm, but it should not be too small. The planarization layer 210 is filled and covered on the inter-dielectric layer, and the planarization layer 210 has a thickness of 0.5-2 nm; the metal trace 211 is provided on the planarization layer 210 and corresponds to the light-emitting area 201. In this implementation, the metal wiring 211 is an anode wiring.

Wherein, the interlayer insulating layer 24 is one of silicon oxide layer, silicon nitride layer, silicon oxide and silicon nitride composite layer; the passivation layer 25 is silicon oxide layer, silicon nitride layer, silicon oxide layer And a silicon nitride composite layer; the material used for the planarization layer 210 is a photoresist material.

The display panel 20 further includes a pixel definition layer 212 overlying the planarization layer 210, which has a slot 216 that penetrates the pixel definition layer 212 and corresponds to the anode wiring 211, and the anode wiring 211 It is exposed in the groove 216; the light-emitting layer 214 is disposed on the anode in the groove 216.

In the display area 200, the display panel 20 further includes a light shielding layer 22, a semiconductor layer 26, a gate insulating layer 27, a gate metal layer 28, and source/drain wiring 29.

Wherein, the light-shielding layer 22 covers one side of the substrate 21 and is covered by the buffer layer 23, and the semiconductor layer 26 covers the buffer layer 23 on the side away from the substrate 21; The layer 26 has a source region 262 and a drain region 263; the gate insulating layer 27 covers the buffer layer 23 and the semiconductor layer 26; the gate metal layer 28 covers the gate insulating layer 27; the source and drain traces 29 cover the interlayer insulating layer 24, the source and drain traces 29 are correspondingly connected to the source region 262 and the drain region 263; the interlayer The insulating layer 24 covers the gate metal layer 28; the anode wiring 211 is connected to the source and drain wiring 29 correspondingly.

The thickness of the semiconductor layer 26 is 10-100 nm, and the material used for the semiconductor layer 26 is indium gallium zinc oxide, indium zinc tellurium oxide or indium gallium zinc tellurium oxide; the material of the gate insulating layer 27 is Silicon oxide or silicon nitride, the gate insulating layer 27 has a thickness of 100-300 nm; the gate metal layer 28 is made of molybdenum, aluminum, copper, tellurium or an alloy, and the gate metal layer 28 has a thickness of 200 -800nm.

In the display panel 20 of the present invention, a first slot 231 is formed at the position of the buffer layer 23 corresponding to the light-emitting area 201, and the position is opposite to the light-emitting area 201; this can improve the flatness of the OLED planarization layer 210 and the anode layer. In addition, the thickness of the planarization layer 210 is reduced, thereby reducing material waste.

Another object of the present invention is to provide a method for manufacturing a display panel, including the following steps:

As shown in FIG. 1, a substrate 21 is provided, and the substrate 21 is cleaned. The substrate 21 is generally a glass substrate. A layer of metal with a thickness of 50-200 nm is deposited on the substrate 21 to form the light-shielding layer 22. The metal may be Mo, Al, Cu, Ti, etc., or an alloy.

A buffer layer 23 is formed on the substrate 21. The buffer layer 23 is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and a silicon nitride composite layer, and the buffer layer 23 has a thickness of 100 to 500 nm

A first slot 231 is etched on the buffer layer 23. The first slot 231 penetrates the buffer layer 23 and corresponds to the light-emitting region 201; the depth of the first slot 231 is 100-500 nm.

A semiconductor layer 26 is formed on the buffer layer 23; the semiconductor is a metal oxide material, the thickness of the semiconductor layer 26 is 10-100 nm, and the material used for the semiconductor layer 26 is indium gallium zinc oxide, indium Zinc tellurium oxide or indium gallium zinc tellurium oxide

Forming a gate insulating layer 27 on the semiconductor layer 26; the material of the gate insulating layer 27 is silicon oxide or silicon nitride, and the thickness of the gate insulating layer 27 is 100-300 nm;

Forming a gate metal layer 28 on the gate insulating layer 27, and etching the gate metal layer 28 to form a patterned gate;

According to the patterned gate, the gate insulating layer 27 is etched; in this way, the gate insulating layer 27 exists only under the film layer with the gate metal pattern, and the remaining gate insulating layer 27 is etched away.

Plasma treatment of the entire surface of the semiconductor layer 26, the gate insulating layer 27 and the gate metal layer 28. In this way, for the semiconductor layer 26 without the gate insulating layer 27 and the gate metal protection, the resistance is significantly reduced after the treatment, and an N+ conductor layer is formed. Since the semiconductor layer 26 under the gate insulating layer 27 has not been processed, it maintains semiconductor characteristics and serves as a TFT channel.

5, the materials used for the interlayer insulating layer 24 are simultaneously deposited on the buffer layer 23 and in the first slot 231 to form the interlayer insulating layer 24, and insulate the interlayer The layer 24 forms a first groove 241 corresponding to the position of the first slot 231, wherein the first groove 241 is located on the side of the interlayer insulating layer 24 away from the buffer layer 23; the interlayer insulating layer The thickness of 24 is 200-1000 nm, and the interlayer insulating layer 24 is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and a silicon nitride composite layer. As shown in FIG. 6, the via holes (not marked in the figure) required for the wiring of the source and drain 29, the drain 292, and the source 291 are etched on the interlayer insulating layer.

As shown in FIG. 7, the materials used for the passivation layer 25 are simultaneously deposited in the interlayer insulating layer 24 and the first groove 241 to form the passivation layer 25, and in the passivation layer 25 A second groove 251 is formed corresponding to the position of the first groove 241, wherein the second groove 251 is located on the side of the passivation layer 25 away from the interlayer insulating layer 24; the thickness of the passivation layer 25 The thickness is 100-500 nm, and the passivation layer 25 is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and a silicon nitride composite layer.

Referring to FIG. 8, the material used for the planarization layer 210 is deposited in the passivation layer 25 and the second groove 251 to form the planarization layer 210; the thickness of the planarization layer 210 is 0.5- 2um, the planarization layer 210 is a layer of photoresist material. A contact hole 213 that penetrates the planarization layer 210 to the drain level 292 is etched in the planarization layer 210.

A metal trace 211 is formed on the planarization layer 210 and the slot 216, and the metal trace 211 corresponds to the light-emitting area 201. The metal wiring 211 is an anode wiring, so that the anode wiring 211 can be connected to the drain 292.

In the light-emitting area 201, a pixel definition layer 212 is formed on the planarization layer 210 and the anode wiring 211, and a slot 216 penetrating through the pixel definition layer 212 is etched to expose the metal wiring 211 In the slot 216;

A light-emitting layer 214 is formed on the anode wiring 211 in the groove 216. The light-emitting layer 214 includes a hole injection layer covering the anode wiring 211 on the side away from the planarization layer 210, and a hole transport layer covering the hole injection layer on the side away from the anode. The hole transport layer is away from the bright layer on the layer-by-layer side of the hole, overlies the bright layer on the electron transport layer away from the hole transport layer, and overlies the electron transport layer on the side away from the bright layer The electron injection layer is not marked in the drawing.

In the cathode layer preparation step, a cathode layer 215 is prepared on the surface of the anode layer and the pixel defining layer 212.

The present invention provides a display panel and a manufacturing method thereof. A slot hole is etched at the position of the buffer layer 23 corresponding to the light-emitting area 201, and the position is opposite to the position of the light-emitting area 201; in this way, the planarization layer 210 of the OLED can be routed to the anode 211 The flatness is improved, and the thickness of the planarization layer 210 is reduced, thereby reducing material waste.

The technical scope of the present invention is not limited to the content in the description. Those skilled in the art can make various deformations and modifications to the embodiments without departing from the technical idea of the present invention, and these deformations and modifications are all It should fall within the scope of the present invention.

Claims (10)

A display panel, including A display area, the display area has a light-emitting area; the light-emitting area includes: Substrate A buffer layer having a first slot, the first slot penetrates the buffer layer and corresponds to the light-emitting area; An interlayer insulation layer is filled in the first slot and covers the buffer layer, the interlayer insulation layer has a first groove, and the first groove is located in the interlayer insulation layer away from the buffer layer. One side of the buffer layer corresponds to the first slot; A passivation layer filled in the first groove and covering the interlayer dielectric layer, the passivation layer has a second groove, and the second groove is located in the passivation layer away from the layer One side of the inter-dielectric layer and corresponds to the first groove; A planarization layer filled and covered on the inter-dielectric layer; Metal traces are provided on the planarization layer and correspond to the light-emitting area. The display panel according to claim 1, wherein: The depth of the second groove is less than or equal to the depth of the first slot; the depth of the first slot is 100-500 nm. The display panel according to claim 1, wherein: The thickness of the interlayer insulating layer is 200-1000 nm; The thickness of the passivation layer is 100 to 500 nm; The thickness of the planarization layer is 0.5-2 nm. The display panel according to claim 1, wherein: The interlayer insulating layer is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and silicon nitride composite layer; The passivation layer is one of a silicon oxide layer, a silicon nitride layer, a silicon oxide and silicon nitride composite layer; The material used for the planarization layer is a photoresist material. The display panel according to claim 1, wherein the metal wiring is an anode wiring, and in the light-emitting area, the display panel further comprises A pixel definition layer covering the planarization layer, which has a slot penetrating the pixel definition layer and corresponding to the anode wiring, and the anode wiring is exposed in the groove; The light-emitting layer is arranged on the anode in the slot. The display panel according to claim 5, wherein, in the display area, the display panel further comprises A semiconductor layer covering a side of the buffer layer away from the substrate; the semiconductor layer has a source region and a drain region; A gate insulating layer covering the buffer layer and the semiconductor layer; A gate metal layer covering the gate insulating layer; Source and drain traces cover the interlayer insulating layer, and the source and drain traces are connected to the source region and the drain region correspondingly; the interlayer insulation layer covers the gate metal Layer up The anode wiring is correspondingly connected to the source and drain wiring. The display panel according to claim 6, wherein: The material used for the semiconductor layer is indium gallium zinc oxide, indium zinc tellurium oxide or indium gallium zinc tellurium oxide; The gate insulating layer material is silicon oxide or silicon nitride; The gate metal layer material is molybdenum, aluminum, copper or tellurium. A method for manufacturing a display panel, which includes the following steps: Provide a substrate; Forming a buffer layer on the substrate; Etching a first slot hole on the buffer layer, the first slot hole penetrates the buffer layer and corresponds to the light-emitting area; The materials used for the interlayer insulating layer are simultaneously deposited on the buffer layer and in the first slot to form the interlayer insulating layer, and the interlayer insulating layer is formed at a position corresponding to the first slot A first groove, wherein the first groove is located on a side of the interlayer insulating layer away from the buffer layer; The materials for the passivation layer are simultaneously deposited in the interlayer insulating layer and the first groove to form the passivation layer, and a second passivation layer is formed at a position corresponding to the first groove. A groove, wherein the second groove is located on a side of the passivation layer away from the interlayer insulating layer; Depositing all materials for the planarization layer in the passivation layer and the second groove to form the planarization layer; A metal trace is formed on the planarization layer, and the metal trace corresponds to the light-emitting area. The method for manufacturing a display panel according to claim 5, wherein the metal wiring is an anode wiring, and after the metal wiring is formed on the planarization layer, the method further comprises In the light-emitting area, forming a pixel definition layer on the planarization layer; Etching a slot penetrating the pixel definition layer, so that the metal trace is exposed in the slot; A light-emitting layer is formed on the anode in the groove. The manufacturing method of the display panel according to claim 6, wherein: Before the step of forming the interlayer insulating layer, the method further includes: Forming a semiconductor layer on the buffer layer; Forming a gate insulating layer on the semiconductor layer; Forming a gate metal layer on the gate insulating layer, and etching the gate metal layer to form a patterned gate; then, according to the patterned gate, etching the gate insulating layer; Plasma treatment of the entire surface of the semiconductor layer, the gate insulating layer and the gate metal layer.