WO2015027620A1 - 阵列基板及其制作方法、显示装置及电子产品 - Google Patents

阵列基板及其制作方法、显示装置及电子产品 Download PDF

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Publication number
WO2015027620A1
WO2015027620A1 PCT/CN2013/089431 CN2013089431W WO2015027620A1 WO 2015027620 A1 WO2015027620 A1 WO 2015027620A1 CN 2013089431 W CN2013089431 W CN 2013089431W WO 2015027620 A1 WO2015027620 A1 WO 2015027620A1
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Prior art keywords
conductive layer
auxiliary conductive
array substrate
data line
auxiliary
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English (en)
French (fr)
Inventor
周纪登
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US14/381,626 priority Critical patent/US9588389B2/en
Publication of WO2015027620A1 publication Critical patent/WO2015027620A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • ADS TFT-LCD Advanced Super Dimension Switch Thin Film Transistor Liquid Crystal Display
  • the electric field generated between the electrodes forms a multi-dimensional electric field, so that liquid crystal molecules between the slit electrodes in the display panel and directly above the slit electrode can be deflected, thereby improving the working efficiency of the liquid crystal molecules and increasing the light transmission efficiency.
  • the display effect is mainly determined by the display panel.
  • the display panel includes an array substrate, a color filter substrate, and a liquid crystal molecular layer between the two substrates.
  • the display panel of the ADS TFT-L €D often exhibits undesirable phenomena such as greening of the screen.
  • the main reason for the flooding of the screen is that the voltage of the common electrode disposed on the array substrate is distorted, that is, the waveform of the voltage of the common electrode is deviated, or the voltage of the common electrode is attenuated, that is, the value of the voltage is decreased as the transmission distance is increased. Small, it is possible to prevent the occurrence of undesirable phenomena such as greening of the screen by preventing distortion of the voltage of the common electrode.
  • the technical problem to be solved by the present invention is to provide an array substrate, a manufacturing method thereof, a display device, and an electronic product, thereby improving the green phenomenon of the display panel of the ADS TFTXCD and achieving a relatively simple operation.
  • the first aspect of the present invention provides an array substrate, which adopts the following technical solutions:
  • An array substrate comprising a substrate substrate, a criss-crossing grid line on the substrate substrate And a data line, and a common electrode, the common electrode comprising a transparent conductive layer and a first auxiliary conductive layer under the transparent conductive layer, a first auxiliary conductive layer of the common electrode and the gate line or the
  • the data lines at least partially overlap.
  • the array substrate further includes a thin film transistor and a pixel electrode, the common electrode further comprising a second auxiliary conductive layer between the periphery of the thin film transistor and a periphery of the pixel electrode, the second auxiliary conductive layer Formed integrally with the first auxiliary conductive layer, the transparent conductive layer being located above the second auxiliary conductive layer.
  • the material of the first auxiliary conductive layer and the second auxiliary conductive layer is metal.
  • the metal is copper, aluminum, silver, molybdenum, chromium or a combination thereof.
  • the first auxiliary conductive layer completely covers the gate line or the data line.
  • the first auxiliary conductive layer is located directly above the gate line or the data line, and an orthographic projection of the first auxiliary conductive layer on the base substrate is smaller than the gate line or the data line is An orthographic projection on the substrate substrate.
  • the first auxiliary conductive layer covers the gate line or a portion of the data line.
  • the first auxiliary conductive layer and the second auxiliary conductive layer have a thickness of 90O4500 A, and the transparent conductive layer has a thickness of 400 to 700 ⁇ .
  • the array substrate described above comprises a substrate substrate, a criss-crossing gate line on the substrate substrate, a data line and a common electrode
  • the common electrode comprises a transparent conductive layer and a first auxiliary conductive layer under the transparent conductive layer, common
  • the first auxiliary conductive layer of the electrode overlaps the gate line or the data line.
  • the common electrode disposed on the array substrate having the structure as described above includes a first auxiliary conductive layer and a transparent conductive layer, wherein the first auxiliary conductive layer and the transparent conductive layer are connected in parallel to form a common electrode, and thus the resistance of the common electrode is small and reduced.
  • the distortion of the common electrode voltage is attenuated, so that the waveform of the voltage of the common electrode is not easily deviated, and the value of the voltage of the common electrode does not decrease significantly with the increase of the transmission distance, thereby improving the green phenomenon of the picture and improving the ADS TFT- LCD display effect.
  • a second aspect of the invention provides a display device comprising the array substrate as described above.
  • a third aspect of the present invention provides a method for fabricating an array substrate, including:
  • Forming a pattern including a gate line, a pattern including a data line, and the gate line and the data line are criss-crossed on the substrate substrate; Forming a pattern including a first auxiliary conductive layer on the pattern of the formed data lines, the first auxiliary conductive layer at least partially overlapping the gate line or the data line;
  • a pattern including the transparent conductive layer is formed.
  • a pattern including the transparent conductive layer is formed.
  • the material of the first auxiliary conductive layer and the second auxiliary conductive layer is metal.
  • the metal is copper, aluminum, silver, molybdenum, chromium or a combination thereof.
  • the first auxiliary conductive layer and the second auxiliary conductive layer have a thickness of 90O4500A, and the transparent conductive layer has a thickness of 400 to 700A.
  • Forming a pattern including a first auxiliary conductive layer on the formed pattern of the data line, the first auxiliary conductive layer at least partially overlapping the gate line or the data line includes:
  • the first auxiliary conductive layer completely covers the gate line or the data line;
  • the first auxiliary conductive layer is located directly above the gate line or the data line, and an orthographic projection of the first auxiliary conductive layer on the base substrate is smaller than the gate line or the data line is An orthographic projection on the substrate; or
  • the first auxiliary conductive layer covers the gate line or a portion of the data line.
  • the array substrate comprises a substrate substrate, a criss-crossing gate line on the substrate substrate, a data line and a common electrode
  • the common electrode comprises a transparent conductive layer and is located under the transparent conductive layer.
  • the first auxiliary conductive layer, the first auxiliary conductive layer of the common electrode overlaps the gate line or the data line.
  • the common electrode disposed on the array substrate having the structure as described above includes a first auxiliary conductive layer and a transparent conductive layer, wherein the first auxiliary conductive layer and the transparent conductive layer are connected in parallel to form a common electrode, and thus the resistance of the common electrode is small and reduced.
  • the distortion of the common electrode voltage is attenuated, making the public
  • the waveform of the voltage of the electrode is not easily deviated, and the value of the voltage of the common electrode is not significantly reduced as the transmission distance is increased, the green phenomenon of the picture is improved, and the display effect of the ADS TFT-LCD is improved.
  • FIG. 1 is a schematic plan view of a first array substrate provided by an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the array substrate shown in FIG. 1 according to the embodiment of the present invention
  • FIG. 3 is a cross-sectional view of the array substrate shown in FIG. 1 according to the embodiment of the present invention
  • FIG. 5 is a cross-sectional view of a second exemplary array substrate of the present invention.
  • FIG. 5 is a schematic diagram of a second embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of a thin film transistor of a first array substrate provided by the embodiment of the present invention;
  • FIG. 8 is an array substrate of the present embodiment.
  • the embodiment of the present invention provides an array substrate, as shown in FIG. 1 to FIG. 3, the array substrate includes a substrate substrate 1, a crisscross gate line 2 and a data line 5 on the substrate substrate 1, and a common Electrode 8.
  • the common electrode 8 includes a transparent conductive layer 82 and a first auxiliary conductive layer 81 under the transparent conductive layer 82, and the first auxiliary conductive layer 81 of the common electrode at least partially overlaps the gate line 2 or the data line 5.
  • the common electrode disposed on the array substrate having the structure as described above includes a first auxiliary conductive layer and a transparent conductive layer, wherein the first auxiliary conductive layer and the transparent conductive layer are connected in parallel to form a common electrode, and thus the resistance of the common electrode is small and reduced.
  • the distortion of the common electrode voltage is attenuated, so that the waveform of the voltage of the common electrode is not easily deviated, and the value of the voltage of the common electrode does not decrease significantly with the increase of the transmission distance, thereby improving the green phenomenon of the picture and improving the ADS TFTTLCD. display effect.
  • the common electrode 8 may further include a second auxiliary conductive layer 83 between the periphery of the thin film transistor and the periphery of the pixel electrode 6, the second auxiliary conductive layer 83 and the first
  • An auxiliary conductive layer 81 is formed in a body, and a transparent conductive layer 82 is disposed on the second auxiliary conductive layer 83.
  • the first auxiliary conductive layer 81 is preferably a metal material having good conductivity, such as copper or aluminum. Silver, molybdenum, chromium, etc.; the transparent conductive layer 82 is preferably a transparent conductive material such as radium oxide oxide or radium oxide oxide; the second auxiliary conductive layer 83 is integrally formed with the first auxiliary conductive layer 81, and is preferably, for example, copper or aluminum.
  • a conductive metal material such as silver, molybdenum or chromium.
  • the common electrode 8 is a transparent conductive material such as radium oxide oxide or radium oxide oxide, and has good light transmittance.
  • the common electrode 8 includes a first auxiliary conductive layer 81, a transparent conductive layer 82 or a second auxiliary conductive layer 83, and the first auxiliary conductive layer 81 and the second auxiliary conductive layer 83 are opaque. metallic material.
  • the width and position of the orthographic projection of the second auxiliary conductive layer 83 on the array substrate should satisfy When the array substrate and the color filter substrate are paired, the black matrix on the color filter substrate may cover the second auxiliary conductive layer 83.
  • the width and position of the orthographic projection of the first auxiliary conductive layer 81 on the array substrate are also The first auxiliary conductive layer 81 is completely covered by the first auxiliary conductive layer 81. As shown in FIG. 1 to FIG. 3, the first auxiliary conductive layer 81 is located. Above the data line 5, the width of the first auxiliary conductive layer 81 is larger than the width of the data line 5, so that the resistance of the common electrode 8 can be reduced to the utmost extent, but the width of the first auxiliary conductive layer 81 needs to be smaller than the corresponding position on the color filter substrate.
  • the width of the black matrix can not affect the transmittance of the display panel of the ADS TFT-LCD.
  • the first auxiliary conductive layer 81 completely covers the data line 5, the step difference between the data line 5 and the pixel electrode 6 can be effectively reduced, the surface of the array substrate is smooth, the alignment film is easy to be coated, and the insufficiently frictional region is not easily formed.
  • the liquid crystal molecules have a good orientation, and the light leakage phenomenon can be improved to some extent.
  • the first auxiliary conductive layer 81 is located directly above the data line 5. As shown in FIG. 4 and FIG. 5, the front projection of the first auxiliary conductive layer 81 on the base substrate 1 is smaller than the data line 5 on the substrate substrate i. Orthographic projection on.
  • the arrangement of the first auxiliary conductive layer 81 can weakly reduce the resistance of the common electrode 8, and cannot reduce the step difference between the data line 5 and the pixel electrode 6, but does not affect the transmittance of the display panel of the ADS TFT-LCD.
  • the first auxiliary conductive layer 81 covers the portion of the data line 5, as shown in FIG. 6 and FIG. 7, the arrangement can reduce the resistance of the common electrode 8 to a certain extent, and can also effectively reduce the first on the data line 5.
  • the auxiliary conductive layer 81 covers the step difference on one side, and plays a role of preventing light leakage to a certain extent.
  • the first auxiliary conductive layer 81 may also completely cover the gate line 2; or the first auxiliary conductive layer 8! is located directly above the gate line 2, and the orthographic projection of the first auxiliary conductive layer 81 on the substrate substrate 1 is smaller than An orthographic projection of the gate line 2 on the base substrate 1; or a portion of the first auxiliary conductive layer 81 covering the gate line 2.
  • the relative positions of the first auxiliary conductive layer 81 and the second auxiliary conductive layer 83 and the gate line 2 or the data line 5 are not limited to the above, as long as the first auxiliary conductive layer 81 and the second auxiliary conductive layer.
  • the arrangement of the layer 83 can reduce the resistance of the common electrode 8 without affecting the transmittance of the display panel of the ADS TFT-LCD, which is not limited in the embodiment of the present invention.
  • the structure of the array substrate further includes a base substrate 1, which is preferably a light-transmissive glass substrate, a quartz substrate, a plastic substrate or the like.
  • a gate line 2 which may have a single layer structure or a multilayer structure.
  • the gate line 2 may be an alloy composed of copper, aluminum, silver, molybdenum, chromium, niobium, nickel, manganese, titanium, tantalum, tungsten or the like or various elements; the gate line 2 is a multilayer structure.
  • it can be copper, titanium, copper, molybdenum, aluminum, molybdenum, etc.
  • the gate line 2 may be directly on the substrate substrate 1, or a buffer layer may be disposed between the gate line 2 and the base substrate 1, and the buffer layer may be silicon nitride or silicon oxide.
  • the thickness of the gate line 2 is preferably 3,500 to 4,400 ⁇ .
  • the gate insulating layer 3 may be a material such as silicon nitride, silicon oxide or silicon oxynitride, which may have a single layer structure or a two-layer structure composed of silicon nitride or silicon oxide.
  • the thickness of the gate insulating layer 3 is preferably 3550 to 4450A.
  • the active layer 4 may be a plurality of semiconductor materials such as polycrystalline silicon, amorphous silicon, single crystal silicon, or semiconductor oxide, and may have a single layer structure or a multilayer structure.
  • the thickness of the active layer 4 is preferably 2,000 to 2,600 ⁇ .
  • the data line 5, the source 51 and the drain 52 may have a single layer structure or a multilayer structure.
  • the data line 5, the source 51 and the drain 52 have a single layer structure and may be an alloy of copper, aluminum, silver, molybdenum, chromium, niobium, nickel, manganese, titanium, tantalum, tungsten or the like or various elements of the above;
  • the data line 5, the source 51 and the drain 52 may be copper, titanium, copper, molybdenum, molybdenum, aluminum, molybdenum or the like.
  • the pixel electrode 6 is electrically connected to the drain electrode 52 and is located on the gate insulating layer 3 as shown in FIGS. 1, 2 and 3.
  • the pixel electrode 6 is often made of a transparent conductive material such as indium tin oxide or indium zinc oxide. Pixel electrode 6
  • the thickness is preferably 400 to 700A.
  • the passivation layer 7 may be silicon nitride, silicon oxide or nitrogen.
  • the single layer structure of silicon oxide may also be a two-layer structure composed of silicon nitride or silicon oxide.
  • an organic resin may be used as the material for the passivation layer 7, such as an acrylic resin, a polyimide, and a polyamide.
  • the thickness of the passivation layer 7 is preferably 200 to 5000 ⁇ .
  • the common electrode 8 includes a first auxiliary conductive layer 81, a transparent conductive layer 82, and a second auxiliary conductive layer 83.
  • the first auxiliary conductive layer 81 and the second auxiliary conductive layer 83 are preferably metal materials having good electrical conductivity, such as copper, aluminum, silver, molybdenum, chromium, etc.; the transparent conductive layer 82 is preferably transparent conductive such as radium oxide oxide or radium oxide oxide. Things.
  • the thickness of the first auxiliary conductive layer 81 and the second auxiliary conductive layer 83 is preferably 900 to 1500 ⁇ .
  • the thickness of the transparent conductive layer 82 is preferably 400 to 700 ⁇ .
  • embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device can be applied to the following electronic products, including but not limited to: liquid crystal panel, electronic paper, organic light emitting diode panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigation device, etc. Functional electronics or components.
  • the embodiment of the present invention provides a method for fabricating an array substrate. As shown in FIG. 8, the method for fabricating the array substrate includes:
  • Step S801 sequentially forming a pattern including a gate line and a pattern including a data line on the base substrate, wherein the gate line and the data line are crisscrossed.
  • a gate metal film can be formed on the base substrate 1 by sputtering, thermal evaporation or the like.
  • a buffer layer may also be formed on the base substrate 1 before the gate metal film is formed. Coating a photoresist on the gate metal film to cover the mask having the pattern of the gate line 2 and the gate 21, then exposing, developing, etching, and finally stripping the photoresist to form a gate line. 2 and the pattern of the gate 21.
  • a gate insulating layer 3 is formed on the pattern.
  • a semiconductor film can be formed on the gate insulating layer 3 by sputtering or the like, covered with a mask having a pattern including the active layer 4, exposed, developed, and etched, and finally the photoresist is stripped to form A pattern of the active layer 4 is included.
  • a layer of data line metal film can be formed on the active layer 4 by sputtering or thermal evaporation.
  • a layer of photoresist is coated on the metal film of the data line, and then covered with a mask having a pattern including the data line 5, the source 5 and the drain 52, exposed, developed, and etched, and finally stripped.
  • the photoresist forms a pattern including the data line 5, the source 51, and the drain 52.
  • a transparent conductive film may be formed on the pattern including the data line 5, the source 51, and the drain 52 by sputtering or the like, and then covered with a mask having a pattern including the pixel electrode 6, and then passed through The steps of exposure, development, etching, etc., finally stripping the photoresist to form a pattern including the pixel electrode 6.
  • the pixel electrode 6 is electrically connected to the drain 52.
  • a passivation layer 7 can be formed on the substrate 1 on which the pattern including the pixel electrode 6 is formed by plasma chemical vapor deposition or the like.
  • the method for fabricating the array substrate further includes:
  • Step S802 forming a pattern including a first auxiliary conductive layer on the formed pattern of the data line, the first auxiliary conductive layer at least partially overlapping the gate line or the data line.
  • a first conductive film may be formed on the formed pattern including the data lines 5 by sputtering or thermal evaporation, and covered with a mask having a pattern including the first auxiliary conductive layer 81, exposed, developed, After etching or the like, the photoresist is stripped to form a pattern including the first auxiliary conductive layer 81.
  • the first auxiliary conductive layer 81 is preferably a metal material having good conductivity such as copper, aluminum, silver, molybdenum, chromium or the like.
  • the thickness of the first auxiliary conductive layer 81 is preferably 900 to 1500A.
  • the difference in the relative position of the first auxiliary conductive layer 81 and the gate line or the data line can be achieved by different designs of the pattern of the first auxiliary conductive layer 81 on the mask.
  • the first auxiliary conductive layer 81 completely covers the gate.
  • Line 2 or data line 5; or the first auxiliary conductive layer 81 is located directly above the gate line 2 or the data line 5, and the orthographic projection of the first auxiliary conductive layer 81 on the substrate substrate i is smaller than the gate line 2 or the data line 5
  • An orthographic projection on the base substrate 1; or the first auxiliary conductive layer 81 covers the gate line 2 or Part of data line 5.
  • a second auxiliary conductive layer 83 may be formed on the pattern of the formed data line 5 including the first auxiliary conductive layer 81.
  • An auxiliary conductive layer 81 is integrally formed, and the second auxiliary conductive layer 83 is located between the periphery of the thin film transistor and the periphery of the pixel electrode 6 on the array substrate. Since the second auxiliary conductive layer 83 and the first auxiliary conductive layer 81 are integrally formed, the second auxiliary conductive layer 83 is also made of a metal material having good conductivity such as copper, aluminum, silver, molybdenum or chromium, and the second auxiliary conductive layer 83 is used. The thickness is preferably 900 ⁇ ! 50 ⁇ .
  • Step S803 forming a pattern including a transparent conductive layer on the formed pattern of the first auxiliary conductive layer.
  • a second conductive film may be formed on the pattern of the formed first auxiliary conductive layer 81 by sputtering or the like. Exposing, developing, etching, etc. are performed using a mask having a pattern including a transparent conductive layer 82, and then the photoresist is stripped to form a pattern including the transparent conductive layer 82, and finally formed as shown in FIG. The structure of the array substrate shown in 3.

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Abstract

一种应用于液晶显示器的阵列基板及其制作方法、显示装置及电子产品，涉及显示技术领域，能够改善ADS　TFT-LCD的显示面板的画面泛绿现象，且易于实现。阵列基板，包括衬底基板（1）、位于衬底基板（1）上的纵横交错的栅线（2）和数据线（5）、以及公共电极（8），公共电极（8）包括透明导电层（82）和位于透明导电层（82）之下的第一辅助导电层（81），公共电极（8）的第一辅助导电层（81）与栅线（2）或数据线（5）至少部分重叠。

Description

阵列基板及其制作方法、 显示装置及电子产品
Figure imgf000002_0001
装置及电子产品。
高级超维场转换技术型薄膜晶体管液晶显示器 （Advanced Super Dimension Switch Thin Film Transistor Liquid Crystal Display , 简禾尔 ADS TFT-LCD) 通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极与板状 电极间产生的电场形成多维电场， 使显示面板内的狭缝电极间和狭缝电极正 上方的液晶分子都能够产生偏转， 从而提高液晶分子工作效率并增大了透光 效率。 其显示效果主要由显示面板决定。 显示面板包括阵列基板、 彩膜基板 和位于两块基板之间的液晶分子层。
ADS TFT-L€D的显示面板常出现画面泛绿等不良现象。画面泛绿产生的 主要原因在于阵列基板上设置的公共电极的电压发生畸变， 即公共电极的电 压的波形发生偏离， 或者公共电极的电压发生衰减， 即电压的数值随着传输 距离的增加而减小， 因此可以通过防止公共电极的电压发生畸变衰减来防止 画面泛绿等不良现象的出现。
( --) 要解决的技术问题
本发明所要解决的技术问题在于提供一种阵列基板及其制作方法、 显示 装置及电子产品， 从而能够改善 ADS TFTXCD的显示面板的画面泛绿现象， 实现较为筒单。
(二） 技术方案
为解决上述技术问题， 本发明的第一方面提供了一种阵列基板， 采用如 下技术方案：
一种阵列基板， 包括衬底基板、 位于所述衬底基板上的纵横交错的栅线 和数据线、 以及公共电极， 所述公共电极包括透明导电层和位于所述透明导 电层之下的第一辅助导电层， 所述公共电极的第一辅助导电层与所述栅线或 所述数据线至少部分重叠。
所述的阵列基板， 还包括薄膜晶体管和像素电极， 所述公共电极还包括 位于所述薄膜晶体管的外围和所述像素电极的外围之间的第二辅助导电层， 所述第二辅助导电层与所述第一辅助导电层一体成型， 所述透明导电层位于 所述第二辅助导电层之上。
所述第一辅助导电层和所述第二辅助导电层的材质为金属， 优选的， 所 述金属是铜、 铝、 银、 钼、 铬或它们的组合。
所述第一辅助导电层完全覆盖所述栅线或所述数据线。
所述第一辅助导电层位于所述栅线或所述数据线的正上方， 且所述第一 辅助导电层在所述衬底基板上的正投影小于所述栅线或所述数据线在所述衬 底基板上的正投影。
所述第一辅助导电层覆盖所述栅线或所述数据线的部分。
所述第一辅助导电层和所述第二辅助导电层的厚度为 90O4500 A， 而所 述透明导电层的厚度为 400〜700A。
以上所述的阵列基板包括衬底基板、位于衬底基板上的纵横交错的栅线、 数据线和公共电极， 公共电极包括透明导电层和位于透明导电层之下的第一 辅助导电层， 公共电极的第一辅助导电层与栅线或数据线重叠。 具有如上所 述结构的阵列基板上设置的公共电极包括第一辅助导电层和透明导电层， 其 中第一辅助导电层和透明导电层并联， 共同构成公共电极， 因此公共电极的 电阻较小， 降低了公共电极电压的畸变衰减， 使得公共电极的电压的波形不 易发生偏离， 且公共电极的电压的数值随着传输距离的增加而无明显减小， 改善了画面泛绿现象， 提高了 ADS TFT-LCD的显示效果。
本发明的第二方面提供了一种显示装置， 包括如上所述的阵列基板。 为了进一步解决上述问题， 本发明的第≡方面还提供了一种阵列基板的 制作方法， 包括：
在所述衬底基板上依次形成包括栅线的图形、 包括数据线的图形， 所述 栅线和所述数据线纵横交错； 在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第一 辅助导电层与所述栅线或所述数据线至少部分重叠；
在所形成的所述第一辅助导电层的图形之上， 形成包括所述透明导电层 的图形。
在所形成的数据线的图形上形成包括第一辅助导电层的同时形成第二辅 助导电层， 所述第二辅助导电层与所述第一辅助导电层一体成型， 所述第二 辅助导电层位于所述阵列基板的薄膜晶体管的外围和像素电极的外 之间； 所述在所形成的所述第一辅助导电层的图形上， 形成包括透明导电层的 图形包括：
在所形成的第一辅助导电层和第二辅助导电层的图形之上， 形成包括所 述透明导电层的图形。
所述第一辅助导电层和所述第二辅助导电层的材质为金属， 优选的， 所 述金属是铜、 铝、 银、 钼、 铬或它们的组合。
所述第一辅助导电层和所述第二辅助导电层的厚度为 90O4500A, 而所 述透明导电层的厚度为 400〜700A。
在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第一 辅助导电层与所述栅线或所述数据线至少部分重叠包括：
所述第一辅助导电层完全覆盖所述栅线或所述数据线； 或者
所述第一辅助导电层位于所述栅线或所述数据线的正上方， 且所述第一 辅助导电层在所述衬底基板上的正投影小于所述栅线或所述数据线在所述衬 底基板上的正投影； 或者
所述第一辅助导电层覆盖所述栅线或所述数据线的部分。
(三) 有益效果
从以上所述可以看出， 所述的阵列基板包括衬底基板、 位于衬底基板上 的纵横交错的栅线、 数据线和公共电极， 公共电极包括透明导电层和位于透 明导电层之下的第一辅助导电层， 公共电极的第一辅助导电层与栅线或数据 线重叠。 具有如上所述结构的阵列基板上设置的公共电极包括第一辅助导电 层和透明导电层， 其中第一辅助导电层和透明导电层并联， 共同构成公共电 极， 因此公共电极的电阻较小， 降低了公共电极电压的畸变衰减， 使得公共 电极的电压的波形不易发生偏离， 且公共电极的电压的数值随着传输距离的 增加而无明显减小， 改善了画面泛绿现象， 提高了 ADS TFT-LCD的显示效 m
木
Figure imgf000005_0001
3实施 技术中的技术方案， 下面将对实 述中所需要使用的附图作筒单地丌¾3， 显而易见地， 下面描述中的附 是本发明的一些实施例， 对于： 普通技术人员来讲， 在不付出创 造性劳动的前提下， 还可以根据这些附图获得其他的附图
图 1为本发 I实施例提供的第一种阵列基板的平面示意图；
图 2为本发 I实施例提供的图 i所示的阵列基板的 A- 截面示意图； 图 3为本发 1实施例提供的图 1所示的阵列基板的 B- B'截面示意图； 图 4为本发 I实施例提供的第二种阵列基板的数据线截面示意图； 图 5为本发 1实施例提供的第二种阵列基板的薄膜晶体管截面示意 图 6为本发 I实施例提供的第三种阵列基板的数据线横截面示意图； 图 7为本发 1实施例提供的第 种阵列基板的薄膜晶体管截面示意图; 图 8为本发 实施例提供的一种阵列基板的
Figure imgf000005_0002
图 9a-图 9d为本
Figure imgf000005_0003
i一衬
3—栅极绝缘层； 数据线；
5卜源极； 52—漏极； 像素电极； 7—钝化层； 8—公共电极； 81— -辅助导电层; 82—透明导电层; 83- 第二辅助导电层
下面结合^图和实施例， 对本发明的具体实施方式做进一歩描述。 以下 实施例仅用于说明本发明， 但不 ^来限制本发明的范围。
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的^图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员所获得的所有其他实施例， 都属 于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一 "、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接"或者"相连" 等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接, 不管是直接的还是间接的。 "上"、 "下"、 "左"、 "右"等仅用于表示相对位置 关系， 当被描述对象的绝对位置改变后， 则该相对位置关系也相应地改变。
本发明实施例提供了一种阵列基板， 如图 1-图 3所示， 该阵列基板包括 衬底基板 I、位于衬底基板 1上的纵橫交错的栅线 2和数据线 5、 以及公共电 极 8。 公共电极 8包括透明导电层 82和位于透明导电层 82之下的第一辅助 导电层 81， 公共电极的第一辅助导电层 81与栅线 2或数据线 5至少部分重 叠。
具有如上所述结构的阵列基板上设置的公共电极包括第一辅助导电层和 透明导电层， 其中第一辅助导电层和透明导电层并联， 共同构成公共电极， 因此公共电极的电阻较小， 降低了公共电极电压的畸变衰减， 使得公共电极 的电压的波形不易发生偏离， 且公共电极的电压的数值随着传输距离的增加 而无明显减小， 改善了画面泛绿现象， 提高了 ADS TFTTLCD的显示效果。
迸一歩地， 为了更好的降低公共电极 8的电阻， 公共电极 8还可以包括 位于薄膜晶体管的外围和像素电极 6的外围之间的第二辅助导电层 83， 第二 辅助导电层 83与第一辅助导电层 81—体成型，透明导电层 82位于第二辅助 导电层 83之上。
具体地， 第一辅助导电层 81优选为导电性良好的金属材料， 如铜、 铝、 银、 钼、 铬等； 透明导电层 82优选为氧化镭锡、 氧化镭锌等透明导电物； 第 二辅助导电层 83与第一辅助导电层 81—体成型， 也优选为如铜、 铝、 银、 钼、 铬等导电性良好的金属材料。
目前， 公共电极 8—般采用的是氧化镭锡、 氧化镭锌等透明导电物， 具 有良好的透光性。 在本发明实施例中公共电极 8包括第一辅助导电层 81、 透 明导电层 82或第二辅助导电层 83， 而第一辅助导电层 81和第二辅助导电层 83选用的是不透光的金属材料。 因此， 为了保证阵列基板上不透明的第二辅 助导电层 83的设置不对 ADS TFT-LCD显示面板的透过率产生影响， 第二辅 助导电层 83 在阵列基板上的正投影的宽度及位置应满足阵列基板与彩膜基 板对盒时， 彩膜基板上的黑矩阵可以将第二辅助导电层 83遮盖。类似地， 为 了保证阵列基板上不透明的第一辅助导电层 81的设置不对 ADS TFT-LCD显 示面板的透过率产生影响，第一辅助导电层 81在阵列基板上的正投影的宽度 及位置也需要进行合理设置，示例性地可以采用如下几种方案之一进行设置： 方案一， 第一辅助导电层 81完全覆盖数据线 5 , 如图 1-图 3所示， 第一 辅助导电层 81位于数据线 5上方， 第一辅助导电层 81的宽度大于数据线 5 的宽度， 因此可以在最大程度上降低公共电极 8的电阻， 但第一辅助导电层 81 的宽度需要小于彩膜基板上相应位置的黑矩阵的宽度， 才可以不对 ADS TFT-LCD的显示面板的透过率造成影响。 当第一辅助导电层 81 完全覆盖数 据线 5时， 还可以有效降低数据线 5与像素电极 6之间的段差， 使阵列基板 表面平滑， 取向膜易于涂覆， 而且不易形成摩擦不充分区域， 使液晶分子具 有较好的取向， 在一定程度上还可以改善漏光现象。
方案二，第一辅助导电层 81位于数据线 5的正上方，如图 4和图 5所示， 第一辅助导电层 81在衬底基板 1上的正投影小于数据线 5在衬底基板 i上的 正投影。第一辅助导电层 81的设置可以微弱降低公共电极 8的电阻， 无法降 低数据线 5与像素电极 6之间的段差， 但不会对 ADS TFT-LCD的显示面板 的透过率产生影响。
方案三， 第一辅助导电层 81覆盖数据线 5的部分， 如图 6和图 7所示， 这种设 可以在一定程度上降低公共电极 8的电阻， 也可以有效降低数据线 5上第一辅助导电层 81覆盖一侧的段差,在一定程度上起到防止漏光的作用。 类似地， 第一辅助导电层 81也可以完全覆盖栅线 2; 或者第一辅助导电 层 8!位于栅线 2的正上方， 且第一辅助导电层 81在衬底基板 1上的正投影 小于栅线 2在衬底基板 1上的正投影；或者第一辅助导电层 81覆盖栅线 2的 部分。
需要说明的是， 第一辅助导电层 81和第二辅助导电层 83与栅线 2或者 数据线 5的相对位置不局限于以上所述几种，只要第一辅助导电层 81和第二 辅助导电层 83的设置既可以降低公共电极 8的电阻，又不影响 ADS TFT-LCD 的显示面板的透过率即可， 本发明实施例对此不进行限制。
具体地， 阵列基板的结构还包括衬底基板 1， 衬底基板 1优选为透光性 好的玻璃基板、 石英基板、 塑料基板等。
如图 1、 图 2和图 3所示， 位于衬底基板 1上的是栅线 2, 栅线 2可以为 单层结构也可以为多层结构。 栅线 2为单层结构时， 可以为铜、 铝、 银、 钼、 铬、 钕、 镍、 锰、 钛、 钽、 钨等材料或以上各种元素组成的合金； 栅线 2为 多层结构时， 可以为铜\钛、 铜^目、 钼 \铝\钼等。 栅线 2可以直接位于衬底基 板 1上， 也可以在栅线 2与衬底基板 1之间设置缓冲层， 缓冲层可以为氮化 硅或者氧化硅。 栅线 2的厚度优选为 3500~4400 A。
位于栅线 2上的是栅极绝缘层 3 , 如图 1、 图 2和图 3所示。 栅极绝缘层 3 可以为氮化硅、 氧化硅或氮氧化硅等材料， 其可以为单层结构， 也可以为 由氮化硅或氧化硅构成的双层结构。栅极绝缘层 3的厚度优选为 3550〜4450A。
位于栅极绝缘层 3上的是有源层 4, 如图 1、 图 2和图 3所示。 有源层 4 可以为多晶硅、 非晶硅、 单晶硅、 半导体氧化物等多种半导体材料， 可以为 单层结构也可以为多层结构。 有源层 4的厚度优选为 2000~2600A。
位于有源层 4上的是数据线 5、 源极 51和漏极 52， 如图 1、 图 2和图 3 所示。 数据线 5、 源极 51和漏极 52可以为单层结构也可以为多层结构。 数 据线 5、 源极 51和漏极 52为单层结构 ， 可以为铜、 铝、 银、 钼、 铬、 钕、 镍、 锰、 钛、 钽、 钨等材料或以上各种元素组成的合金； 数据线 5、 源极 51 和漏极 52为多层结构时， 可以为铜\钛、 铜\钼、 钼 \铝\钼等。
像素电极 6与漏极 52电连接， 位于栅极绝缘层 3上， 如图 1、 图 2和图 3所示。 像素电极 6遥常选用氧化铟锡、 氧化铟锌等透明导电物。像素电极 6 的厚度优选为 400〜700A。
如图 1、 图 2和图 3所示， 位于数据线 5、 源极 51、 漏极 52和像素电极 6上的是钝化层 7，钝化层 7可以为氮化硅、氧化硅或者氮氧化硅的单层结构， 也可以为氮化硅或氧化硅构成的双层结构。 此外， 还可以选用有机树脂作为 钝化层 7所用的材料， 例如丙烯酸类树脂、 聚酰亚胺和聚酰胺等。 钝化层 7 的厚度优选为 200〜5000A。
位于钝化层 7上的是公共电极 8 , 如图！、 图 2和图 3所示。 公共电极 8 包括第一辅助导电层 81、 透明导电层 82和第二辅助导电层 83。 第一辅助导 电层 81和第二辅助导电层 83优选为导电性良好的金属材料， 如铜、 铝、 银、 钼、 铬等； 透明导电层 82优选为氧化镭锡、 氧化镭锌等透明导电物。 第一辅 助导电层 81和第二辅助导电层 83的厚度优选为 900〜1500A。 透明导电层 82 的厚度优选为 400〜700A。
此外， 本发明实施例还提供了一种显示装置， 该显示装置包括如上所述 的阵列基板。 该显示装置可以应用于如下的电子产品当中， 包括但不限于： 液晶面板、 电子纸、 有机发光二极管面板、 手机、 平板电脑、 电视机、 显示 器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的电子产品或部件。
本发明实施例提供了一种阵列基板的制作方法， 如图 8所示， 该阵列基 板的制作方法包括：
步骤 S801、在衬底基板上依次形成包括栅线的图形、包括数据线的图形, 栅线和数据线纵横交错。
经过上述步骤之后的阵列基板如图 9a和图％所示。 其具体实施过程可 以如下所述：
首先， 可以通过溅射、热蒸发等方法在衬底基板 1上形成一层栅金属膜。 在形成栅金属膜之前， 还可以在衬底基板 1 上先形成一层缓冲层。 在栅金属 膜上涂覆一层光刻胶,使 ^具有包括栅线 2和栅极 21图形的掩膜板进行遮盖, 然后曝光、显影、刻蚀， 最后剥离光刻胶， 形成包括栅线 2和栅极 21的图案。
其次，可以通过等离子体增强化学气相沉积等方法在栅线 2和栅极 21的 图案上形成栅极绝缘层 3。
再次， 可以通过溅射等方法在栅极绝缘层 3上形成半导体薄膜， 使用具 有包括有源层 4的图形的掩膜板进行遮盖， 进行曝光、 显影和刻蚀， 最后剥 离光刻胶， 形成包括有源层 4的图案。
接着， 可以通过溅射或者热蒸发等方法， 在有源层 4上形成一层数据线 金属膜。 在数据线金属膜上涂覆一层光刻胶， 然后使用具有包括数据线 5、 源极 5 !和漏极 52的图形的掩膜板进行遮盖， 迸行曝光、 显影和刻蚀， 最后 剥离光刻胶， 形成包括数据线 5、 源极 51和漏极 52的图案。
然后， 可以通过溅射等方法在包括数据线 5、 源极 51和漏极 52的图案 上形成一层透明导电薄膜， 然后使用具有包括像素电极 6的图形的掩膜板迸 行遮盖， 然后经过曝光、 显影、 刻蚀等步骤， 最后剥离光刻胶， 形成包括像 素电极 6的图案。 其中像素电极 6与漏极 52电连接。
最后， 可以通过等离子体化学气相沉积等方法在形成了包括像素电极 6 的图案的衬底基板 1上形成一层钝化层 7。
如图 8所示， 该阵列基板的制作方法还包括：
歩骤 S802、在所形成的数据线的图形上形成包括第一辅助导电层的图形， 第一辅助导电层与栅线或数据线至少部分重叠。
经过上述步骤之后的阵列基板如图 9c和图 9d所示。 其具体实施过程可 以如下所述：
可以使用溅射或者热蒸发等方法在形成的包括数据线 5的图案上形成一 层第一导电薄膜， 使用具有包括第一辅助导电层 81 的图形的掩膜板进行遮 盖， 经过曝光、 显影、 刻蚀等步骤后， 剥离光刻胶， 形成包括第一辅助导电 层 81的图案。 第一辅助导电层 81优选为导电性良好的金属材料， 如铜、 铝、 银、 钼、 铬等。 第一辅助导电层 81的厚度优选为 900〜1500A。
迸一歩地，可以通过对掩膜板上第一辅助导电层 81图形的不同设计来实 现第一辅助导电层 81与栅线或者数据线相对位置的不同，例如第一辅助导电 层 81完全覆盖栅线 2或数据线 5 ; 或者第一辅助导电层 81位于栅线 2或数 据线 5的正上方， 且第一辅助导电层 81在衬底基板 i上的正投影小于栅线 2 或数据线 5在衬底基板 1上的正投影；或者第一辅助导电层 81覆盖栅线 2或 数据线 5的部分。
此外， 为了进一步降低公共电极 8 的电阻， 还可以在所形成的数据线 5 的图形上形成包括第一辅助导电层 81 的同日寸形成第二辅助导电层 83， 第二 辅助导电层 83与第一辅助导电层 81—体成型，第二辅助导电层 83位于阵列 基板上薄膜晶体管的外围和像素电极 6的外围之间。 由于第二辅助导电层 83 和第一辅助导电层 81—体成型， 因此第二辅助导电层 83也选用铜、 铝、 银、 钼、 铬等导电性良好的金属材料， 第二辅助导电层 83 的厚度优选为 900〜！ 50θΛ。
步骤 S803、 在所形成的第一辅助导电层的图形之上， 形成包括透明导电 层的图形。
可以通过溅射等方法， 在所形成的第一辅助导电层 81的图形上， 形成一 层第二导电薄膜。使用具有包括透明导电层 82图形的掩膜板遮盖，进行曝光、 显影、 刻蚀等歩骤， 然后剥离光刻胶， 形成包括透明导电层 82的图案， 最后 形成如图 I、 图 2 和图 3所示的阵列基板的结构。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

1、 一种阵列基板， 包括衬底基板、 位于所述衬底基板上的纵横交错的栅 线和数据线、 以及公共电极， 其特征在于，
所述公共电极包括透明导电层和位于所述透明导电层之下的第一辅助导 电层， 所述公共电极的第一辅助导电层与所述栅线或所述数据线至少部分重 叠。
2、 根据权利要求 1所述的阵列基板， 还包括薄膜晶体管和像素电极， 其 特征在于，
所述公共电极还包括位于所述薄膜晶体管的外围和所述像素电极的外 之间的第二辅助导电层， 所述第二辅助导电层与所述第一辅助导电层一体成 型， 所述透明导电层位于所述第二辅助导电层之上。
3、 根据权利要求 2所述的阵列基板， 其特征在于，
所述第一辅助导电层和所述第二辅助导电层的材质为金属。
4、 根据权利要求 3所述的阵列基板， 其特征在于， 所述金属是铜、 铝、 银、 钼、 铬或它们的组合。
5、 根据权利要求 1 4中任一项所述的阵列基板， 其特征在于，
所述第一辅助导电层完全覆盖所述栅线或所述数据线。
6、 根据权利要求 1 4中任一项所述的阵列基板， 其特征在于，
所述第一辅助导电层位于所述栅线或所述数据线的正上方， 且所述第一 辅助导电层在所述衬底基板上的正投影小于所述栅线或所述数据线在所述衬 底基板上的正投影。
7、 根据权利要求 1 4中任一项所述的阵列基板， 其特征在于，
所述第一辅助导电层覆盖所述栅线或所述数据线的部分。
8、 根据权利要求 2 4中任一项所述的阵列基板， 其特征在于，
所述第一辅助导电层和所述第二辅助导电层的厚度为 900〜i 500 A。
9、 根据权利要求 i 8中任一项所述的阵列基板， 其特征在于，
所述透明导电层的厚度为 400〜700A。
10、 一种显示装置， 其特征在于， 包括权利要求 1-9 中任一项所述的阵 列基板。
I K 一种阵列基板的制作方法， 其特征在于， 包括：
在衬底基板上依次形成包括栅线的图形、 包括数据线的图形， 所述栅线 和所述数据线纵横交错；
在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第一 辅助导电层与所述栅线或所述数据线至少部分重叠；
在所形成的所述第一辅助导电层的图形之上， 形成包括透明导电层的图 形。
12、 根据权利要求 11所述的阵列基板的制作方法， 其特征在于， 在所形 成的数据线的图形上形成包括第一辅助导电层的同时形成第二辅助导电层， 所述第二辅助导电层与所述第一辅助导电层一体成型， 所述第二辅助导电层 位于所述阵列基板的薄膜晶体管的外围和像素电极的外围之间；
所述在所形成的所述第一辅助导电层的图形上， 形成包括透明导电层的 图形包括：
在所形成的第一辅助导电层和第二辅助导电层的图形之上， 形成包括所 述透明导电层的图形。
13、 根据权利要求 12所述的阵列基板的制作方法， 其特征在于， 所述第一辅助导电层和所述第二辅助导电层的材质为金属。
14、 根据权利要求 13所述的阵列基板的制作方法， 其特征在于， 所述金 属是铜、 铝、 银、 钼、 铬或它们的组合。
15、 根据权利要求 12-14 中任一项所述的阵列基板的制作方法， 其特征 在于，
所述第一辅助导电层和所述第二辅助导电层的厚度为 900〜1500A。
16、 根据权利要求 11 15 中任一项所述的阵列基板的制作方法， 其特征 在于， 在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第 一辅助导电层与所述栅线或所述数据线至少部分重叠包括：
所述第一辅助导电层完全覆盖所述栅线或所述数据线。
17、 根据权利要求 11 15 中任一项所述的阵列基板的制作方法， 其特征 在于， 在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第 一辅助导电层与所述栅线或所述数据线至少部分重叠包括：
所述第一辅助导电层位于所述栅线或所述数据线的正上方， 且所述第一 辅助导电层在所述衬底基板上的正投影小于所述栅线或所述数据线在所述衬 底基板上的正投影。
18、 根据权利要求 11 15 中任一项所述的阵列基板的制作方法， 其特征 在于， 在所形成的数据线的图形上形成包括第一辅助导电层的图形， 所述第 一辅助导电层与所述栅线或所述数据线至少部分重叠包括：
所述第一辅助导电层覆盖所述栅线或所述数据线的部分。
19、 根据权利要求 11 18 中任一项所述的阵列基板的制作方法， 其特征 在于，
所述透明导电层的厚度为 400〜700A。
20、 一种电子产品， 其特征在于， 包括权利要求 10所述的显示装置。
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