WO2004025699A3 - Assemblies having stacked semiconductor chips - Google Patents

Assemblies having stacked semiconductor chips Download PDF

Info

Publication number
WO2004025699A3
WO2004025699A3 PCT/US2003/028041 US0328041W WO2004025699A3 WO 2004025699 A3 WO2004025699 A3 WO 2004025699A3 US 0328041 W US0328041 W US 0328041W WO 2004025699 A3 WO2004025699 A3 WO 2004025699A3
Authority
WO
WIPO (PCT)
Prior art keywords
microelectronic assembly
assemblies
semiconductor chips
stacked semiconductor
stacked microelectronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/028041
Other languages
French (fr)
Other versions
WO2004025699A2 (en
Inventor
Teck-Gyu Kang
Yoichi Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Solutions LLC
Original Assignee
Tessera LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tessera LLC filed Critical Tessera LLC
Priority to AU2003270392A priority Critical patent/AU2003270392A1/en
Publication of WO2004025699A2 publication Critical patent/WO2004025699A2/en
Publication of WO2004025699A3 publication Critical patent/WO2004025699A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A stacked microelectronic assembly comprises a continuous sheet (20) including a core panel (26) and a plurality of side panels (28, 30, 32, 34), each having a folded portion (28a’, 30a’, 32a’, 34a’) that connects the side panel to an edge of the core panel. At least two of the panels are at least partially horizontally aligned with one another in a stack. During manufacture of a stacked microelectronic assembly, failed microelectronic elements are identified and associated side panels thereof are simply cut-off. This results in the production of a usable stacked microelectronic assembly albeit of reduced capacity, or reduced functionality.
PCT/US2003/028041 2002-09-11 2003-09-08 Assemblies having stacked semiconductor chips Ceased WO2004025699A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003270392A AU2003270392A1 (en) 2002-09-11 2003-09-08 Assemblies having stacked semiconductor chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9888002P 2002-09-11 2002-09-11
US60/4098,880 2002-09-11

Publications (2)

Publication Number Publication Date
WO2004025699A2 WO2004025699A2 (en) 2004-03-25
WO2004025699A3 true WO2004025699A3 (en) 2004-06-17

Family

ID=31990051

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/028041 Ceased WO2004025699A2 (en) 2002-09-11 2003-09-08 Assemblies having stacked semiconductor chips

Country Status (2)

Country Link
AU (1) AU2003270392A1 (en)
WO (1) WO2004025699A2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7224056B2 (en) 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US7265440B2 (en) 2003-06-16 2007-09-04 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7479398B2 (en) 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7566955B2 (en) 2001-08-28 2009-07-28 Tessera, Inc. High-frequency chip packages
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157309B2 (en) 2004-04-09 2007-01-02 Tessera, Inc. Manufacture of microelectronic fold packages
US8143095B2 (en) 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
US7755457B2 (en) 2006-02-07 2010-07-13 Harris Corporation Stacked stripline circuits
JP7141877B2 (en) * 2018-07-18 2022-09-26 キオクシア株式会社 semiconductor storage device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5448511A (en) * 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
US5776797A (en) * 1995-12-22 1998-07-07 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5448511A (en) * 1994-06-01 1995-09-05 Storage Technology Corporation Memory stack with an integrated interconnect and mounting structure
US5776797A (en) * 1995-12-22 1998-07-07 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7566955B2 (en) 2001-08-28 2009-07-28 Tessera, Inc. High-frequency chip packages
US7265440B2 (en) 2003-06-16 2007-09-04 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7642629B2 (en) 2003-06-16 2010-01-05 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7479398B2 (en) 2003-07-03 2009-01-20 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7495341B2 (en) 2003-07-03 2009-02-24 Tessera Technologies Hungary Kft. Methods and apparatus for packaging integrated circuit devices
US7224056B2 (en) 2003-09-26 2007-05-29 Tessera, Inc. Back-face and edge interconnects for lidded package
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
US9548145B2 (en) 2007-01-05 2017-01-17 Invensas Corporation Microelectronic assembly with multi-layer support structure

Also Published As

Publication number Publication date
AU2003270392A1 (en) 2004-04-30
WO2004025699A2 (en) 2004-03-25
AU2003270392A8 (en) 2004-04-30

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