WO2002021498A1

WO2002021498A1 - Circuit and method of driving data line by low power in a lcd

Info

Publication number: WO2002021498A1
Application number: PCT/KR2001/001517
Authority: WO
Inventors: Oh-Kyong Kwon
Original assignee: Neotek Research Co Ltd
Current assignee: Neotek Research Co Ltd
Priority date: 2000-09-08
Filing date: 2001-09-07
Publication date: 2002-03-14
Anticipated expiration: 2003-03-08
Also published as: TW565824B; KR20020020416A; KR100366315B1; AU2001286304A1

Abstract

The present invention relates to the source driving circuit of Thin Film Transistor-Liquid crystal Device (TFT-LCD). The circuit of the present invention, the low power source driving circuit for driving data line of TFT-LCD according to video data, comprising the means of: digital-analog converter; polarity modulator; output buffer; and switching means. According to the present invention, as preventing overcharging or overdischarging as charging and discharging until not fixed voltage level but level controlled by video signal in polarity modulation, it is possible to prevent unnecessary power consumption.

Description

CIRCUIT AND METHOD OF DRIVING DATA LINE BY LOW

POWER IN A LCD

TECHNICAL FIELD The present invention relates to a source driving circuit of a thin film transistor

(TFT) liquid crystal device (LCD) and, more particularly, to a low power source driving circuit and method for driving data lines with low power.

BACKGROUND ART The liquid crystal display (LCD), which is ordinarily used for displaying characters, symbols or graphics, is a display device incorporating the liquid crystal technology and the semiconductor technology, in which the liquid crystal's optical feature of changing molecular arrays by electric fields is used. The thin film transistor (TFT) LCD uses a TFT as a switching component turning on or off the internal pixels. As the TFT is turned on or off, the pixels are accordingly turned on or off. As shown in Figure 1, in a general TFT liquid crystal display, cells constituting pixels are arranged in an array form. Each cell comprises a TFT 132 for the switching function, a liquid crystal cell 134, and a storage capacitor Cs. Sources for TFTs are connected commonly in the direction of the column, forming data lines Dl-DN, and then are connected to a source driver 120. Gates of TFTs are connected commonly in the direction of the row, forming scan lines Sl-SM, and then are connected to a gate driver 110. Thus, a display device of NxM resolution (i.e., SVGA of 800x600, XGA of 1024x768, UXGA of 1600x1200) is implemented. The source driver 120 is also called as a data driver or a column driver. The gate driver 110 is also called as a row driver. As shown in Figure 1, a liquid crystal cell 134 is connected to the drain of a TFT 132 through a pixel electrode and the other side is connected to the common electrode. The pixel electrode is made of ITO which is transparent and electrically conductive. When the on signal is supplied to the TFT gate, the pixel electrode supplies the signal voltage supplied through the source driver 120 to the liquid crystal cell 134. The common electrode is also made of ITO and supplies the common voltage Vcom to the liquid crystal cell.

The storage capacitor Cs sustains the signal voltage supplied to the pixel electrode (pixel ITO) for a certain period of time. It also controls the light transmission rate of a pixel by changing the array status of the liquid crystal cell through charging and discharging. One end of the storage capacitor Cs may be connected to an independent electrode or a gate electrode. If it is connected to a gate electrode, the structure thereof is called the "storage on gate" method.

When driving the above-described pixel array, if the voltage is supplied only in one direction of the liquid crystal, the liquid crystal is quickly degraded. Thus, the inversion, i.e., the method of periodically changing the direction of supplying the image data voltage, is used. The data voltage direction is usually changed to the opposing direction by the period of every one field. There are three types of inversion. According to the field inversion method, in each field, all pixels of the panel change the voltage polarity at the same time. According to the line inversion method, the pixel line connected to a certain scanning line is inverted alternately. According to the dot inversion method, each pixel is separately inverted. In any of the above three methods, when inversion is conducted, the pixel voltage (voltage supplied to the pixel electrode from the TFT drain) in relation to the common voltage Vcom is changed from the positive (+) direction to the negative (-) direction and vice versa.

Figure 2 illustrates a part of a conventional source driving circuit of the related art. It illustrates a D/A converter 21, an output buffer 22, an odd number polarity modulator 23, an even number polarity modulator 24, and MUX 25. As shown in Figure 2, latch clock is generated from a shift register (not shown in the drawing), and the digital video data inputted from a video card is inputted to the D/A converter 21 after being latched in the latch unit (not shown) according to the latch clock.

The image signal voltage converted into an analog signal at the D/A converter 21 passes the output buffer 22 and then is classified into the odd number data line or the even number data line. The odd number data line's polarity is modulated according to the output of the odd number polarity modulator 23 and is supplied to the data line through the MUX 25. The even number data line's polarity is modulated according to the output of the even number polarity modulator 24 and is supplied to the data line through the MUX 25.

Thus, a source driving circuit according to a prior art requires MUX switches for each column. As a result, the circuit becomes complex and additional power is consumed for driving the switches.

Figure 3 a illustrates the output waveform of a multi-step source driving circuit for supplying the image signal to data lines by utilizing the above-described source driving circuit.

As shown in Figure 3a, VSS voltage is ON VDD voltage is ION and the common voltage Ncom is 5N. The medium voltage of the positive image signals supplied to pixel electrodes for the inversion is 7J5N. The medium voltage of the negative image signals is 2.25N The positive image signals are located in the oblique line area around the positive medium voltage NH. The negative image signals are located in the oblique line area around the negative medium voltage NL.

Conventionally, in each line time, the polarity modulation is conducted from and to the fixed voltages NH and NL (B of Figure 3a) and then, after such modulation, the gray scale display is conducted (C and D of Figure 3a). As shown in Figure 3a, if the load capacitor (C _OAD) is operated upon dividing the voltage between N2 and Nl into five parts (generally, Ν sub-divisions), the electric power consumed therefor is reduced to the level of 1/5 of that in the single step driving as shown in Equation 1 and Equation 2 (in the case of Ν steps, 1/Ν electric power).

(Α7A 1 p STEP =C ^V ^y 2 c F= c P COAΨ In Figure 3b, the load capacitance (C_LOAD) is the sum of capacitances of N data lines (column lines). N is 1/2 of the number of outputs of one source driver.

The conventional source driving method of a liquid crystal device described above obtains high efficiency in the all-black mode or in the all-gray mode, as shown in Figure 4a. ^* However, in the all-white mode, as shown in Figure 4b, the charging/discharging occurs up to the medium voltages (VH:7J5V, VL.2.25V) so as to cause the polarity modulation. Thus, overcharging occurs and the electric power is wasted unnecessarily. In other words, in the all-black mode, the black level is higher than the medium voltage NH in the positive and lower than the medium voltage NL in the negative. Thus, even if the medium voltages are modulated, high efficiency may be achieved. In contrast, in the all-white mode, the white level is lower than the medium voltage NH in the positive and higher than the medium voltage VL in the negative, requiring a narrow swing width. Nonetheless, in the all-white mode, overcharging occurs (i.e., the voltage is charged up to a higher level than the required level) and thus, additional electric power waste occurs. Therefore, so as to raise efficiency in saving the electric power regardless of the relevant mode, it is necessary to eliminate the overcharging.

DISCLOSURE OF THE INVENTION

The object of the present invention is to provide a source driving circuit and driving method with a raised electric power efficiency by charging only up to certain voltages as determined by the relevant image signal voltage rather than charging up to a certain fixed medium voltage and thereby preventing the overcharging. It is another object of the present invention to provide a source driving circuit with a simple circuit structure without MUX switches required for each line of the conventional driving circuit by controlling operation amplifiers of the output buffers collectively with a few switches.

In order to achieve the above objects, the present invention's multi-step source driving circuit for driving data lines of a TFT liquid crystal display according to image data comprises: a digital-analog converter for converting the image data into analog signals; a polarity modulator for providing multi-step charging and discharging voltages for the polarity modulation; an output buffer for receiving image signals inputted from the digital-analog converter and conducting the polarity modulation through charging and discharging at the polarity modulation period in which the output buffers are connected to the polarity modulator, wherein at the time of charging, if the charging voltage of the polarity modulator is higher than the image signals, the level of image signals becomes the saturation level and at the time of discharging, if the discharging voltage of the polarity modulator is lower than the image signals, the level of image signals becomes the saturation level, and at the gray-scale display period, the polarity modulated outputs are supplied to the relevant data lines; and switching means for connecting the polarity modulator to the output buffers at the polarity modulation period and connecting the output buffers to the power supplier at the gray-scale display period.

In order to achieve the above objects, the present invention's low power source driving method for data lines of a TFT liquid crystal display conducts the charging or discharging only up to the levels as controlled by image signals instead of up to certain fixed voltage levels as medium voltages for the polarity modulation, thereby preventing overcharging or over-discharging.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates an equivalent circuit of a TFT liquid crystal display.

Figure 2 illustrates a conventional multi-step source driving circuit of the related art.

Figure 3 a illustrates output voltage waveforms in a conventional multi-step source driving method of the related art.

Figure 3b is a circuit diagram illustrating a polarity modulator in a conventional multi-step source driving method of the related art. Figure 4a illustrates driving waveforms of all-black images in a conventional multi-step source driving method of the related art.

Figure 4b illustrates driving waveforms of all-white images in a conventional multi-step source driving method of the related art. Figure 5 illustrates output voltage forms in the low power source driving method according to a preferred embodiment of the present invention.

Figure 6a illustrates the structure of the source driving circuit of a liquid crystal display according to a preferred embodiment of the present invention.

Figure 6b is a detailed circuit diagram of an operation amplifier (Op- Amp) at the output end of a preferred embodiment of the present invention.

Figure 7 illustrates waveforms of control signals for switches illustrated in Figure 6a.

Figure 8a is a diagram of driving waveforms of all-black images in the low power source driving method according to a preferred embodiment of the present invention.

Figure 8b is a diagram of driving waveforms of all-white images in the low power source driving method according to a preferred embodiment of the present invention.

Figure 9 is a circuit diagram of the polarity modulator of the source driving circuit according to a preferred embodiment of the present invention.

** Descriptions of reference numerals for important parts of the drawings **

610: D/A converter 620: Polarity modulator

630: Output buffer 632: Operation amplifier

634: Input amplifier 640: LCD panel BEST MODE FOR CARRYING OUT THE INVENTION

Reference will now be made in detail to preferred embodiments of the present invention as illustrated in the accompanying drawings. Figure 5 illustrates the output voltage waveforms in the low power source driving method according to a preferred embodiment of the present invention.

In Figure 5, VSS voltage is ON NDD voltage is ION and the common voltage V_COM supplied to the common electrode is 5 1H, 2H,... represents line times. Each line time is composed of a polarity inversion period (i.e., charging/discharging period (A or C)) and a gray-scale display period (B or D). For the purpose of the line inversion, during 1H, the positive is supplied to the pixel electrode and during 2H, the negative is supplied to the pixel electrode. In particular, VCH is the maximum charging level in the positive side as controlled by image signals and VCL is the maximum discharging level in the negative side as controlled by image signals. As shown in Figure 5, at the time of the polarity modulation, the present invention does not charge or discharge up to certain fixed medium voltage levels (VH, VL). Rather, charging and discharging is conducted only up to voltages (VCH, VCL) controlled by image signals. Thus, overcharging is prevented.

Figure 6a illustrates the structure of the low power source driving circuit of a liquid crystal display according to a preferred embodiment of the present invention. Figure 6b is a detailed circuit diagram of an operation amplifier (Op-Amp) of an output buffer illustrated in Figure 6a.

As shown in Figure 6a, the source driving circuit for supplying the driving voltage to an LCD panel 640 comprises a digital-analog converter 610 for outputting image signal voltages of odd number data lines ("odd number lines") and even number data lines ("even number lines"), a polarity modulator 620, an output buffer 630, switches swla, swlb, sw2a and sw2b for controlling charging and discharging. The output buffer 630 is composed of as many Op-Amps 632 as the number of data lines. The Op-Amp 632 is further composed of an input amplifier 634, a PMOS transistor Mp, and an NMOS transistor M_N, as shown in Figure 6b.

When the first switch swla is connected, the output of the charging end VD of the polarity modulator 620 is connected to V_H of even number lines, and the output of the discharging end VS of the polarity modulator 620 is connected to V_L θf odd number lines. Thus, the even number lines are charged and the odd number lines are discharged. When the second switch swlb is connected, the VDD voltage is supplied to V_H of odd number lines and GND is connected to VL of even number lines.

When the third switch sw2a is connected, the output of the charging end VD of the polarity modulator 620 is connected to V_H of odd number lines, and the output of the discharging end VS of the polarity modulator 620 is connected to V_L of even number lines. Thus, the odd number lines are charged and the even number lines are discharged. When the fourth switch sw2b is connected, the VDD voltage is supplied to V_H of even number lines and GND is connected to N_Lθf odd number lines.

As shown in Figure 6b, the input amplifier 634 of an Op-Amp receives the output of the D/A converter 610 at the inverting (-) end and receives feedback signal at the non-inverting (+) end. Then, the input amplifier 634 amplifies the input by the gain Ao and outputs it. The output of the input amplifier 634 is transferred to the gates of the PMOS transistor (M_P) and the ΝMOS transistor (MM), which are serially connected between VH and V and thereafter is outputted as Vo- Now, the charging/discharging actions of the all-white mode are explained with references to Figure 6a and Figure 6b.

1. Charge Action

At the time of charging in Vo load of data lines, the voltage of 6.5 V is supplied to Vi. If voltage lower than the voltage at Vi is supplied to V_H from the polarity modulator 620, the PMOS transistor (Mp) is turned on and thus the charging is conducted step by step. If voltage higher than the voltage at Vi is supplied to V_H, the input amplifier (Input Amp) 634 generates high signals (High) decreasing the gate- source voltage of the PMOS transistor (Mp), causing the cutoff. Therefore, voltage higher than the voltage at Vi is prevented from being charged at Vo and, as a result, overcharging is prevented.

2. Discharge Action

At the time of discharge, if voltage lower than Vr is supplied to V_L of the operation amplifier 632 from the polarity modulator 620, the input amplifier (Input Amp) 634 generates low signals (Low) and thus the gate-source voltage of the NMOS transistor (M_N) decreases and becomes cut-off. Consequently, the discharge to the voltage lower than Vr does not occur.

Figure 7 illustrates waveforms of control signals for turning on/off the switches shown in Figure 6a according to a preferred embodiment of the present invention.

In Figure 7, at the initial stage, it is assumed that even number lines are the negative image state (i.e., the discharging state) and odd number lines are the positive image state (i.e., the charging state). With respect to the waveform conditions, one line time is 22μs (if the frame frequency is 75Hz and if the resolution is 1600X1200 UXGA, one line time is 1/(75X1200) ll.lμs and the one line time is doubled in the event of the divided driving). Figure 7 illustrates the charging/discharging periods of even number lines and odd number lines during two line times. In Figure 7, 'Section

A' is the period for even number line charging and odd number line discharging (polarity modulation) of the first line time and 'Section B' is the period for the grayscale display of the first line time. 'Section C is the period for odd number line charging and even number line discharging (polarity modulation) of the second line time and 'Section D' is the period for the gray-scale display of the second line time.

As shown in Figure 6a and Figure 7, when swla is turned on in Section A, even number lines are charged step-by-step through the polarity modulator 620. At the same time, odd number lines are discharged step-by-step through the polarity modulator 620. In Section B, after the completion of the polarity inversion, if swla and sw2a are turned off and if swlb and sw2b are turned on, VDD and VSS voltage sources are connected to all operation amplifiers of the output buffer 630. Thus, the output of the output buffer 630 is supplied to each data line (column line).

In Section C, when sw2a is turned on, even number lines are discharged step- by-step and odd number lines are charged step-by-step. In Section D, the same switch on/off operation occurs as in Section B (i.e., swla and sw2a are off and swlb and sw2b are on) and the gray scales are displayed.

The foregoing may be expressed with the following table 1. <Table 1>

Figure 8a illustrates the driving waveforms of the all-black image in the low power source driving method according to a preferred embodiment of the present invention and Figure 8b illustrates the driving waveforms of the all-white image in the low power source driving method according to a preferred embodiment of the present invention.

As shown in Figure 8a and Figure 8b, differently from the conventional stepwise charging method of the related art, in the present invention, charging and discharging occurs only up to the desired voltages. Thus, there is no overcharging. If the five step driving is used, regardless of the types of images, approximately 80% of the driving power consumption is saved.

From the comparison of the low power source driving circuit of the present invention (Figure 6a) and the conventional multi-step source driving circuit of the related art (Figure 2), it may be discovered that the MUX switches existing in each and every line between the output end Op- Amp and the LCD panel of the conventional multi-step source driving method of the related art have been eliminated in the present invention because, in the present invention's driving circuit, the switches of the driving circuit's output buffer 630 are classified into even number lines and odd number lines and are controlled collectively at the time of polarity modulation. As a result, additional power consumption required for driving MUX switches is not necessary according to the present invention. Also, the circuit becomes simpler.

Figure 9 is a circuit diagram of the polarity modulator for driving the source driving circuit according to a preferred embodiment of the present invention.

As shown in Figure 9, the polarity modulator 620 comprises seven capacitors Cι~C₇ for stepwise charging, switches SW1-SW7 for connecting the capacitors Cι~C to the discharge end VS, switches SW8-SW14 for connecting the capacitors Cι~C₇ to the charge end VD, and two diodes Di and D .

The diode Di is included so as to prevent the reverse flow of current from the capacitor C₇ to the discharge end VS at the time of the stepwise discharging in the all- white mode (VH: 6.5V). The diode D₂ is included so as to prevent the reverse flow of the current from the charge end VD to the capacitor d at the time of charging in the all-white mode (VL: 3.5V). In summary, the polarity modulator 620 according to a preferred embodiment of the present invention comprises 7 external capacitors, 14 switches and 2 diodes.

The foregoing embodiments of the low power source driving circuit and method are merely exemplary and are not to be construed as limiting the present invention. Many alternatives, modifications and variations will be apparent to those skilled in the art.

INDUSTRIAL APPLICABILITY

As explained above, the source driving circuit of the present invention controls operation amplifiers (Op-Amps) of the buffer collectively with a few switches. Therefore, the switches existing in each and every line of the conventional driving circuit of the related art are no more necessary and thus the circuit structure becomes simple. As a result, the electric power required for driving the switches may be saved. Furthermore, because the charging/discharging occurs only up to the level as controlled by image signals instead of certain fixed voltage levels at the time of the polarity modulation, overcharging or over-discharging is prevented in the present invention. Consequently, unnecessary power consumption is prevented.

WHAT IS CLAIMED IS:

1. A low power source driving circuit method for driving data lines of a liquid crystal display, which charges or discharges only up to certain voltages as controlled by relevant image signals instead of certain fixed voltage levels as medium voltages at the time of charging and discharging for the polarity modulation, and thus prevents the overcharging or over-discharging.

2. A low power multi-step source driving circuit for driving data lines of a TFT liquid crystal display according to relevant image data comprising: a digital-analog converter for converting the image data into analog signals; a polarity modulator for providing multi-step charging and discharging voltages for the polarity modulation; an output buffer for receiving image signals inputted from the digital-analog converter and conducting the polarity modulation through charging and discharging at the polarity modulation period in which the output buffers are connected to the polarity modulator, wherein at the time of charging, if the charging voltage of the polarity modulator is higher than the image signals, the level of image signals becomes the saturation level and at the time of discharging, if the discharging voltage of the polarity modulator is lower than the image signals, the level of image signals becomes the saturation level, and at the gray-scale display period, the polarity modulated outputs are supplied to the relevant data lines; and switching means for connecting the polarity modulator to the output buffers at the polarity modulation period and connecting the output buffers to the power supplier at the gray-scale display period. 3. The low power source driving circuit of a liquid crystal display according to claim 2, wherein the output buffer is composed of as many operation amplifiers as the number of data lines.

4. The low power source driving circuit of a liquid crystal display according to claim 3, wherein the operation amplifier comprises: an input amplifier for receiving the image signals (V_); a PMOS transistor M which, at the time of charging, is turned on and causes the stepwise charging if voltage lower than the image signals (Vi) is supplied from the polarity modulator, or is cut off if voltage higher than the image signals (Vr) is supplied; and an NMOS transistor M_N which, at the time of discharging, is turned on and causes the stepwise discharging if voltage higher than the image signals (Ni) is supplied from the polarity modulator, or is cut off if voltage lower than the image signals (Ni) is supplied.

5. The low power source driving circuit of a liquid crystal display according to claim 3, wherein the switching means, for the inversion of lines which are classified into odd number lines and even number lines, comprises: the first switch swla for controlling the even number line charging / odd number line discharging; the second switch sw2a for controlling the odd number line charging / even number line discharging; the third switch swlb for connecting VDD to odd number lines' operation amplifiers and GND power source to even number lines' operation amplifiers; and the fourth switch sw2b for connecting VDD to even number lines' operation amplifiers and GND power source to odd number lines' operation amplifiers.

6. The low power source driving circuit of a liquid crystal display according to claim 5, wherein: the first switch is on in the even number line charging (odd number line discharging) period of the first line time, off in the gray-scale display period of the first line time, off in the even number line discharging (odd number line charging) period of the second line time, and off in the gray-scale display period of the second line time; the second switch is off in the even number line charging (odd number line discharging) period of the first line time, on in the gray-scale display period of the first line time, off in the even number line discharging (odd number line charging) period of the second line time, and off in the gray-scale display period of the second line time ; the third switch is off in the even number line charging (odd number line discharging) period of the first line time, off in the gray-scale display period of the first line time, on in the even number line discharging (odd number line charging) period of the second line time, and off in the gray-scale display period of the second line time; and the fourth switch is off in the even number line charging (odd number line discharging) period of the first line time, on in the gray-scale display period of the first line time, off in the even number line discharging (odd number line charging) period of the second line time, and on in the gray-scale display period of the second line time . 7. The low power source driving circuit of a liquid crystal display according to claim 2, wherein the polarity modulator comprises N capacitors, N switches for connecting the capacitors to the discharge end, N switches for connecting the capacitors to the charge end, and a diodes Di for preventing the reverse flow of the current from C_N to the discharge end VS at the time of stepwise discharging in the all-white mode, and a diode D₂ for preventing the reverse flow of the current from the charge end VD to Ci at the time of charging in the all-white mode.