TWM654581U - Direct current converter and direct current controller - Google Patents

Abstract

A DC controller includes a compensation circuit and a control circuit. The compensation circuit is coupled to a power output circuit of a DC converter and is configured to receive a ramp signal, a voltage feedback signal and a driving feedback signal to generate a control compensation signal. The voltage feedback signal is generated according to an output voltage of the DC converter, and the driving feedback signal is associated with a phase node voltage in the power output circuit. The control circuit is configured to compare the voltage feedback signal with the control compensation signal to generate a comparison signal. The control circuit is further configured to output a pulse width modulation signal to the power output circuit according to the comparison signal and a clock signal. The pulse width modulation signal has a duty cycle. The control circuit is further configured to set the duty cycle according to the comparison signal, and to reset the duty cycle according to the clock signal.

Description

DC voltage converter and DC voltage controller

The present disclosure relates to power control, and more particularly to a DC voltage converter and a DC voltage controller.

A DC-to-DC converter is an electromechanical device used for power conversion, which is used to convert the voltage of a DC power source. DC converters are widely used and can be used to supply power to low-power devices (such as batteries) or high-power devices (such as industrial machines). Since the power required by the load used by the DC converter may change at any time depending on the operating state, the power supply stability of the DC converter is very important.

The present disclosure relates to a DC voltage controller, which is applied to a DC voltage converter. The DC voltage converter includes a DC voltage controller, a power output circuit and an energy storage circuit. The power output circuit is coupled between the DC voltage controller and the energy storage circuit, and is used to convert an input voltage into an output voltage. The DC voltage controller includes a compensation circuit and a control circuit. The compensation circuit is coupled to the power output circuit, and is used to receive a ramp signal, a voltage feedback signal and a drive feedback signal of the power output circuit to generate a compensation signal. The voltage feedback signal is generated according to the output voltage, and the drive feedback signal is related to the phase node voltage of the phase node in the power output circuit. The control circuit is coupled between the compensation circuit and the power output circuit to compare the voltage feedback signal and the control compensation signal to generate a comparison signal. The control circuit is also used to output a pulse width modulation signal to the driving circuit according to the comparison signal and the clock signal. The pulse width modulation signal has a duty cycle, and the control circuit is also used to set the duty cycle according to the comparison signal and reset the duty cycle according to the clock signal.

The present disclosure also relates to a direct current voltage converter, including a power output circuit, an energy storage circuit, a compensation circuit and a control circuit. The power output circuit includes an upper bridge switch, a lower bridge switch and a drive circuit, which are used to convert an input voltage into an output voltage. The energy storage circuit is coupled to the power output circuit to receive the output voltage. The compensation circuit is coupled to the power output circuit to receive a ramp signal, a voltage feedback signal and a drive feedback signal of the power output circuit to generate a control compensation signal. The voltage feedback signal is generated according to the output voltage, and the drive feedback signal is related to the phase node voltage of the phase node in the power output circuit. The control circuit is coupled between the compensation circuit and the power output circuit to compare the voltage feedback signal and the control compensation signal to generate a comparison signal. The control circuit is also used to output a pulse width modulation signal to the driving circuit according to the comparison signal and the clock signal. The pulse width modulation signal has a duty cycle, and the control circuit is also used to set the duty cycle according to the comparison signal and reset the duty cycle according to the clock signal.

Based on this, by using the "drive feedback signal related to the phase node voltage" as the control compensation signal and generating the control compensation signal in a negative feedback manner, the DC voltage converter will be able to adjust the duty cycle of the pulse width modulation signal according to the load condition to improve the power supply stability. At the same time, the application bandwidth and transient response of the DC voltage converter can also be improved.

The following will disclose multiple implementations of the present invention with diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. In other words, in some implementations of the present invention, these practical details are not necessary. In addition, in order to simplify the diagrams, some commonly used structures and components will be depicted in the diagrams in a simple schematic manner.

In this article, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this article to describe different elements, the terms are only used to distinguish between elements or operations described with the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit this creation.

FIG. 1A is a schematic diagram of a DC voltage converter 100 according to an embodiment of the present disclosure. The DC voltage converter 100 includes a power output circuit 110, a DC voltage controller 200, and an energy storage circuit LC. The power output circuit 110 further includes a driving circuit 111 and a switching circuit 112. The DC voltage controller 200 further includes a compensation circuit 120 and a control circuit 130. The switching circuit 112 is used to receive an input voltage Vin and receive a control signal through the driving circuit 111. In addition, the energy storage circuit LC includes an inductor L1 and a capacitor C1.

The power output circuit 110 is coupled between the DC voltage controller 200 and the energy storage circuit LC, and is used to selectively (e.g., alternately) turn on or off the upper bridge switch T1 and the lower bridge switch T2 according to the control signal to convert the input voltage Vin into the output voltage Vout, and output the output voltage Vout to the energy storage circuit LC. At the same time, the power output circuit 110 also generates a voltage feedback signal Vfb through multiple resistors R1 and R2. In one embodiment, the voltage feedback signal Vfb can be a voltage division of the output voltage Vout.

In one embodiment, there is a phase voltage node (such as the phase node N shown in FIG. 1A) between the upper bridge switch T1 and the lower bridge switch T2, one end of the inductor L1 is coupled to the phase node N, and the other end thereof is used to generate an output voltage Vout through the output capacitor C1. Since the operation of the power output circuit 110 is understandable to those skilled in the art, it will not be further described here. In addition, in one embodiment, the DC voltage converter 100 can be applied as one of the conversion circuits in a multi-phase DC voltage converter to output a single-phase current.

Referring to FIG. 1A , the compensation circuit 120 generates a drive feedback signal Isen according to the lower bridge current IML (i.e., the current flowing through the lower bridge switch T2). The drive feedback signal Isen is related to the phase node voltage Vx of the phase node N. In this embodiment, the drive feedback signal Isen is a drive current signal generated according to the lower bridge current IML (i.e., the current flowing through the lower bridge switch T2) to provide lower bridge current information.

The compensation circuit 120 is used to receive the ramp signal Vramp, the voltage feedback signal Vfb and the drive feedback signal Isen, and generate a control compensation signal Vcomps according to the ramp signal Vramp and the drive feedback signal Isen.

In one embodiment, the compensation circuit 120 includes an error detection circuit 121 and an operation circuit 122. The input end of the error detection circuit 121 is used to receive a voltage reference signal Vref (such as a fixed bias signal) and a voltage feedback signal Vfb to generate an error signal Vcomp. The error signal Vcomp is generated according to the voltage feedback signal Vfb and the voltage reference signal Vref, so that the compensation circuit 120 generates a control compensation signal Vcomps. In one embodiment, the error detection circuit 121 includes a comparator to generate an error signal Vcomp according to the difference between the voltage reference signal Vref and the voltage feedback signal Vfb.

The operation circuit 122 is coupled between the error detection circuit 121 and the control circuit 130 to receive the error signal Vcomp, the ramp signal Vramp and the drive feedback signal Isen respectively. The operation circuit 122 is used to generate the control compensation signal Vcomps according to the error signal Vcomp, the ramp signal Vramp and the drive feedback signal Isen. The ramp signal Vramp can be a sawtooth wave with a fixed slope. "Sawtooth wave" means that in each signal cycle, it will change from a fixed level (such as rising or falling), and when the current signal cycle ends and enters the next signal cycle, it will return to the original fixed level. In some embodiments, the signal slope of the ramp signal Vramp is positive, that is, in the signal cycle, the level of the ramp signal Vramp gradually increases. However, the present disclosure is not limited to this. In other embodiments, the ramp signal Vramp can also be a triangular wave according to the different slopes.

In one embodiment, the driving feedback signal Isen is fed back to the operation circuit 122, and the control compensation signal Vcomps is the error signal Vcomp plus the ramp signal Vramp and minus the driving feedback signal Isen.

The control circuit 130 is coupled between the compensation circuit 120 (operation circuit 122) and the power output circuit 110, and is used to compare the voltage feedback signal Vfb and the control compensation signal Vcomps to generate a comparison signal Va. The control circuit 130 is also used to generate a pulse width modulation signal Vdt according to the comparison signal Va and the clock signal CLK, and output the pulse width modulation signal Vdt to the driving circuit 111. The driving circuit 111 generates a corresponding control signal according to the duty ratio (also called duty cycle) of the pulse width modulation signal Vdt to selectively turn on or off the upper bridge switch T1 and the lower bridge switch T2. The drive feedback signal Isen can be regarded as a half-cycle current signal, and its waveform is a half-cycle signal as shown in Figure 1A. For example, in the positive half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned on and the lower bridge switch T2 is turned off. At this time, the input voltage Vin charges the capacitor C1, and the current flows from the phase node N to the capacitor C1. At this time, the drive feedback signal Isen is zero; in the negative half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned off and the lower bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower bridge switch T2. According to the characteristics of the inductor volt-second balance, when the input voltage Vin no longer charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, the inductor L1 will tend to maintain the original current direction for output to continue to provide the inductor current. At this time, the current of the lower bridge switch T2 (i.e., the lower bridge current IML) will flow from the ground end to the phase node N. The larger the current flowing through the lower bridge switch T2, the larger the drive feedback signal Isen will be.

The control circuit 130 is used to set the duty cycle of the pulse width modulation signal Vdt according to the comparison signal Va (i.e., switch to the enable level), and reset the duty cycle of the pulse width modulation signal Vdt according to the clock signal CLK (i.e., switch to the disable level). In one embodiment, the control circuit 130 uses the "leading-edge" of each pulse of the clock signal CLK as a judgment condition to generate the pulse width modulation signal Vdt. When the comparison signal Va changes (ie, the voltage feedback signal Vfb and the control compensation signal Vcomps intersect), the control circuit 130 sets the pulse width modulation signal Vdt to an enable level; when the clock cycle of the clock signal CLK occurs, the pulse width modulation signal Vdt is reset to a disable level.

In one embodiment, the control circuit 130 includes a signal comparator 131 and a signal register 132. The signal comparator 131 has a first input terminal (e.g., a positive electrode) and a second input terminal (e.g., a negative electrode). The first input terminal is used to receive the control compensation signal Vcomps, and the second input terminal is used to receive the voltage feedback signal Vfb. A comparison signal Va is generated according to the difference between the control compensation signal Vcomps and the voltage feedback signal Vfb. The signal register 132 is coupled between the signal comparator 131 and the power output circuit 110, and its input terminal is used to receive the comparison signal Va, and can output a pulse width modulation signal Vdt according to the clock signal CLK. In one embodiment, the signal register 132 may be an SR flip-flop, and the S terminal is used to receive the comparison signal Va.

The present disclosure utilizes the drive feedback signal Isen associated with the phase node N in the power output circuit 110 as a control compensation signal to generate the control compensation signal Vcomps in a negative feedback manner (i.e., deduction), and accordingly, the DC voltage converter 100/DC voltage controller 200 will be able to adjust the duty cycle of the pulse width modulation signal Vdt in advance according to the load condition, so as to provide electric energy corresponding to the load condition in real time, thereby improving the power supply stability of the DC voltage converter 100. In addition, the use of the drive feedback signal Isen for control compensation can increase the application bandwidth of the DC voltage converter 100 and improve the transient response of the signal.

For example, when the DC voltage converter 100 is under heavy load (i.e., the load at the output terminal requires more power), the duty cycle of the pulse width modulation signal Vdt should be increased accordingly to increase the output current of the DC voltage converter 100. In this regard, the present disclosure utilizes the drive feedback signal Isen associated with the phase node N and provides the drive feedback signal Isen to the input terminal of the signal comparator 131, so as to instantly reflect the current load status of the DC voltage converter 100 to adjust the pulse width modulation signal Vdt, thereby providing better transient response and accuracy of the output.

Please refer to FIG. 1B, which is a schematic diagram of a variation of the DC voltage converter 100 corresponding to FIG. 1A. As shown in FIG. 1B, the DC voltage converter 100' further includes a feedback circuit 140, and the power output circuit 110 generates a driving feedback signal Isen through the feedback circuit 140. The feedback circuit 140 is coupled between the phase node N of the power output circuit 110 and the compensation circuit 120, and is used to generate a driving current signal according to the phase node voltage Vx of the phase node N as the driving feedback signal Isen. The input and output of the feedback circuit 140 can be in the form of voltage-to-current conversion, current-to-current conversion, or current-to-voltage conversion, and can be used in combination with other signals to generate a control compensation signal Vcomps. In FIG. 1B, similar components related to the embodiment of FIG. 1A are represented by the same reference numerals for easy understanding, and the specific principles of similar components have been described in detail in the previous paragraph. If it is not necessary to introduce it because of the coordinated operation relationship with the components of FIG. 1B, it will not be repeated here.

FIG. 1C is a schematic diagram of a feedback circuit 300 and a compensation circuit 120A according to an embodiment of the present disclosure, wherein the feedback circuit 300 may be an example of the feedback circuit 140 in FIG. 1B , and the compensation circuit 120A may be an example of the compensation circuit 120 in FIG. 1B . As shown in FIG. 1C , the compensation circuit 120A includes an error detection circuit 121 and an operation circuit 122, and the error detection circuit 121 provides an error signal Vcomp to the operation circuit 122 through a buffer 121a. The buffer 121a includes an operational amplifier connected in negative feedback, which is used to generate a substantially identical error signal Vcomp according to the error signal Vcomp1 output by the error detection circuit 121, so that the error signal Vcomp1 is not affected by the drive feedback signal Isen, thereby achieving the effect of signal isolation. In addition, the error signal Vcomp generates a current I31 through the resistor 122b, the ramp signal Vramp generates a current I32 through the transconductance amplifier 122c, and the drive feedback signal Isen are added and subtracted in the accumulator 122a to generate a control compensation signal Vcomps, wherein the transconductance amplifier 122c is coupled to the voltage VCC.

In addition, the compensation circuit 120A also obtains the ramp signal Vramp through the signal generating circuit 150. The signal generating circuit 150 includes a current source 151, a capacitor 152 and a switch 153, and is used to generate the ramp signal Vramp according to the clock signal CLK, wherein the current source 151 is coupled to the voltage VCC. Specifically, the signal generating circuit 150 controls the on and off of the switch 153 according to the clock signal CLK to control the time for the current source 151 to charge the capacitor 152.

Specifically, in the positive half cycle, the clock signal CLK turns off the switch 153, at which time the current source 151 charges the capacitor 152, the voltage of the node 154 coupled to the capacitor 152 rises, and the slope of the ramp signal Vramp is positive; in the negative half cycle, the clock signal CLK turns on the switch, at which time the capacitor 152 discharges to the ground, the voltage of the node 154 coupled to the capacitor 152 drops, and the slope of the ramp signal Vramp is negative. Since people in the art can understand the various ways or methods of generating the ramp signal Vramp, they will not be further described here, and the signal generating circuit 150 of the present disclosure is not limited to that shown in FIG. 1C.

In this embodiment, the feedback circuit 300 is a transconductance amplifier circuit and includes a comparison circuit 310 and a current source 320, wherein the current source is coupled to the voltage VCC. The comparison circuit 310 generates a driving voltage signal according to the difference between the phase node voltage Vx and the ground voltage Vg, and the driving voltage signal is equivalent to providing information of the lower bridge current. The current source 320 is coupled to the comparison circuit 310 to generate a driving current signal according to the received driving voltage signal, and the generated driving current signal will be used as the driving feedback signal Isen.

Please refer to Figures 1B and 1C. In one embodiment, the feedback circuit 140/300 is coupled to the phase node N, and processes (e.g., subtracts) the phase node voltage Vx and the ground voltage Vg to simulate the lower bridge current information, so that the generated driving feedback signal Isen has the lower bridge current information. Therefore, the driving feedback signal Isen generated by the feedback circuit 140 is a driving current signal corresponding to the current of the lower bridge switch T2 (i.e., the half-cycle signal of the output current of the DC voltage converter 100'). Similarly, the driving feedback signal Isen can be regarded as a half-cycle current signal, and its waveform is shown in Figures 1B or 1C.

For example, in the positive half cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned on and the lower bridge switch T2 is turned off. At this time, the input voltage Vin charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, the phase node voltage Vx is not zero, and the pulse output by the comparison circuit 310 is sawtooth-shaped.

On the other hand, in the negative half cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned off and the lower bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower bridge switch T2. According to the characteristics of the inductor volt-second balance, when the input voltage Vin no longer charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, the current direction of the inductor L1 will tend to maintain the original current direction to continue to provide the inductor current. At this time, the current direction of the lower bridge switch T2 will flow from the ground end to the phase node N, so the phase node voltage Vx will be negative. As shown in FIG. 1C , the change in the voltage level of the phase node voltage Vx will affect the output of the comparison circuit 310, thereby adjusting the current size of the current source 320. For example, when the current flowing through the lower bridge switch T2 is larger, the phase node voltage Vx is lower than the ground voltage Vg and becomes more negative, so that the voltage level change of the phase node voltage Vx and the ground voltage Vg is larger, so the drive feedback signal Isen generated by the current source 320 is larger. That is, the difference between the "phase node voltage Vx and the ground voltage Vg" detected by the comparison circuit 310 can be used to adjust the size of the drive feedback signal Isen generated by the current source 320.

FIG. 2A is a schematic diagram of a DC voltage converter 400 according to another embodiment of the present disclosure. In FIG. 2A, similar components related to the embodiment of FIG. 1A are represented by the same reference numerals for ease of understanding, and the specific principles of the similar components have been described in detail in the previous paragraphs and will not be repeated here. The difference between the DC voltage converter 400 of FIG. 2A and the DC voltage converter 100 of FIG. 1A is that the compensation circuit 120 generates the drive feedback signal Isen based on the inductor current information (i.e., the current flowing through the inductor L1) instead of the lower bridge current information. Accordingly, the DC voltage converter 400 can adjust the duty cycle of the pulse width modulation signal Vdt in advance according to the load condition to improve the power supply stability of the DC voltage converter 100 and improve the transient response of the signal.

Please refer to FIG. 2B, which is a schematic diagram of a variation of the DC voltage converter 400 corresponding to FIG. 2A. In FIG. 2B, similar components related to the embodiment of FIG. 2A are represented by the same reference numerals for easy understanding, and the specific principles of similar components have been described in detail in the previous paragraphs. Unless they have a cooperative operation relationship with the components of FIG. 2B and are necessary to be introduced, they will not be repeated here. As shown in FIG. 2B, the DC voltage converter 400' further includes a feedback circuit 440, and the power output circuit 110 generates a drive feedback signal Isen through the feedback circuit 440. The feedback circuit 440 is coupled between the power output circuit 110 and the compensation circuit 120, and is used to generate a driving current signal according to the phase node voltage Vx of the phase node N as a driving feedback signal Isen.

As shown in Figures 1A, 1B, 2A and 2B, in the circuit architecture of the present disclosure, the positive end of the signal comparator 131 is used to receive the control compensation signal Vcomps, and the control compensation signal Vcomps is based on the "error signal Vcomp and the ramp signal Vramp", and further introduces the "current information of the power output circuit 110 (such as: lower bridge current, inductor current)" as control compensation. The negative end of the signal comparator 131 receives the voltage feedback signal Vfb. The signal comparator 131 adjusts the duty cycle of the pulse width modulation signal in real time by comparing the signals received at the positive and negative ends. Accordingly, the DC voltage converter will have a faster transient response and improve the control stability. The present disclosure provides a new circuit architecture for the DC voltage converter, which is faster than the fixed frequency control technology or the constant on time technology. When the control compensation signal Vcomps is pulled up quickly and the voltage feedback signal Vfb is dropped, due to the fast transient response, the intersection of the control compensation signal Vcomps and the voltage feedback signal Vfb can be greatly advanced to achieve the effect of generating the working cycle earlier.

In addition, when the output current of the DC voltage converter is too large, the control compensation signal Vcomps will decrease, and the present disclosure can also shorten the working cycle immediately. By properly adjusting the transconductance gain of the lower bridge circuit, it can be ensured that the capacitor C1 in the energy storage circuit LC will not be overcharged, thereby improving the system stability.

FIG. 2C is a schematic diagram of a feedback circuit 440 and a compensation circuit 120B according to another embodiment of the present disclosure. The compensation circuit 120B may be the same as the compensation circuit 120A of FIG. 1C. As shown in FIG. 2C, in this embodiment, the feedback circuit 440 includes a multiplier circuit 401, a filter circuit 402, a comparison circuit 403, and a current source 404, wherein the comparison circuit 403 and the current source 404 may be collectively regarded as a transconductance amplifier circuit, and the current source 404 is coupled to the voltage VCC. The multiplier circuit 401 is coupled to the phase node N of the power output circuit 110 to receive the phase node voltage Vx. In one embodiment, the scale circuit 401 is used to reduce the phase node voltage Vx so as to input the adjusted phase node voltage Vx to the filter circuit 402. In some embodiments, the scale circuit 401 may be omitted.

The filter circuit 402 is coupled to the multiplier circuit 401 to generate multiple filter signals according to the adjusted phase node voltage Vx. As shown in FIG. 2C, in one embodiment, the filter circuit 402 is a second-order filter to generate a first-order filter signal V01 and a second-order filter signal V02 according to the phase node voltage Vx. After filtering, the first-order filter signal V01 includes the DC signal component and the AC signal component in the phase node voltage Vx, and the second-order filter signal V02 only includes the DC signal component of the phase node voltage Vx.

The comparison circuit 403 is coupled to the filter circuit 402 to generate a driving voltage signal according to the filter signal, and the driving voltage signal is used to generate a driving feedback signal Isen. For example, the positive input terminal of the comparison circuit 403 is used to receive the first-order filter signal V01, and the negative input terminal of the comparison circuit 403 is used to receive the second-order filter signal V02, so as to generate the driving voltage signal by comparing the first-order filter signal V01 and the second-order filter signal V02. The comparison circuit 403 subtracts the second-order filter signal V02 from the first-order filter signal V01 to output the full-cycle current information of the inductor current. The full-cycle current information includes the current information corresponding to the upper bridge switch T1 in the positive half cycle and the current information corresponding to the lower bridge switch T2 in the negative half cycle.

The current source 404 is coupled to the comparison circuit 403 and the compensation circuit 120B to generate a driving current signal according to the received driving voltage signal, and the generated driving current signal will be used as the driving feedback signal Isen. The driving feedback signal Isen will be similar to the AC signal of the current of the inductor L1 (e.g., the slope of the signal is similar or the same).

For example, in the positive half cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned on and the lower bridge switch T2 is turned off. At this time, the input voltage Vin charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, the phase node voltage Vx is not zero, and the pulse output by the comparison circuit 403 is sawtooth-shaped.

On the other hand, in the negative half cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned off and the lower bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower bridge switch T2. As mentioned above, the current direction of the lower bridge switch T2 will flow from the ground end to the phase node N, so the phase node voltage Vx will be negative. As shown in Figure 2C, the voltage level change of the phase node voltage Vx will change the output of the comparison circuit 403, thereby adjusting the driving current signal output by the current source 404.

As in the above-mentioned embodiment, the DC voltage converter 100/100'/400/400' and the DC voltage controller 200 are based on the error signal Vcomp between the voltage reference signal Vref and the voltage feedback signal Vfb, with the ramp signal Vramp (e.g., full-cycle sawtooth wave), and the negative feedback drive feedback signal Isen to generate the control compensation signal Vcomps (e.g., full-cycle signal or half-cycle signal of the output current of the DC voltage converter). Accordingly, the bandwidth and transient response of the DC voltage converter 100 will be improved, and the output capacitor C1 will not be overcharged, achieving the advantages of stable power supply, fixed frequency control, and fast response.

Please refer to FIG. 1A and FIG. 3A together. FIG. 3A is a schematic diagram showing the transient response of the signal of the DC voltage converter 100 when the load is ramped in some embodiments of the present disclosure, and from top to bottom are the waveform of the current IL (the current flowing through the inductor L1), the waveform of the control compensation signal Vcomps/the error signal Vcomp/the voltage feedback signal Vfb, the waveform of the pulse width modulation signal Vdt, and the waveform of the lower bridge current IML (i.e., the detected current flowing through the lower bridge switch T2).

When the load condition of the DC voltage converter 100 gradually changes from light load to heavy load, as the current IL (inductor current) increases, the error signal Vcomp and the control compensation signal Vcomps will gradually increase. Whenever the control compensation signal Vcomps is greater than the voltage feedback signal Vfb (indicating that the load is insufficient and the upper bridge switch T1 needs to be turned on longer), the pulse width modulation signal Vdt will respond immediately and output a high level, providing an instant transient response. If the transient response is realized only by comparing the error signal Vcomp with the voltage feedback signal Vfb, it can be seen from FIG. 3A that the error signal Vcomp exceeds the voltage feedback signal Vfb at time point P1, that is, the pulse width modulation signal Vdt outputs a high level at time point P1, thus having a relatively poor transient response.

Please refer to FIG. 1A and FIG. 3B together. FIG. 3B is a schematic diagram showing the transient response of the signal of the DC voltage converter 100 when the load rapidly increases to a heavy load in some embodiments of the present disclosure, and from top to bottom are the waveform of the current IL (the current flowing through the inductor L1), the waveform of the control compensation signal Vcomps/the error signal Vcomp/the voltage feedback signal Vfb, the waveform of the pulse width modulation signal Vdt, and the waveform of the lower bridge current IML (i.e., the detected current flowing through the lower bridge switch T2).

When the load condition of the DC voltage converter 100 changes rapidly from light load to heavy load, as the current IL (inductor current) increases, the error signal Vcomp and the control compensation signal Vcomps will gradually increase. Whenever the control compensation signal Vcomps is greater than the voltage feedback signal Vfb (indicating that the load is insufficient and the upper bridge switch T1 needs to be turned on for a longer time), the pulse width modulation signal Vdt will respond immediately and output a high level, providing an instant transient response. In addition, by quickly pulling down the control compensation signal Vcomps in each cycle, the minimum off time (minumum off time) of the upper bridge switch T1 can be achieved when the circuit is overloaded (e.g., from time point P2 to time point P3). In addition, when the circuit turns to light load at time point P3, the control compensation signal Vcomps will be quickly pulled down to less than the voltage feedback signal Vfb, so that the pulse width modulation signal Vdt will immediately present a low level. According to the above comparison, compared with the method of relying only on the error signal Vcomp and the voltage feedback signal Vfb for control compensation, the solution disclosed in the present disclosure obviously has better transient response.

Please refer to FIG. 1A and FIG. 3C together. FIG. 3C is a schematic diagram showing the transient response of the signal fast unloading of the DC voltage converter 100 in some embodiments of the present disclosure, and from top to bottom are the waveform of the current IL (the current flowing through the inductor L1), the waveform of the control compensation signal Vcomps/the error signal Vcomp/the voltage feedback signal Vfb, the waveform of the pulse width modulation signal Vdt, and the waveform of the lower bridge current IML (i.e., the detected current flowing through the lower bridge switch T2). During the process of rapid unloading of the load condition of the DC voltage converter 100, the solution of the present disclosure can pull the control compensation signal Vcomps down to below the voltage feedback signal Vfb at time point P4, and the pulse width modulation signal Vdt will immediately respond and output a low level, providing an instant transient response. If only relying on the comparison between the error signal Vcomp and the voltage feedback signal Vfb, the pulse width modulation signal Vdt must wait until time point P5 to output a low level. From the above, it can be seen that the technical solution of the present disclosure obviously has a better transient response.

The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other and are not limited to the order of textual description or the order of diagram presentation in this disclosure.

Although the contents of this disclosure have been disclosed as above in the form of implementation, it is not intended to limit the contents of this disclosure. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the contents of this disclosure. Therefore, the protection scope of the contents of this disclosure shall be subject to the scope defined by the attached patent application.

100: DC voltage converter 100’: DC voltage converter 110: Power output circuit 111: Driving circuit 112: Switching circuit 120: Compensation circuit 120A: Compensation circuit 120B: Compensation circuit 121: Error detection circuit 121a: Buffer 122: Operation circuit 122a: Accumulator 122b: Resistor 122c: Transconductance amplifier 130: Control circuit 131: Signal comparator 132: Signal register 140: Feedback circuit 150: Signal generation circuit 151: Current source 152: Capacitor 153: switch 154: node 200: DC voltage controller 300: feedback circuit 310: comparison circuit 320: current source 400: DC voltage converter 400’: DC voltage converter 440: feedback circuit 401: multiplier circuit 402: filter circuit 403: comparison circuit 404: current source C1: capacitor CLK: clock signal I31: current I32: current Isen: drive feedback signal IL: current IML: lower bridge current LC: energy storage circuit L1: inductor N: phase node P1-P5: time point R1: resistor R2: resistor T1: upper bridge switch T2: lower bridge switch V01: first-order filter signal V02: second-order filter signal Va: comparison signal VCC: voltage Vcomp: error signal Vcomp1: error signal Vcomps: control compensation signal Vdt: pulse width modulation signal Vfb: voltage feedback signal Vg: ground voltage Vin: input voltage Vn: reference voltage Vout: output voltage Vramp: ramp signal Vref: voltage reference signal Vx: phase node voltage

FIG. 1A is a schematic diagram of a DC voltage converter according to one embodiment of the present disclosure. FIG. 1B is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure. FIG. 1C is a schematic diagram of a feedback circuit and a compensation circuit according to one embodiment of the present disclosure. FIG. 2A is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure. FIG. 2B is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure. FIG. 2C is a schematic diagram of a feedback circuit and a compensation circuit according to another embodiment of the present disclosure. FIG. 3A to FIG. 3C are signal change diagrams of a DC voltage converter in different states according to some embodiments of the present disclosure.

100: DC voltage converter

110: Power output circuit

111:Drive circuit

112: Switching circuit

120: Compensation circuit

121: Error detection circuit

122: Operational circuit

130: Control circuit

131:Signal comparator

132:Signal register

200: DC voltage controller

C1: Capacitor

CLK: clock signal

Isen: Drive feedback signal

IML: Lower bridge current

LC: Energy storage circuit

L1: Inductor

N: Phase node

R1: resistor

R2: resistor

T1: bridge switch

T2: Down bridge switch

Va: Comparison signal

Vcomp: Error signal

Vcomps: control compensation signal

Vdt: Pulse Width Modulation Signal

Vfb: voltage feedback signal

Vin: Input voltage

Vout: output voltage

Vramp: Ramp signal

Vref: voltage reference signal

Vx: Phase node voltage

Claims (10)

A DC voltage controller is applied to a DC voltage converter. The DC voltage converter includes the DC voltage controller, a power output circuit and an energy storage circuit. The power output circuit is coupled between the DC voltage controller and the energy storage circuit and is used to convert an input voltage into an output voltage. The DC voltage controller includes: a compensation circuit coupled to the power output circuit and used to receive a ramp signal, a voltage feedback signal and a drive feedback signal of the power output circuit to generate a control compensation signal, wherein the voltage feedback signal is based on the output voltage. The drive feedback signal is related to a phase node voltage of a phase node in the power output circuit; and a control circuit is coupled between the compensation circuit and the power output circuit to compare the voltage feedback signal and the control compensation signal to generate a comparison signal, wherein the control circuit is also used to output a pulse width modulation signal to the power output circuit according to the comparison signal and a clock signal; wherein the pulse width modulation signal has a duty cycle, and the control circuit is also used to set the duty cycle according to the comparison signal, and reset the duty cycle according to the clock signal. A DC voltage controller as described in claim 1, wherein the compensation circuit further generates the control compensation signal based on an error signal, and the error signal is generated based on the voltage feedback signal. A DC voltage controller as described in claim 2, wherein the compensation circuit comprises: an error detection circuit for generating the error signal according to the voltage feedback signal and a voltage reference signal; and an operation circuit coupled to the error detection circuit for generating the control compensation signal according to the error signal, the ramp signal and the drive feedback signal. A DC voltage controller as described in claim 1, wherein the power output circuit includes a driving circuit, an upper bridge switch and a lower bridge switch, the energy storage circuit includes an inductor, the upper bridge switch and the lower bridge switch are coupled to the control circuit, the phase node is coupled between the upper bridge switch and the lower bridge switch, one end of the inductor is coupled to the phase node, and the power output circuit is used to alternately turn on the upper bridge switch and the lower bridge switch to output the output voltage at the other end of the inductor. The DC voltage controller as described in claim 4 further includes: a feedback circuit coupled between the phase node of the power output circuit and the compensation circuit, for generating a driving current signal according to the phase node voltage as the driving feedback signal. A DC voltage controller as described in claim 5, wherein the feedback circuit comprises: a comparison circuit, generating a driving voltage signal according to the phase node voltage and a ground voltage; and a current source, coupled to the comparison circuit, for generating the driving current signal according to the driving voltage signal. A DC voltage controller as described in claim 5, wherein the feedback circuit comprises: a filter circuit for generating a plurality of filter signals according to the phase node voltage; and a comparison circuit coupled to the filter circuit for generating a drive voltage signal according to the filter signals, wherein the drive voltage signal is used to generate the drive feedback signal. A DC voltage controller as described in claim 7, wherein the filter circuit is a second-order filter for generating a first-order filter signal and a second-order filter signal according to the phase node voltage, and the comparison circuit is used to compare the first-order filter signal and the second-order filter signal to generate the driving voltage signal. A DC voltage controller as described in claim 1, wherein the control circuit comprises: a signal comparator having a first input terminal and a second input terminal, wherein the first input terminal is used to receive the control compensation signal, and the second input terminal is used to receive the voltage feedback signal to generate the comparison signal; and a signal register coupled to the signal comparator and the power output circuit to receive the comparison signal to output the pulse width modulation signal. A DC voltage converter includes: a power output circuit including an upper bridge switch, a lower bridge switch and a driving circuit for converting an input voltage into an output voltage; an energy storage circuit coupled to the power output circuit for receiving the output voltage; a compensation circuit coupled to the power output circuit for receiving a ramp signal, a voltage feedback signal and a driving feedback signal of the power output circuit to generate a control compensation signal, wherein the voltage feedback signal is generated according to the output voltage, and the driving feedback signal is related to the output voltage. A phase node voltage of a phase node in the power output circuit; and a control circuit coupled between the compensation circuit and the power output circuit for comparing the voltage feedback signal and the control compensation signal to generate a comparison signal, wherein the control circuit is also used to output a pulse width modulation signal to the power output circuit according to the comparison signal and a clock signal; wherein the pulse width modulation signal has a duty cycle, and the control circuit is also used to set the duty cycle according to the comparison signal, and reset the duty cycle according to the clock signal.

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