TWI896602B - Substrate processing method and substrate processing device - Google Patents

Abstract

An object of the invention is to remove a peripheral section of a substrate along a reformed layer formed inside the substrate, thereby appropriately reducing the thickness of the substrate.

A substrate processing method for processing a substrate includes a step of irradiating laser light from the rear of the substrate to form a plurality of first peripheral reformed layers along the boundary between a peripheral section to be removed from the substrate and a center section of the substrate, wherein the plurality of first peripheral reformed layers are each formed at different heights so that with increasing distance in the radial direction from the outside to the inside of the substrate, the first peripheral reformed layers are formed closer to the rear surface side inside the substrate and further from the front surface side.

Description

Substrate processing method and substrate processing device

The present invention relates to a substrate processing method and a substrate processing apparatus.

Patent Document 1 discloses a processing apparatus for a laminated substrate formed by bonding a first substrate to a second substrate. Formed within the first substrate are: a peripheral modified layer extending in the thickness direction along the boundary between the peripheral portion to be removed and the central portion; and an internal surface modified layer extending along the surface of the first substrate from the central portion toward the peripheral portion. The processing apparatus described in Patent Document 1 can remove the peripheral portion of the first substrate and separate the back side of the first substrate (thinning the first substrate) along the peripheral modified layer and the internal surface modified layer formed within the first substrate.

[Prior Art Literature] [Patent Literature]

[Patent Document 1] International Publication No. 2020/017599

According to the technology of the present invention, the peripheral portion of the substrate can be removed and the substrate can be thinned appropriately along the modified layer formed inside the substrate.

One aspect of the present invention is a substrate processing method for processing a substrate, comprising the steps of: irradiating the substrate with laser light from the back side thereof to form a plurality of first peripheral modified layers along the boundary between the peripheral portion of the substrate to be removed and the central portion of the substrate; the plurality of first peripheral modified layers are formed at different heights from the outer side to the inner side of the substrate and from the surface side to the back side within the substrate.

According to the present invention, the peripheral portion of the substrate can be removed and the substrate can be thinned appropriately along the modified layer formed inside the substrate.

1: Wafer processing system

2: Moving in and out of the station

3: Processing Station

10: Wafer cassette loading platform

20: Wafer transport device

21: Transportation Road

22: Transport arm

30: Transfer device

40: Etching device

41: Cleaning device

50: Wafer transport device

51: Transport arm

60: Interface modification device

61: Internal Modification Device

70: Wafer transport device

71: Transport Arm

71a: Adsorption surface

72: Arm component

80: Processing equipment

81: Rotating Table

82: Rotation centerline

83: Clips

84: Grinding unit

85: Grinding Department

86: Pillar

90: Control device

A0: Transmitting position

A1: Processing location

Ac: junction area

Ad:Border

Ae: Unjoined area

B1: First processing block

B2: Second processing block

B3: The third processing block

C1~C4: Fissure

Ct: Wafer Cassette

C′: Turtle crack

D: Component layer

Fs, Fw: surface film

G: Final finishing thickness height

H: Recording media

K: Corner

M1: (first) peripheral modified layer

M1(1): The outermost peripheral modified layer

M2: Internal surface modification layer

M3: Second peripheral modified layer

M4: Split modified layer

M′: Peripheral modified layer

P1~P7: Steps

R: Chamfered area

S: Second wafer

Sa: Surface

Sb: Back

T: stacked wafers

W: First wafer

Wa: surface

Wb: Back

Wc: Central

Wd1: Component wafer

Wd2: Separated wafers

We: Peripheral Department

W′: wafer

W′b: Back

W′e: Periphery

Figure 1 is an explanatory diagram showing the issues involved in the separation of the first wafer.

Figure 2 is a side view showing an example of the stacked wafer configuration.

FIG3 is a top view schematically showing the configuration of a wafer processing system according to an embodiment of the present invention.

Figures 4(a) to 4(f) illustrate an example of the main steps in the semiconductor wafer manufacturing process.

Figure 5 is a flow chart showing an example of the main steps in the semiconductor wafer manufacturing process.

Figure 6 is an explanatory diagram showing an example of forming a modified layer inside the first wafer.

Figure 7 is a top view showing an example of forming a modified layer on the first wafer.

FIG8 is an explanatory diagram showing another example of forming a modified layer inside the first wafer.

FIG9 is an explanatory diagram showing another example of forming a modified layer inside the first wafer.

Figure 10 is an enlarged view showing an example of the stacked wafer configuration.

Figures 11(a) and (b) are explanatory diagrams showing another example of separation of the first wafer.

Figure 12 is a top view showing another example of forming a modified layer on the first wafer.

FIG13 is an explanatory diagram showing another example of forming a modified layer inside the first wafer.

FIG14 is an explanatory diagram showing another example of forming a modified layer inside the first wafer.

In recent years, the semiconductor device manufacturing process involves thinning a semiconductor substrate (hereinafter referred to as a "wafer"), which has multiple electronic circuits and other components formed on its surface, by removing the periphery of the wafer (so-called edge trimming) and separating the wafer into a device wafer on the front side and a separation wafer on the back side.

Wafer edge trimming and thinning are performed using, for example, the substrate processing apparatus disclosed in Patent Document 1. Specifically, laser light is irradiated into the interior of the wafer to form a peripheral modified layer, which serves as a base for peripheral removal, and an internal surface modified layer, which serves as a base for wafer separation. The peripheral portion is removed using the peripheral modified layer as a base, and the wafer is separated (thinned) using the internal surface modified layer as a base.

Furthermore, Patent Document 1 discloses that by forming a peripheral modified layer and an internal surface modified layer at the same height within the wafer, the peripheral removal of the wafer and the separation of the back side can be performed simultaneously. According to Patent Document 1, the separated wafer can be recovered after removal. Furthermore, since the diameter of the recovered separated wafer is the same as that of the wafer before separation, the separated wafer can be reused as, for example, a support wafer.

However, when the wafer's peripheral portion is removed integrally with the separation wafer in this manner, as shown in Figure 1, during the formation of the peripheral modified layer M', which serves as the base for the removal of the peripheral portion W'e, there is a risk that a tortoise crack C' extending from the peripheral modified layer M' may extend to the back surface W'b of the wafer W'. If such a tortoise crack C' reaches the back surface W'b, the peripheral portion W'e may be removed from the separation wafer using the tortoise crack C' as the base, making it impossible to properly recover the removed peripheral portion W'e, or the separation wafer may not be recovered in the desired shape, rendering it unusable.

The technology of the present invention, developed in light of the above circumstances, allows for the appropriate removal of the substrate's periphery and thinning along a modified layer formed within the substrate. The following describes a substrate processing apparatus and method according to embodiments of the present invention with reference to the drawings. Throughout this specification and drawings, elements with substantially identical functional components are designated with identical reference numerals to avoid redundant description.

As shown in Figure 2, a wafer processing system 1 serving as a substrate processing apparatus according to an embodiment of the present invention processes a stacked wafer T, which is a stacked substrate formed by bonding a first wafer W serving as a substrate to a second wafer S serving as another substrate. Furthermore, in the wafer processing system 1, the peripheral portion We of the first wafer W is removed and thinned. Hereinafter, the surface of the first wafer W that is bonded to the second wafer S is referred to as the front surface Wa, and the surface opposite to the front surface Wa is referred to as the back surface Wb. Similarly, the surface of the second wafer S that is bonded to the first wafer W is referred to as the front surface Sa, and the surface opposite to the front surface Sa is referred to as the back surface Sb. Furthermore, the radially inner side of the peripheral portion We of the first wafer W that is to be removed is referred to as the center portion Wc.

The first wafer W is, for example, a semiconductor wafer such as a silicon substrate, and an element layer D including a plurality of elements is formed on the surface Wa. A surface film Fw is further formed in the element layer D to be bonded to the surface film Fs of the second wafer S via the surface film Fw. Regarding the surface film Fw, for example, an oxide film ( _SiO2 film, TEOS film), a SiC film, a SiCN film or an adhesive can be listed. In addition, the peripheral portion We of the first wafer W is chamfered, and the cross-section of the peripheral portion We is thinner toward its front end. In addition, the peripheral portion We is the portion that is removed when the first wafer W is separated later, for example, a range of 0.5mm to 3mm in diameter from the outer end of the first wafer W.

The second wafer S is, for example, a wafer that supports the first wafer W. A surface film Fs is formed on the surface Sa of the second wafer S, and the peripheral portion is chamfered. Regarding the surface film Fs, for example, an oxide film ( _SiO2 film, TEOS film), a SiC film, a SiCN film, or an adhesive, etc. can be listed. In addition, the second wafer S functions as a protective material (support wafer) for protecting the device layer D of the first wafer W. In addition, the second wafer S does not necessarily have to be a supporting wafer, but can also be a device wafer with a device layer formed in the same manner as the first wafer W. In this case, a surface film Fs is formed on the surface Sa of the second wafer S through the device layer.

In the following description, the surface Wa side of the first wafer W after separation is referred to as the device wafer Wd1, and the backside Wb side of the first wafer W after separation is referred to as the separation wafer Wd2. The device wafer Wd1 refers to the first wafer W in a state bonded to the second wafer S, and is sometimes referred to as the device wafer Wd1 together with the second wafer S. Furthermore, the surfaces of the device wafer Wd1 and separation wafer Wd2 after separation are sometimes referred to as the separation surfaces, respectively.

As shown in Figure 3, the wafer processing system 1 comprises an integrally connected loading and unloading station 2 and a processing station 3. The loading and unloading station 2 loads and unloads wafer cassettes Ct, which can accommodate multiple stacked wafers T, device wafers Wd1, and separation wafers Wd2, to and from the outside. The processing station 3 is equipped with various processing devices to perform the desired processing on the stacked wafers T.

A wafer cassette loading station 10 is provided at the loading/unloading station 2. In the illustrated example, a plurality of wafer cassettes Ct, for example three, can be freely loaded on the wafer cassette loading station 10 in a row in the Y-axis direction. The number of wafer cassettes Ct loaded on the wafer cassette loading station 10 is not limited to the embodiments of the present invention and can be arbitrarily determined.

In the loading/unloading station 2, a wafer transport device 20 is installed adjacent to the wafer cassette stage 10 on the negative X-axis side of the wafer cassette stage 10. The wafer transport device 20 is movable along a transport path 21 extending in the Y-axis direction. Furthermore, the wafer transport device 20 holds and transports stacked wafers T and includes, for example, two transport arms 22, 22. Each transport arm 22 is movable horizontally, vertically, about a horizontal axis, and about a vertical axis. Furthermore, the configuration of the transport arms 22 is not limited to the embodiments of the present invention and may have any configuration. Furthermore, the wafer transport device 20 can transport stacked wafers T to the wafer cassette Ct on the wafer cassette stage 10 and the transfer device 30 described later.

In the loading and unloading station 2, the transfer device 30 for transferring stacked wafers T is installed adjacent to the wafer transport device 20 on the negative X-axis side of the wafer transport device 20.

Processing station 3 is equipped with three processing blocks, B1 to B3, for example. The first processing block B1, the second processing block B2, and the third processing block B3 are arranged in this order from the positive side of the X-axis (the side of the loading and unloading station 2) to the negative side.

The first processing block B1 is equipped with an etching apparatus 40 for etching the polished surface of the first wafer W after polishing by the processing apparatus 80 described later; a cleaning apparatus 41 for cleaning the polished surface of the first wafer W; and a wafer transport apparatus 50. The etching apparatus 40 and the cleaning apparatus 41 are stacked. The number and arrangement of the etching apparatus 40 and the cleaning apparatus 41 are not limited to this.

The wafer transport device 50 is, for example, positioned on the negative Y-axis side of the etching apparatus 40 and the cleaning apparatus 41. The wafer transport device 50 holds and transports stacked wafers T and includes, for example, two transport arms 51, 51. Each transport arm 51 is movable horizontally, vertically, around a horizontal axis, and around a vertical axis. The configuration of the transport arms 51 is not limited to the embodiments of the present invention and may have any configuration. Furthermore, the wafer transport device 50 can transport stacked wafers T to the transfer apparatus 30, the etching apparatus 40, the cleaning apparatus 41, the interface modification apparatus 60 (described later), and the internal modification apparatus 61 (described later).

The second processing block B2 is equipped with an interface modification device 60 serving as a second modification unit, an internal modification device 61 serving as a modification unit, and a wafer transport device 70. The interface modification device 60 and the internal modification device 61 are stacked. The number and arrangement of the interface modification devices 60 and the internal modification device 61 are not limited to this.

The interface modification device 60, serving as the second modification section, irradiates the outer periphery of the device layer D of the first wafer W with laser light (interface laser light, such as a _CO2 laser), thereby modifying the interface between the first wafer W and the device layer D in the peripheral portion We of the first wafer W, which is the target for removal. This creates an unbonded region Ae in the peripheral portion We of the first wafer W, where the bonding strength between the first wafer W and the second wafer S is reduced.

The internal modification device 61, which serves as the modification portion, irradiates the interior of the first wafer W with laser light (internal laser light, such as a YAG laser) to form a peripheral modification layer M1 and an internal surface modification layer M2. The peripheral modification layer M1 serves as the starting point for removing the peripheral portion We. The internal surface modification layer M2 serves as the starting point for separating the first wafer W into the device wafer Wd1 and the separation wafer Wd2.

The wafer transport device 70 is, for example, arranged on the positive Y-axis side of the interface modification device 60 and the internal modification device 61. The wafer transport device 70 adsorbs, holds and transports the stacked wafers T by means of an adsorption holding surface not shown in the figure, and has, for example, two transport arms 71, 71. Each transport arm 71 is supported by a multi-jointed arm component 72 and can move freely in the horizontal direction, in the lead vertical direction, around the horizontal axis and around the lead vertical axis. In addition, the structure of the transport arm 71 is not limited to the embodiment of the present invention and can adopt any structure. In addition, the wafer transport device 70 can transport the stacked wafers T to the etching device 40, the cleaning device 41, the interface modification device 60, the internal modification device 61, and the processing device 80 described later.

The third processing block B3 is equipped with a processing device 80.

The processing device 80 includes a rotating table 81. The rotating table 81 is rotatable about a lead-lined rotational centerline 82 by a rotating mechanism (not shown). Two chucks 83 are mounted on the rotating table 81 to hold stacked wafers T by suction. The chucks 83 are evenly spaced along the same circumference as the rotating table 81. The two chucks 83 can be moved to a transfer position A0 and a processing position A1 by rotating the rotating table 81. Furthermore, the two chucks 83 can each be rotated about a lead-lined axis by a rotating mechanism (not shown).

At transfer position A0, stacked wafers T are transferred. At processing position A1, a grinding unit 84 is located to grind the first wafer W. The grinding unit 84 includes a grinding section 85 equipped with a rotatable annular grinding stone (not shown). Furthermore, the grinding section 85 is movable in the vertical direction along a support 86.

The wafer processing system 1 described above includes a control device 90 serving as a control unit. The control device 90 is, for example, a computer equipped with a CPU and memory, and includes a program storage unit (not shown). The program storage unit stores a program for controlling the processing of stacked wafers T in the wafer processing system 1. The program can be recorded on a computer-readable recording medium H and installed from the recording medium H into the control device 90.

Next, wafer processing, which is a substrate processing method performed using the wafer processing system 1, will be described. In this embodiment of the present invention, the stacked wafer T is pre-formed in a bonding device (not shown) outside the wafer processing system 1. In the following description, the thickness direction of the first wafer W is sometimes referred to as the "upper and lower directions," with the back surface Wb of the first wafer W being designated "upper" and the front surface Wa being designated "lower."

First, a wafer cassette Ct containing multiple stacked wafers T, as shown in Figure 4(a), is placed on the wafer cassette loading platform 10 of the loading/unloading station 2. The stacked wafers T are then removed from the cassette Ct by the wafer transport device 20 and transported to the transfer device 30. After being transported to the transfer device 30, the stacked wafers T are then transferred to the interface modification device 60 by the wafer transport device 50. As shown in Figure 4(b), the interface modification device 60 irradiates the interface between the first wafer W and the device layer D with laser light to modify the interface (step P1 in Figure 5).

After modifying the interface between the first wafer W and the device layer D in step P1, the bond strength between the first wafer W and the second wafer S is reduced. This creates a "bonding region Ac" between the first wafer W and the device layer D, and an "unbonded region Ae" radially outward of the bonding region Ac where the bonding strength is reduced.

Furthermore, "modification" of the interface during the formation of the unbonded region Ae refers to a process that reduces or eliminates the bonding strength between the first wafer W and the second wafer S. This includes, for example, peeling, removal, or amorphization of the interface achieved by irradiation with laser light.

The stacked wafer T, with the unbonded area Ae formed therein, is then transported to the internal modification device 61 by the wafer transport device 50. As shown in Figures 4(c) and 4(d), the internal modification device 61 sequentially forms a peripheral modified layer M1 and an internal surface modified layer M2 within the first wafer W (steps P2 and P3 in Figure 5).

To form the peripheral modified layer M1, the stacked wafer T (first wafer W) is rotated while laser light is periodically irradiated from a laser head (not shown). The laser light irradiation position is simultaneously shifted radially inward of the first wafer W and toward the back surface Wb of the first wafer W. In other words, as shown in Figure 6 , the multiple peripheral modified layers M1 formed within the first wafer W are formed at different heights, with the formation positions increasing as they move radially inward of the first wafer W when viewed in cross-section. Furthermore, as shown in Figure 7 , the peripheral modified layer M1 is formed in a ring shape concentric with the bonded area Ac (unbonded area Ae). The number of peripheral modified layers M1 formed on the first wafer W is not limited to the example shown and can be arbitrarily determined.

Furthermore, within the first wafer W, a crack C1 (turtle crack) extends along the direction of formation of the peripheral modified layer M1, that is, from the radially outward side of the first wafer W to the inward side, and from the front surface Wa to the back surface Wb of the first wafer W. As shown in Figure 6, the lower end of the crack C1 reaches the front surface Wa of the first wafer W, but the upper end does not reach the back surface Wb. In other words, because the extension length of the crack C1 is determined by the formation interval of the peripheral modified layer M1 and the output of the laser light, the formation of the peripheral modified layer M1 is controlled in this manner so that the crack C1 reaches the front surface Wa but does not reach the back surface Wb.

When the first wafer W is subsequently separated, the peripheral portion We is removed from the device wafer Wd1 using this peripheral modified layer M1 and the crack C1 as a starting point. To properly remove this peripheral portion We, for example, it is desirable to form the peripheral modified layers M1 separately with a formation spacing that connects the cracks C1 extending from adjacent peripheral modified layers M1. Alternatively, the formation spacing can be controlled so that adjacent peripheral modified layers M1 partially overlap.

Here, the crack C1 extending into the interior of the first wafer W generally tends to extend along the crystal orientation of the first wafer W. Furthermore, from a molding or processing perspective, the crystal orientation of the first wafer W often extends in the face and thickness directions of the first wafer W. Therefore, when the peripheral modified layer M' is arranged in the thickness direction as shown in Figure 1, the crack C1 is more likely to extend in the thickness direction, that is, more likely to reach the back surface Wb.

In this regard, in embodiments of the present invention, adjacent peripheral modified layers M1 are offset in the thickness and radial directions, in other words, arranged diagonally. This suppresses the extension of cracks C1 and their arrival at the back surface Wb, compared to conventional methods in which peripheral modified layers M' are arranged in the thickness direction. Furthermore, in embodiments of the present invention, since the formation intervals of the peripheral modified layers M1 are controlled to allow cracks C1 to connect to each other or to allow portions of the peripheral modified layers M1 to overlap, cracks C1 can be more effectively prevented from reaching the back surface Wb.

Here, as shown in FIG6 , the formation position of the most radially outward peripheral modified layer M1 (1) formed in the interior of the first wafer W is set slightly radially inward from the inner peripheral end of the unbonded region Ae formed by the interface modification device 60, that is, the boundary Ad between the bonded region Ac and the unbonded region Ae. The boundary Ad is, for example, the result of the formation of the unbonded region Ae in the interface modification device 60, or is detected using an IR camera or the like in an alignment device (not shown) provided at an arbitrary position in the wafer processing system 1.

The peripheral modified layer M1 is ideally formed so that it overlaps with the boundary Ad. However, it can sometimes be radially offset due to processing errors. Furthermore, if the peripheral modified layer M1 is formed radially outward from the boundary Ad, that is, in the unbonded area Ae, the first wafer W may float relative to the second wafer S after the peripheral portion We is removed. By controlling the peripheral modified layer M1 so that it is formed radially inward from the boundary Ad, even if the formation position shifts due to processing errors, the peripheral modified layer M1 can be formed overlapping the boundary Ad, or even closer to the boundary Ad even if it is radially outward from the boundary Ad, thereby preventing the first wafer W from floating.

After forming the peripheral modified layer M1, the laser head (not shown) is moved to form an inner surface modified layer M2 extending radially inward from the peripheral modified layer M1 in the planar direction of the first wafer W. To form the inner surface modified layer M2, the stacked wafer T (first wafer W) is rotated while the laser head periodically irradiates the layer with laser light, moving the laser light irradiation position radially inward of the first wafer W. This results in the inner surface modified layer M2 being formed completely within the first wafer W along the planar direction. The radial formation interval of the inner surface modified layer M2 can be arbitrarily determined.

Furthermore, within the first wafer W, crack C2 extends along the direction of formation of the inner surface modified layer M2, that is, along the surface of the first wafer W. Later, during separation of the first wafer W, this inner surface modified layer M2 and crack C2 serve as the base point for peeling the separation wafer Wd2 from the device wafer Wd1. As shown in Figure 6, for proper peeling, it is desirable that the radially outer end of crack C2 connects to the upper end of crack C1, and that cracks C2 extending from adjacent inner surface modified layers M2 connect to each other.

Here, in this embodiment of the present invention, the peripheral modified layer M1 is formed by rotating the stacked wafer T while shifting the laser beam irradiation position radially inward of the first wafer W and toward the back surface Wb of the first wafer W, as described above. Furthermore, the internal surface modified layer M2 is formed by rotating the stacked wafer T while shifting the laser beam irradiation position radially inward of the first wafer W, as described above.

Specifically, in this embodiment of the present invention, by stopping the movement of the laser beam irradiation position during the formation of the peripheral modified layer M1 in the thickness direction, the internal surface modified layer M2 can be formed continuously following the formation of the peripheral modified layer M1. In other words, there is no need to stop laser beam irradiation when transitioning from the formation of the peripheral modified layer M1 to the formation of the internal surface modified layer M2. Furthermore, by continuously forming the peripheral modified layer M1 and the internal surface modified layer M2 radially outward without stopping laser beam irradiation, the processing throughput associated with the modified layer formation operation in the internal modification device 61 can be significantly improved.

The stacked wafer T, with the internal surface modified layer M2 formed thereon, is then transferred to the processing apparatus 80 by the wafer transfer apparatus 50. In the processing apparatus 80, as shown in FIG4(e), the stacked wafer T is first transferred from the transfer arm 71 to the chuck 83. The first wafer W is then separated into the device wafer Wd1 and the separation wafer Wd2, using the peripheral modified layer M1, the crack C1, the internal surface modified layer M2, and the crack C2 as the starting points (step P4 in FIG5). At this point, the peripheral portion We of the first wafer W is also integrated with the separation wafer Wd2 and removed from the first wafer W.

In step P4, the first wafer W is separated by suction and hold by the suction surface 71a of the transfer arm 71, while the second wafer S is suction and hold by the chuck 83. With the suction surface 71a suctioning and holding the back surface Wb of the first wafer W, the transfer arm 71 is then raised, separating the first wafer W into the device wafer Wd1 and the separation wafer Wd2. As described above, in step P4, the separation wafer Wd2 is separated integrally with the peripheral portion We. In other words, the removal of the peripheral portion We and the separation (thinning) of the first wafer W are performed simultaneously.

Here, when the peripheral modified layers M1 are arranged in the thickness direction of the first wafer W, there is a concern that when the separation wafer Wd2 is pulled upward by the transfer arm 71, the separation wafer Wd2 may interfere with the corner K of the device wafer Wd1, as shown in Figure 1. Furthermore, if the separation wafer Wd2 and the device wafer Wd1 interfere with each other in this manner, there is a concern that the corner K may break. To address this issue, in an embodiment of the present invention, adjacent peripheral modified layers M1 are offset in the thickness direction and radial direction, in other words, arranged in an oblique direction. This prevents the formation of corners K on the device wafer Wd1, and reduces interference between the device wafer Wd1 and the separation wafer Wd2 during the ascent of the separation wafer Wd2. Furthermore, by suppressing the chipping of the corners K, degradation of the finished device wafer can be minimized, while also minimizing contamination of the wafer processing system 1 by particles generated by chipping.

Furthermore, the separated wafer Wd2 is recovered outside the wafer processing system 1, for example. Alternatively, a recovery unit (not shown) may be provided within the movable range of the transfer arm 71, and the separated wafer Wd2 may be recovered in the recovery unit.

Furthermore, in the embodiment of the present invention, the first wafer W is separated using the transfer arm 71 in the processing device 80. However, a separation device (not shown) for separating the first wafer W may also be provided in the wafer processing system 1. For example, the separation device may be stacked with the interface modification device 60 and the internal modification device 61. Furthermore, the method for separating the first wafer W may be arbitrarily determined.

After separating the first wafer W, the chuck 83 is moved to processing position A1, and as shown in Figure 4(f), the grinding unit 84 grinds the separation surface of the device wafer Wd1 (step P5 in Figure 5). This grinding process removes the peripheral modified layer M1 and internal modified layer M2 remaining on the separation surface of the device wafer Wd1, while reducing the device wafer Wd1 to the desired final thickness.

The stacked wafer T, after the first wafer W is thinned to the desired thickness in the processing apparatus 80, is transported to the cleaning apparatus 41 by the wafer transport apparatus 70, where the polished surface of the device wafer Wd1 is cleaned (step P6 in FIG5 ).

Next, the stacked wafer T is transported to the etching apparatus 40 by the wafer transport apparatus 50, where the polished surface of the device wafer Wd1 is wet-etched using a chemical solution (step P7 in FIG5 ).

After all the processing has been completed, the stacked wafers T are transferred to the transfer device 30 by the wafer transport device 50 and further transferred to the wafer cassette Ct on the wafer cassette stage 10 by the wafer transport device 20. This completes the entire wafer processing cycle in the wafer processing system 1.

Furthermore, in the above embodiment, the unbonded region Ae is formed in the interface modification device 60 located within the wafer processing system 1. However, the unbonded region Ae may be formed in advance before the stacked wafers T are loaded into the wafer processing system 1. In this case, the interface modification device 60 may be omitted from the configuration of the wafer processing system 1.

According to the above embodiment, by offsetting adjacent peripheral modified layers M1 in the thickness and radial directions and arranging them in an oblique direction, cracks C1 extending from the peripheral modified layers M1 can be prevented from reaching the back surface Wb of the first wafer W. This prevents the peripheral portion We from accidentally peeling off from the separation wafer Wd2, allowing the separation wafer Wd2 to be properly reused.

Furthermore, according to the above embodiment, the peripheral modified layer M1 and the internal surface modified layer M2 can be formed continuously from the diameter of the first wafer W outward without stopping the laser beam irradiation. This can appropriately increase the processing throughput related to the modified layer formation operation in the internal modifying device 61.

Furthermore, according to the above-described embodiments of the present invention, by aligning adjacent peripheral modified layers M1 in an oblique direction, corner portions K are prevented from forming at the ends of the device wafer Wd1. This can prevent stress concentration at the ends of the device wafer Wd1 during separation of the first wafer W. This can prevent chipping at the ends of the device wafer Wd1 during separation of the first wafer W, thereby suppressing the generation of particles within the wafer processing system 1 and preventing defects in the finished device wafer Wd1.

Furthermore, if the adjacent peripheral modified layers M1 are formed in an oblique arrangement, as shown in FIG4(f), the end of the device wafer Wd1 reduced to its final finishing thickness will have a tilt, and there is concern that the device wafer Wd1 may not be properly manufactured at this end. Therefore, the peripheral modified layers formed in the wafer processing system 1 are preferably formed in an arranged direction perpendicular to the plane direction of the first wafer W, starting from the final finishing thickness of the device wafer Wd1, at least on the surface Wa side.

Specifically, as shown in FIG8 , the peripheral modified layer formed within the first wafer W preferably includes: a first peripheral modified layer M1 arranged in an oblique direction as in the above-described embodiment; and a second peripheral modified layer M3 arranged in the thickness direction of the first wafer W.

As described above, the first peripheral modified layer M1 is formed obliquely within the first wafer W, with the upper end of the crack C1 connecting to the outer peripheral end of the crack C2 extending from the inner surface modified layer M2. Furthermore, the lower end of the crack C1 does not reach the surface Wa of the first wafer W but is located at least above the final finished thickness G of the device wafer Wd1.

The second peripheral modified layer M3 is formed within the first wafer W in the thickness direction. It is preferably formed slightly radially inward of the boundary Ad between the unbonded area Ae and the bonded area Ac, and above the final finish thickness G of the device wafer Wd1. Furthermore, a crack C3 extending from the second peripheral modified layer M3 in the thickness direction of the first wafer W has its lower end reaching the surface Wa of the first wafer W, and its upper end connecting to the lower end of the crack C1.

By forming the second peripheral modified layer M3 in the thickness direction of the first wafer W and positioning it above the final finishing thickness G of the device wafer Wd1, the formation of a tilt at the end of the finished device wafer Wd1 can be effectively suppressed. Furthermore, the peripheral modified layers M1 and M3 can be effectively prevented from remaining on the device wafer Wd1 after the finish grinding process. Furthermore, by forming the peripheral modified layer M1 in an oblique direction above the final finishing thickness G, the formation of a corner K on the device wafer Wd1 during separation of the first wafer W can be effectively suppressed. Furthermore, by arranging the second peripheral modified layer M3 in the thickness direction of the first wafer W, the crack C3 can be more easily extended in the thickness direction of the first wafer W, that is, the crack C3 can be appropriately extended to the surface Wa of the first wafer W.

Furthermore, in the above embodiment, for example, when forming the peripheral modified layer M1, the irradiation position of the laser light is moved at a constant speed in the radial and thickness directions of the first wafer W, and as shown in FIG6, the peripheral modified layer M1 is arranged in a substantially straight line shape when viewed in cross section. However, the arrangement of the peripheral modified layer M1 is not limited to this. For example, by controlling the movement of the irradiation position of the laser light during the formation of the peripheral modified layer M1, the peripheral modified layer M1 can be arranged in a substantially arc shape when viewed in cross section, as shown in FIG9. In this case, since the corner portion K is not formed on the device wafer Wd1, the device wafer Wd1 can be appropriately suppressed from being broken when the first wafer W is separated. Furthermore, since the peripheral modified layer M1 is not formed in an aligned manner in the thickness direction, the crack C1 can be prevented from extending in the thickness direction of the first wafer W and reaching the back surface Wb of the first wafer W.

Furthermore, in the above embodiment, an unbonded region Ae is formed at the interface between the first wafer W and the device layer D in the interface modification device 60 located inside or outside the wafer processing system 1. However, the formation of an unbonded region Ae is not essential. Specifically, as shown in FIG2 , the peripheries of the first wafer W and the second wafer S are chamfered, thereby forming chamfered portions whose thickness decreases toward the ends. In other words, in the stacked wafer T formed by bonding the first wafer W and the second wafer S with the chamfered portions formed in this manner, the first wafer W and the second wafer S can be considered unbonded at the chamfered portions.

As shown in FIG10 , the area where the chamfers R of the first and second wafers W and S in the stacked wafer T are formed can also be considered the unbonded area Ae. In other words, the chamfers R can be considered the peripheral portion We of the first wafer W to be removed. Specifically, the inner peripheral edge of the chamfers R can be considered the boundary Ad in the aforementioned embodiment, and the peripheral modified layer M1 can be formed slightly radially inward of the boundary Ad. In this case, the lower edge of the crack C1 extending from the peripheral modified layer M1 is formed so as to reach the radially inner edge of the chamfer R on the surface Wa side of the first wafer W. This eliminates the need to form an unbonded area Ae at the interface of the first wafer W through laser irradiation, shortening wafer processing time. Furthermore, the interface modification device 60 is no longer required, simplifying the system configuration. Furthermore, by ensuring that the lower end of the crack C1 reaches the radially inner end of the chamfer R, the peripheral portion We can be more effectively removed.

Furthermore, as shown in FIG11( a ), a peripheral modified layer M1 can also be formed inside the first wafer W in such a manner that the crack C1 reaches the surface Wa and the back surface Wb of the first wafer W, respectively. That is, as shown in FIG11( b ), the peripheral modified layer M1 and the crack C1 can be used as base points to remove only the peripheral portion We from the first wafer W. The removed peripheral portion We is, for example, recovered to a recovery portion (not shown). In this manner, when the peripheral modified layer M1 is arranged in an oblique direction and the peripheral portion We is removed, as shown in the above-mentioned embodiment, the formation of a corner portion K on the first wafer W after the peripheral portion We is removed can be suppressed, that is, the generation of cracks in the corner portion K of the first wafer W can be suppressed. Furthermore, this can suppress the generation of particles within the wafer processing system 1 and prevent degradation in the quality of the first wafer W (device wafer Wd1), which is the product.

Furthermore, when only the peripheral portion We is removed from the first wafer W, using the peripheral modified layer M1 and crack C1 as a starting point, the back surface Wb of the first wafer W is subsequently polished in a processing apparatus 80, for example, to thin the first wafer W. In this case, as shown in FIG11 , by forming the crack C1 obliquely relative to the front surface Wa of the first wafer W, chipping of the outer edge of the polished first wafer W can be suppressed. This also suppresses the generation of particles within the wafer processing system 1 after polishing, and reduces the quality degradation of the finished first wafer W (device wafer Wd1).

When the technology of the present invention is used to suppress chipping on the outer edge of the first wafer W after polishing, the crack C1 is formed in an oblique direction relative to the surface Wa of the first wafer W. Furthermore, during the process of forming the crack C1 in the oblique direction, the crack C1 can also be oriented perpendicularly to the surface Wa of the first wafer W. In other words, the lower end of the crack C1 can be formed in an oblique direction relative to the surface Wa, while the upper end of the crack C1 can be formed perpendicularly to the back surface Wb. However, the area in which the crack C1 extends perpendicularly to the surface Wa of the first wafer W is formed so that it can be removed by subsequent polishing.

The crack C1 is located at an oblique position relative to the surface Wa of the first wafer W (i.e., the direction of the crack C1 changes from perpendicular to oblique). It is located at the inner peripheral edge of the unbonded region Ae between the first wafer W and the second wafer S. Alternatively, the position may be located slightly radially inward from the inner peripheral edge of the unbonded region Ae. Furthermore, this unbonded region Ae may be a modified unbonded region Ae with reduced bonding strength, as shown in FIG6 , or may be a chamfered portion R, as shown in FIG10 .

Furthermore, when only the peripheral portion We is removed from the first wafer W using the peripheral modified layer M1 and the crack C1 as starting points, it is preferably divided into smaller pieces in the circumferential direction. For example, a method for dividing the peripheral portion We into smaller pieces is to form a plurality of divided modified layers M4 within the peripheral portion We and then divide the peripheral portion We into smaller pieces using the plurality of divided modified layers M4 as starting points.

Specifically, for example, in the internal modification device 61, laser light is irradiated onto the interior of the first wafer W (peripheral portion We). As shown in Figures 12 and 13 , multiple segmented modified layers M4 are formed perpendicularly to the surface of the first wafer W and along the radial direction of the first wafer W. In the illustrated example, radially extending lines dividing the modified layer M4 are formed at eight locations. However, if the lines dividing the modified layer M4 are formed at at least two locations, the peripheral portion We can be fragmented and removed.

The multiple divided modified layers M4 are formed radially outward from the upper end of the crack C1 (the portion reaching the back surface Wb). Furthermore, the multiple divided modified layers M4 are formed above the peripheral modified layer M1 and the crack C1 in the thickness direction of the first wafer W, such that the lower end of the crack C4 extending from the divided modified layer M4 (described later) reaches the peripheral modified layer M1 or the crack C1. For example, the multiple divided modified layers M4 of this embodiment of the present invention are formed by controlling the radial distance of the irradiated laser light in accordance with the thickness position of the first wafer W. In this case, the lower end of the crack C4 preferably does not pass through the peripheral modified layer M1 or the crack C1.

Furthermore, since the multiple divided modified layers M4 are removed as the peripheral portion We, the position of the bottommost divided modified layer M4 is not particularly limited. In the embodiment of the present invention, the bottommost divided modified layer M4 is formed above the final finishing thickness height G.

Furthermore, the crack C4 extends from the split modified layer M4. In the region radially outward from the boundary Ad between the unbonded region Ae and the bonded region Ac, the upper end of the crack C4 reaches the back surface Wb, and the lower end reaches the surface Wa. On the other hand, in the region radially inward from the boundary Ad, the upper end of the crack C4 reaches the back surface Wb, and the lower end reaches the peripheral modified layer M1 or the crack C1. Furthermore, the formation timing of the crack C4 is not limited to the embodiment of the present invention. For example, the crack C4 may reach the back surface Wb not when the split modified layer M4 is formed by irradiation with laser light, but when the peripheral portion We is removed. The method for removing the peripheral portion We is not particularly limited. For example, the peripheral portion We can be removed by suction and holding it, or by impacting it. Alternatively, a sharp-tipped insertion member (such as a wedge-shaped roller or blade) can be inserted from the side of the stacked wafer T into the interface between the peripheral portion We and the device layer D.

According to an embodiment of the present invention, when removing the peripheral portion We, the peripheral portion We is separated using the annular peripheral modified layer M1 as a base point and then divided into multiple pieces by the segmented modified layer M4. This allows the peripheral portion We to be broken down into smaller pieces, making it easier to remove.

Furthermore, in this embodiment of the present invention, the segmented modified layer M4 is formed above the peripheral modified layer M1 and the crack C1, with the lower end of the crack C4 reaching the peripheral modified layer M1 or the crack C1. In other words, the segmented modified layer M4 is formed broadly radially outward from the upper end of the crack C1. Thus, the segmented modified layer M4 can reliably fragment the peripheral portion We.

Furthermore, the position where the divided modified layer M4 is formed radially outward from the peripheral modified layer M1 and the crack C1 is not limited to the above-described embodiment.

For example, as shown in Figure 14 , the multiple divided modified layers M4 can also be formed radially outward of the outermost side of the peripheral modified layer M1 on the first wafer W. That is, the multiple divided modified layers M4 can also be formed radially outward of the boundary Ad between the unbonded area Ae and the bonded area Ac. Furthermore, the position of the bottommost divided modified layer M4 is not particularly limited; however, in embodiments of the present invention, it is positioned above the final finish thickness height G. Cracks C4 extending from the divided modified layer M4 reach both the front surface Wa and the back surface Wb.

In this case, similar to the above-described embodiment, the peripheral portion We can be easily fragmented and removed by dividing the modified layer M4. Furthermore, in this embodiment of the present invention, since the radial distance of the irradiated laser light is preferably uniform across the thickness of the first wafer W, laser processing can be performed more easily. In particular, if the radial distance between the upper end of the crack C1 and the boundary Ad is sufficiently small, the peripheral portion We can be properly divided even if no modified layer exists between the peripheral modified layer M1 and the divided modified layer M4.

Furthermore, in the examples shown in Figures 13 and 14 above, the crack C1 is formed in an oblique direction relative to the surface Wa of the first wafer W. However, the direction of the crack C1 may also be oriented perpendicularly to the surface Wa of the first wafer W during the process of forming the oblique crack C1.

Furthermore, in the above embodiments, the stacked wafer T includes the device layer D, but it may also be a stacked wafer that does not include the device layer D.

Furthermore, in the above embodiment, the example of "removing and thinning the peripheral portion of the first wafer W in a stacked wafer T formed by bonding a first wafer W and a second wafer S in the wafer processing system 1" is used for description. However, the first wafer W may not be bonded to the second wafer S.

It should be understood that the embodiments disclosed herein are illustrative only and not restrictive. The embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended patent applications.

Ac: junction area

Ad:Border

Ae: Unjoined area

C1, C2: Cracks

D: Component layer

Fw, Fs: surface film

S: Second wafer

T: stacked wafers

M1: Peripheral modified layer

M1(1): The outermost peripheral modified layer

M2: Internal surface modification layer

W: First wafer

Wa: surface

Wb: Back

Claims (6)

A substrate processing method is used to process a laminated substrate formed by bonding a first substrate to a second substrate, comprising the following steps: irradiating a laser beam from the back side of the first substrate, and forming a plurality of first peripheral modified layers along the boundary between the peripheral portion of the first substrate to be removed and the central portion of the first substrate; the plurality of first peripheral modified layers are formed at different height positions in a manner from the outer side to the inner side of the first substrate and from the inner surface side to the back side of the first substrate; irradiating the first peripheral modified layers with a laser beam; A plurality of segmented modified layers are formed radially along the interior of a first substrate. The plurality of segmented modified layers are formed radially outward from the upper end of a first torsion crack extending from the first peripheral modified layer. The plurality of segmented modified layers are formed such that, above the first peripheral modified layer and the first torsion crack in the thickness direction of the first substrate, the lower end of a fourth torsion crack extending from the segmented modified layer reaches the first peripheral modified layer or the first torsion crack, while the lower end of the fourth torsion crack does not pass through the first peripheral modified layer or the first torsion crack. The substrate processing method of claim 1, wherein the plurality of segmented modified layers are also formed radially outward of the first substrate relative to the outermost sides of the plurality of first peripheral modified layers. The substrate processing method of claim 2 further comprises the steps of: forming an unbonded region in the peripheral portion that reduces the bonding strength between the first substrate and the second substrate; and forming the plurality of segmented modified layers radially outward from a boundary between the unbonded region and a bonding region formed by bonding the first substrate and the second substrate. A substrate processing device is used to process a stacked substrate formed by bonding a first substrate to a second substrate, comprising: a modifying portion for irradiating a laser beam from the back side of the first substrate and forming a plurality of first peripheral modified layers along the boundary between the peripheral portion of the first substrate to be removed and the central portion of the first substrate; and a control portion for controlling the formation of the modified layer on the first substrate; the control portion controls the operation of the modifying portion so that the plurality of first peripheral modified layers are formed from the radially outer side to the inner side of the first substrate and from the inner surface side to the back side of the first substrate. The plurality of segmented modified layers are formed at different heights and laser light is irradiated into the interior of the first substrate to form a plurality of segmented modified layers along the radial direction of the first substrate. The plurality of segmented modified layers are formed radially outward from the upper end of a first torsion crack extending from the first peripheral modified layer. The plurality of segmented modified layers are formed such that: above the first peripheral modified layer and the first torsion crack in the thickness direction of the first substrate, the lower end of a fourth torsion crack extending from the segmented modified layer reaches the first peripheral modified layer or the first torsion crack; and the lower end of the fourth torsion crack does not pass through the first peripheral modified layer or the first torsion crack. The substrate processing apparatus of claim 4, wherein the control unit controls the operation of the modifying unit so that the plurality of divided modified layers are also formed radially outward of the first substrate relative to the outermost side of the plurality of first peripheral modified layers. The substrate processing apparatus of claim 5, wherein: the reforming section forms an unbonded region in the peripheral portion that reduces the bonding strength between the first substrate and the second substrate; and the control section controls the operation of the reforming section so that the plurality of divided reformed layers are formed radially outward of a boundary between the unbonded region and a bonding region formed by bonding the first substrate and the second substrate.