TWI864600B - Memory management device and method applied to intelligence processing unit - Google Patents

Abstract

A memory management device includes a pre-fetch circuit, a setting circuit, and a mapping circuit. The pre-fetch circuit receives original data via a direct memory access (DMA) circuit, and the original data indicates a mapping relation between a first virtual address and physical addresses of a memory. The setting circuit analyzes the original data to sequentially map the physical addresses into second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores a mapping relation between the physical addresses and the second virtual addresses to be a first mapping table and utilizes the first mapping table according to at least read request corresponding to at least one channel of the DMA circuit to access the memory.

Description

Memory management device and method for intelligent processor

This case is about a memory management device and method, and in particular, a memory management device and method that can improve the memory management efficiency of an intelligent processor.

With the development of artificial intelligence technology, the use scenarios of smart processors are becoming more and more diverse. In the existing technology, the internal storage space of the smart processor can be increased to meet the memory bandwidth access requirements of the smart processor for these scenarios. In the existing technology, the memory management of the smart processor may generate fragmented data access (usually involving multiple discontinuous physical addresses), or require a complete search buffer to obtain the physical address of the memory. This will make the memory management efficiency inefficient, thereby affecting the instruction processing efficiency.

In some implementations, one of the purposes of this case is to provide a memory management device and method to improve the shortcomings of the prior art.

In some embodiments, a memory management device for an intelligent processor includes a pre-fetch circuit, a setting circuit, and a mapping circuit. The pre-fetch circuit obtains an original data through a direct memory access circuit, and the original data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. The setting circuit parses the original data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between the physical addresses and the second virtual addresses as a first mapping table according to the write request, and uses the first mapping table to access the memory according to at least one read request corresponding to at least one channel of the direct memory access circuit.

In some implementations, the memory management method includes the following operations: obtaining a raw data through a direct memory access circuit, the raw data indicating a mapping relationship between a first virtual address and a plurality of physical addresses of a memory; parsing the raw data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issuing a write request; and storing the mapping relationship between the physical addresses and the second virtual addresses as a first mapping table according to the write request, and using the first mapping table to access the memory according to at least one read request corresponding to at least one channel of the direct memory access circuit.

The features, implementation and effects of this case are described in detail below with reference to the diagrams for a preferred embodiment.

All terms used in this article have their usual meanings. The definitions of the above terms in commonly used dictionaries and the use examples of any term discussed herein in the content of this case are only examples and should not limit the scope and meaning of this case. Similarly, this case is not limited to the various embodiments shown in this specification.

As used herein, "coupling" or "connection" may refer to two or more components making physical or electrical contact directly or indirectly, or two or more components operating or acting on each other. As used herein, the term "circuit" may refer to a device that is composed of at least one transistor and/or at least one active and passive component connected in a certain manner to process signals.

FIG1 is a schematic diagram of a memory management device 100 according to some embodiments of the present invention. In some embodiments, the memory management device 100 can be applied to an intelligent processor (Intelligence Processing Unit) to manage the internal memory of the intelligent processor to improve the utilization rate of the internal memory.

The memory management device 100 includes a pre-fetch circuit 110, a setting circuit 120, a mapping circuit 130, and a control circuit 140. The pre-fetch circuit 110 is coupled to a direct memory access circuit 100A to access an external memory (such as, but not limited to, a dynamic random access memory) and/or a cache memory in an intelligent processor. The pre-fetch circuit 110 can obtain the original data OD through the direct memory access circuit 100A. In some embodiments, the original data OD can indicate a mapping relationship between a first virtual address and a plurality of physical addresses in a memory (such as the aforementioned external memory or cache memory). The setting method of the original data OD will be explained later with reference to Figure 2.

In some embodiments, in the initial stage or after the memory management device 100 is first started, the pre-fetch circuit 110 can configure the parameters inside the circuit (for example, but not limited to, the value of the register) via the trigger signal TR1 sent by the main processor (for example, the central processor) in the system. In subsequent operations, the main processor (and/or the control circuit 140) can send subsequent trigger signals TR1 according to the command CMD to be executed to control the pre-fetch circuit 110 to obtain the corresponding original data OD via the direct memory access circuit 100A.

In some embodiments, the pre-fetch circuit 110 further determines whether the remaining data capacity in the pre-fetch circuit 110 is sufficient to store a portion of the original data OD, so as to selectively store the portion of the data until the original data OD is completely stored. For example, the pre-fetch circuit 110 includes a pre-fetch control circuit 111 and a buffer circuit 112. The pre-fetch control circuit 111 is controlled by the trigger signal TR1, and sequentially reads a plurality of partial data (which may constitute the original data OD) through the direct memory access circuit 100A. The pre-fetch control circuit 111 can determine whether the current remaining data capacity of the buffer circuit 112 is greater than or equal to the data volume of a partial data, so as to selectively control the buffer circuit 112 to store the partial data. For example, if the current remaining data capacity of the buffer circuit 112 is greater than or equal to the data volume of a partial data, the pre-fetch control circuit 111 can control the buffer circuit 112 to receive and store the partial data via the direct memory access circuit 100A. Similarly, the pre-fetch control circuit 111 can repeatedly perform the above operation until the complete original data OD is stored (i.e., pre-fetched) in the buffer circuit 112. In some embodiments, the direct memory access circuit 100A in the smart processor supports data transfer with multiple strides, multiple levels of length, and memory alignment (byte align). Therefore, in the above-mentioned process of pre-fetching the original data OD, the pre-fetch control circuit 111 can gradually transfer the partial data, wherein each partial data can have a fixed length, for example, but not limited to, 256 bits.

The setting circuit 120 parses the original data OD to sequentially map the aforementioned multiple physical addresses to multiple second virtual addresses (including the first virtual address) and issues a write request WR. In some embodiments, the setting circuit 120 can be implemented by a decoder and a state machine to parse according to the data format of the original data OD to obtain the mapping relationship between the physical addresses and the second virtual addresses. The operation here can be explained with reference to Figure 3. After obtaining the above-mentioned mapping relationship, the setting circuit 120 can issue a write request WR to the mapping circuit 130, thereby storing the above-mentioned mapping relationship as a mapping table. In some embodiments, the setting circuit 120 is controlled by the trigger signal TR2. The control circuit 140 can decode a command CMD from the main processor to generate the trigger signal TR2 to control the setting circuit 120 to parse the original data OD to update the mapping relationship between the virtual address and the physical address.

The mapping circuit 130 stores the mapping relationship between the physical addresses and the second virtual addresses in the first storage space of the mapping circuit 130 as a first mapping table according to the write request WR, and uses the first mapping table to access the external memory or cache memory according to one or more (at least one) read requests RR1-RRN from the direct memory access circuit 100A, wherein the read requests RR1-RRN correspond to different channels of the direct memory access circuit 100A. For example, when a part of the instructions or operations in the command CMD of the main processor are executed by the intelligent processor, the intelligent processor can issue one or more read requests RR1-RRN to the mapping circuit 130 through the direct memory access circuit 100A. The mapping circuit 130 can utilize the first mapping table (or other mapping tables that can indicate the mapping relationship between other virtual addresses and other physical addresses) based on the one or more read requests RR1~RRN to obtain the actual storage address (i.e., physical address) of the desired instruction and/or data in the aforementioned external memory or cache memory, and then obtain the desired instruction and/or data from the external memory or cache memory.

In some embodiments, the mapping circuit 130 further temporarily stores the read requests RR1~RRN and the write requests WR, and arbitrates the read requests RR1~RRN and the write requests WR to determine the order in which each of the read requests RR1~RRN and the write requests WR accesses the multiple storage spaces of the mapping circuit 130.

In detail, the mapping circuit 130 includes an arbitration circuit 131 and a memory 132. The arbitration circuit 131 includes a buffer 131A, which can temporarily store the read requests RR1~RRN and the write requests WR. In this way, it can be avoided that the arbitration circuit 131 stops receiving write requests and/or read requests due to abnormalities such as too many requests during the arbitration process. The arbitration circuit 131 can execute an arbitration algorithm to determine the order in which the write request WR and the read requests RR1~RRN access the multiple storage spaces of the memory 132. In some embodiments, the arbitration algorithm can be, but is not limited to, a Round-Robin algorithm. The memory 132 includes multiple storage spaces, which can store multiple mapping tables respectively. For example, the arbitration circuit 131 can store the mapping relationship between the physical addresses and the second virtual addresses in the first storage space among the multiple storage spaces in response to the write request WR as a first mapping table.

By setting the arbitration circuit 131, the direct memory access circuit 100A and the setting circuit 120 can access multiple mapping tables in the mapping circuit 130 in parallel, thereby realizing efficient memory management. For example, when the setting circuit 120 wants to store the first mapping table in the first storage space of the memory 132 (corresponding to the write request WR) and the direct memory access circuit 100A wants to read the mapping table of the second storage space in the memory 132 (for example, corresponding to the read request RR1), since the storage spaces to be accessed by the two are different, the arbitration circuit 131 allows the setting circuit 120 and the direct memory access circuit 100A to access the first and second storage spaces at the same time. In other words, in this case, the period during which the circuit 120 writes the first mapping table to the first storage space and the period during which the direct memory access circuit 100A reads the second storage space at least partially overlap. In this way, the access efficiency of the memory 132 can be improved, thereby improving the efficiency of memory management.

The control circuit 140 can decode the command CMD from the main processor and determine the dependencies in the command CMD to set the multiple trigger signals TR2 and S1~SN. The control circuit 140 can determine the operation status of the multiple storage spaces in the memory 132 according to the multiple virtual register values corresponding to the multiple trigger signals TR2 and S1~SN (for example, the multiple virtual register values EVR1~EVR4 and EVR1'~EVR4' in FIG. 4B) to set the output sequence of the multiple trigger signals TR2 and S1~SN. As described above, the trigger signal TR2 can trigger the setting circuit 120 to issue a write request WR, and the remaining multiple trigger signals S1~SN can trigger the direct memory access circuit 100A to issue the read requests RR1~RRN. The multiple trigger signals S1~SN correspond to the read requests RR1~RRN respectively. For example, the trigger signal S1 can trigger the direct memory access circuit 100A to issue a read request RR1, and the trigger signal S2 can trigger the direct memory access circuit 100A to issue a read request RR2. By analogy, the corresponding relationship between the multiple trigger signals S1~SN and the read requests RR1~RRN should be understood. The detailed operation of the control circuit 140 will be described later with reference to FIG. 4A and FIG. 4B .

FIG2 is a schematic diagram of the original data OD in FIG1 according to some embodiments of the present invention. As shown in FIG2, the original data OD includes multiple columns of data, each column of data includes 16 information, and each information may include 16 bits. In other words, the length of a column of data is 256 bits.

Taking the data from the 1st to 3rd rows as an example, based on the order from right to left and from top to bottom, the original data OD includes quantity information (marked as TL=32), tag information (marked as Tag), quantity information (marked as LEN=4), information of the first virtual address (marked as VA), information of multiple physical addresses (marked as PA0~PA3 in sequence), quantity information (marked as LEN=26), first virtual address (marked as The information of the first virtual address (indicated as VA), the information of multiple physical addresses (indicated as PA0~PA25 in sequence), the quantity information (indicated as LEN=1), the information of the first virtual address (indicated as VA), the information of the physical address (indicated as PA0), the quantity information (indicated as LEN=1), the information of the first virtual address (indicated as VA), the information of the physical address (indicated as PA0), and multiple invalid information (indicated as TL=0). It should be specially explained that the virtual address VA and the physical address PA0~PA25 in different information fields can represent different addresses. Multiple invalid information is fragmented useless information, which can be used to fill in the data to achieve bit alignment.

The quantity information TL=32 indicates that the number of all physical addresses to be set this time is 32. For example, in the data from the 1st to the 3rd columns, there are 32 pieces of information related to the physical address. The tag information Tag can be used to allow the setting circuit 120 to determine whether the correct original data OD is read. The quantity information LEN=4 indicates the incremented quantity of the virtual address VA (equivalent to the quantity of the second virtual address). For example, the virtual address VA (equivalent to the first virtual address or the second virtual address) can correspond to the physical address PA0 located on its left, the virtual address VA+1 (equivalent to the second virtual address) can correspond to the physical address PA1 on the left, and so on. The virtual address VA+3 can correspond to the physical address PA3. Furthermore, if further analogy is used, the subsequent quantity information LEN=26 and the virtual address VA can indicate that the virtual address VA corresponds to the physical address PA0, and the virtual address VA+25 corresponds to the physical address PA25. Based on this, it should be understood that the above-mentioned multiple information can indicate the mapping relationship between multiple physical addresses and multiple second virtual addresses.

Based on the above setting method, multiple physical addresses can be compressed to correspond to one virtual address. For example, in the first row, the quantity information LEN=4 can correspond one virtual address VA to four physical addresses PA0~PA3. In some embodiments, the original data OD can be pre-generated by an external system or a main processor. For example, the external system and the main processor can prepare the original data OD in advance based on the relevant scenarios applied by the neural network executed by the smart processor (that is, the original data OD is generated offline). In this way, the data volume can be compressed and the direct memory access circuit 100A can use continuous virtual addresses, thereby generating continuous instructions to reduce the frequency of replacing the mapping table.

FIG3 is a flow chart showing the operations performed by the setting circuit 120 of FIG1 according to some embodiments of the present invention. In some embodiments, the following multiple operations may be used to implement the operation of the state machine.

In operation S310, the next operation is executed from the idle state by triggering a trigger signal (e.g., trigger signal TR2). In operation S320, the original data is read, invalid information (e.g., invalid information TL=0 in FIG. 2 ) is discarded, and it is confirmed whether the quantity information is correctly read (e.g., quantity information TL=32). If the quantity information is correctly read, operation S330 is executed. In operation S330, the tag information (e.g., tag information Tag) is compared to confirm whether the correct original data is read. For example, when the control circuit 140 decodes the command CMD, the control circuit 140 can confirm the tag of the mapping table to be used for the operation or instruction related to the command CMD. The control circuit 140 can transmit the information of the tag and the trigger signal TR2 to the setting circuit 120. The setting circuit 120 can compare the tag information Tag in the original data OD to determine whether the correct original data OD is obtained. If the original data OD is obtained correctly, the operation S340 is executed. If the original data is not obtained correctly, the operation S350 is executed to report an error.

In operation S340, the information of the virtual address and the quantity information (for example, the quantity information TL=32) are parsed. If the parsing is completed, operation S360 is executed to parse the information of the multiple physical addresses to set the mapping relationship between the multiple second virtual addresses and the multiple physical addresses. For example, as mentioned above, in the first row of data in FIG. 2, the mapping relationship associated with the multiple physical addresses PA0~PA3 associated with the quantity information LEN=4 is: the virtual address VA corresponds to the physical address PA0, the virtual address VA+1 corresponds to the physical address PA1, the virtual address VA+2 corresponds to the physical address PA2, and the virtual address VA+3 can correspond to the physical address PA3 on the left. In other words, through operation S340 and operation S360, the setting circuit 120 can restore the compressed mapping relationship in the original data OD (i.e., one virtual address corresponds to multiple physical addresses) to a mapping relationship between multiple virtual addresses and multiple physical addresses. If in operation S360, the number of processed physical addresses is different from the value of the quantity information (e.g., TL=32), it means that the number of physical addresses is wrong. In this state, operation S350 is executed to report an error, and after reporting the error, the relevant data is cleared and the idle state is returned. In operation S370, a write request is issued and arbitration is waited for to be completed, and the mapping relationship between the plurality of second virtual addresses and the plurality of physical addresses is stored as a first mapping table before returning to an idle state.

FIG4A is a schematic diagram of the control circuit 140 in FIG1 according to some embodiments of the present invention. The control circuit 140 includes an instruction decoder 141, a plurality of task queue circuits 142[0]~142[N], a plurality of trigger circuits 143[0]~143[N], an external virtual register queue circuit 144, and a dependency confirmation circuit 145.

Each of the plurality of task queue circuits 142[0]-142[N] may be, but is not limited to, a first-in first-out (FIFO) circuit. The task queue circuit 142[0] stores the tasks to be executed by the setting circuit 120, and the task queue circuits 142[1]-142[N] respectively store the tasks to be executed by the 1st to Nth channels of the direct memory access circuit 100A. The plurality of trigger circuits 143[0]-143[N] are respectively configured to correspond to the plurality of task queue circuits 142[0]-142[N]. For example, the trigger circuit 143[0] may generate a trigger signal TR2 according to a request issued by the task queue circuit 142[0]. The trigger circuit 143[1] can generate a trigger signal S1 to the direct memory access circuit 100A according to the request issued by the task queue circuit 142[1], so that the first channel of the direct memory access circuit 100A issues a read request RR1. Similarly, the trigger circuit 143[N] can generate a trigger signal SN to the direct memory access circuit 100A according to the request issued by the task queue circuit 142[N], so that the Nth channel of the direct memory access circuit 100A issues a read request RRN.

The command decoder 141 can decode the command CMD to confirm the command or data required by the command CMD, and transmit the relevant tasks to multiple task queue circuits 142[0] and 142[1]~142[N] accordingly. For example, if the required command or data involves a physical address recorded in a new mapping table, the command decoder 141 can send the task to the task queue circuit 142[0]. The trigger circuit 143[0] can generate a new write request WR accordingly to control the setting circuit 120 to replace the existing mapping table.

In order to ensure that the setting circuit 120 and the control circuit 140 can correctly and concurrently use the multiple mapping tables stored in the mapping circuit 130, the operation status of the multiple storage spaces in the mapping circuit 130 can be determined by an external virtual register queue circuit 144 and a dependency confirmation circuit 145 to set the output sequence through the multiple trigger signals TR2 and S1~SN. The instruction decoder 141 can decode the command CMD, and set multiple external virtual register values (such as multiple external virtual register values EVR1~EVR4 and EVR1'~EVR4' in FIG. 4B) in the external virtual register queue circuit 144 according to the dependency between the instruction or data required by the command CMD, so as to record the operation status of multiple storage spaces in the mapping circuit 130 (for example, whether they are being written by the setting circuit 120 or being accessed by a channel of the direct memory access circuit). The dependency confirmation circuit 145 can confirm the output sequence of multiple trigger signals TR2 and S1~SN according to the dependency between the instruction or data and the multiple external virtual register values. According to the dependency between instructions or data, the dependency confirmation circuit 145 can set whether multiple task queue circuits 142[0]~142[N] can transmit requests to multiple trigger circuits 143[0]~143[N]. For example, the dependency confirmation circuit 145 can set the output sequence of multiple trigger signals TR2 and S1~SN by interrupting the connection between multiple task queue circuits 142[0]~142[N] and multiple trigger circuits 143[0]~143[N]. The description here will be described later with reference to FIG. 4B.

FIG4B is a schematic diagram of the work schedule of the setting circuit 120 and the direct memory access circuit 100A in FIG1 for accessing the memory 132 according to some embodiments of the present invention. In the example in FIG4B , the dependency confirmation circuit 145 can determine the order in which the setting circuit 120 and the direct memory access circuit 100A access the memory 132 according to the dependencies between the multiple instructions. In some embodiments, the dependency confirmation circuit 145 can record the dependencies between the multiple instructions and/or data in advance according to the multiple related scenarios applied by the smart processor, so as to set the output order of the multiple trigger signals TR2 and S1~SN according to the instructions included in the currently received command CMD.

For example, in some scenarios, the decoded command CMD includes multiple instructions corresponding to a series of mathematical operations (such as image processing operations or convolution operations, etc.). For example, the first instruction may be a convolution operation, and the second instruction uses the calculation result of the convolution operation to perform filtering processing to generate the next output. The dependency confirmation circuit 145 allows the direct memory access circuit 100A to first use the multiple physical addresses indicated in the first mapping table of the memory 132 to access the multiple instructions and/or data used in the convolution operation to perform the first level operation (such as the operation from time t1 to time t2). Then, the dependency confirmation circuit 145 allows the setting circuit 120 to replace the first mapping table of the memory 132 with the second mapping table (e.g., the operation from time t2 to time t3), and controls the direct memory access circuit 100A to access the multiple instructions and/or data used in the filtering process according to the multiple physical addresses indicated by the second mapping table to perform the second-level operation (e.g., the operation starting from time t3).

Specifically, at time t1, channel 1 of the direct memory access circuit 100A is reading the first mapping table in the memory 132 to obtain the physical address using the first mapping table and fetch the instruction or data from the aforementioned external memory or cache memory to perform the convolution operation. Therefore, the external virtual register value EVR1 (which is stored in the external virtual register queue circuit 144) corresponding to channel 1 of the direct memory access circuit 100A is switched to a default value (indicated by a slash background) to indicate that the corresponding storage space storing the first mapping table in the memory 132 is busy. At time t2, channel 1 of the direct memory access circuit 100A finishes reading the first mapping table. The setting circuit 120 may clear the corresponding storage space and write the second mapping table to the corresponding storage space. Therefore, the setting circuit 120 may switch the corresponding external virtual register values EVR1′ and EVR2′ (which are stored in the external virtual register queue circuit 144) to default values to indicate that the corresponding storage space in the memory 132 is busy. At time t3, the setting circuit 120 completes replacing the second mapping table, and the channel 2 of the direct memory access circuit 100A is reading the second mapping table in the memory 132 to obtain the physical address using the second mapping table and fetch the instruction or data from the aforementioned external memory or cache memory for filtering processing.

Channels 3 and 4 of the direct memory access circuit 100A access the second mapping table stored in the second storage space in the memory 132 to obtain the required data and/or data. Since the first storage space is different from the second storage space, the working time of channel 3 may partially overlap with the working time of channel 1 and/or the time when the setting circuit 120 writes to the first storage space. Similarly, the working time of channel 2 may partially overlap with the working time of channel 3 or 4 and/or the time when the setting circuit 120 writes to the second storage space (i.e., the time when the external virtual register values EVR3' and EVR4' are busy).

The operation between channel 3 and channel 4 of the direct memory access circuit 100A and the setting circuit 120 is similar to the above operation, so it will not be repeated. From the above operation process, it can be understood that the operation of the replacement mapping table of the setting circuit 120 will not affect the processing efficiency of channel 3. Similarly, the operation of the replacement mapping table of the setting circuit 120 will not affect the processing efficiency of channel 1. Accordingly, by setting multiple external virtual register values EVR1~EVR4 and EVR1'~EVR4', the setting circuit 120 and the direct memory access circuit 100A can access multiple storage spaces of the memory 132 in parallel with higher efficiency.

FIG5 is a flow chart of a memory management method 500 according to some embodiments of the present invention. In operation S510, an original data is obtained through a direct memory access circuit, and the original data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. In operation S520, the original data is parsed to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issue a write request. In operation S530, the mapping relationship between the physical addresses and the second virtual addresses is stored as a first mapping table according to the write request, and the memory is accessed using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

The description of the above-mentioned multiple operations can refer to the above-mentioned embodiments, so it will not be repeated. The multiple operations of the above-mentioned memory management method 500 are only examples, and are not limited to be executed in the order in this example. Without violating the operation mode and scope of each embodiment of this case, the various operations under the memory management method 500 can be appropriately added, replaced, omitted or executed in a different order (for example, they can be executed simultaneously or partially simultaneously).

In summary, the memory management device and memory management method in some embodiments of the present invention can realize dynamic updating of mapping tables inside the smart processor, generate compressed mapping relationship data offline, and parallelize access to improve the efficiency of memory management, thereby improving the operating efficiency of the smart processor.

Although the embodiments of this case are described above, these embodiments are not used to limit this case. People with ordinary knowledge in this technical field can make changes to the technical features of this case based on the explicit or implicit content of this case. All these changes may fall within the scope of patent protection sought by this case. In other words, the scope of patent protection of this case shall be subject to the scope of patent application defined in this specification.

100: Memory management device

100A: Direct memory access circuit

110: Prefetch circuit

111: Prefetch control circuit

112: Buffer circuit

120: Setting circuit

130: Mapping circuit

131: Arbitration circuit

131A: Buffer

132: Memory

140: Control circuit

141: Command decoder

142[0]~142[N]: Task queue circuit

143[0]~143[N]: Trigger circuit

144: External virtual register queue circuit

145: Dependency confirmation circuit

500:Memory management method

CMD: Command

EVR1-EVR4,EVR1’-EVR4’: virtual register value

LEN=4,LEN=26,LEN=1,LEN=5,LEN=1: Quantity information

OD:Original data

PA0~PA25: physical address

RR1~RRN: read request

S1~SN: trigger signal

S310,S320,S330,S340,S350,S360,S370: Operation

S510, S520, S530: Operation

TL=32,TL=4,TL=13: quantity information

TR1,TR2: trigger signal

Tag: Tag information

VA: Virtual Address

WR: Write Request

t1~t3: time

〔Figure 1〕is a schematic diagram of a memory management device according to some embodiments of the present invention; 〔Figure 2〕is a schematic diagram of the original data in Figure 1 according to some embodiments of the present invention; 〔Figure 3〕is a flow chart of the operation performed by the setting circuit in Figure 1 according to some embodiments of the present invention; 〔Figure 4A〕is a schematic diagram of the control circuit in Figure 1 according to some embodiments of the present invention; 〔Figure 4B〕is a schematic diagram of the work schedule of the setting circuit and the direct memory access circuit in Figure 1 accessing the memory according to some embodiments of the present invention; and 〔Figure 5〕is a flow chart of the memory management method according to some embodiments of the present invention.

100: Memory management device

100A: Direct memory access circuit

110: Prefetch circuit

111: Prefetch control circuit

112: Buffer circuit

120: Setting circuit

130: Mapping circuit

131: Arbitration circuit

131A: Buffer

132: Memory

140: Control circuit

CMD: Command

OD:Original data

RR1~RRN: read request

S1~SN: trigger signal

TR1,TR2: trigger signal

WR: Write Request

Claims (10)

A memory management device is applied to an intelligent processor. The memory management device comprises: a pre-fetch circuit, which obtains an original data through a direct memory access circuit, wherein the original data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory; a setting circuit, which parses the original data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request; and a mapping circuit, which stores the first virtual address according to the write request. The mapping relationship between the physical addresses and the second virtual addresses is a first mapping table, and the first mapping table is used to access the memory according to at least one read request of at least one channel corresponding to the direct memory access circuit, wherein the pre-fetch circuit includes: a buffer circuit; and a pre-fetch control circuit, which determines whether a remaining data capacity of the buffer circuit is greater than or equal to the data amount of a part of the original data, so as to selectively control the buffer circuit to store the part of the data. A memory management device as claimed in claim 1, wherein the original data includes a first quantity information, a second quantity information, a tag information, information of the first virtual address, and information of the physical addresses, wherein the first quantity information indicates the quantity of the physical addresses, and the second quantity information indicates the quantity of the second virtual addresses. As in the memory management device of claim 2, the setting circuit determines whether the original data is correctly pre-fetched according to the first quantity information and the tag information, and maps the physical addresses to the second virtual addresses in sequence according to the information of the first virtual address, the second quantity information and the information of the second virtual addresses. A memory management device as claimed in claim 3, wherein the setting circuit sequentially increments the first virtual address according to the information of the first virtual address and the second quantity information to generate the second virtual addresses. A memory management device as in claim 1, wherein the mapping circuit further arbitrates the write request and the at least one read request to determine the order in which each of the write request and the at least one read request accesses a storage space used to store the first mapping table. A memory management device as claimed in claim 1, wherein when the mapping circuit intends to store the first mapping table to a first storage space in the mapping circuit and the at least one read request intends to read a second storage space in the mapping circuit, the period during which the first mapping table is stored in the first storage space and the period during which the second storage space is read in response to the at least one read request at least partially overlap. A memory management device as claimed in claim 1, wherein the mapping circuit comprises: a memory comprising a plurality of storage spaces; and an arbitration circuit temporarily storing the at least one read request and the write request, and determining the order in which the write request and the at least one read request access the storage spaces, wherein the arbitration circuit stores the first mapping table to a corresponding storage space among the storage spaces in response to the write request to replace a second mapping table previously stored in the corresponding storage space. The memory management device of claim 1 further comprises: a control circuit that decodes an instruction from a host processor and determines the dependency of the instruction to set a plurality of trigger signals, and determines the operation status of a plurality of storage spaces in the mapping circuit according to the plurality of external virtual register values corresponding to the trigger signals to set the output sequence of the trigger signals, wherein a first trigger signal among the trigger signals is used to trigger the setting circuit to issue the write request, and the remaining trigger signals among the trigger signals are used to trigger the direct memory access circuit to issue the at least one read request. A memory management method comprises: obtaining an original data through a direct memory access circuit, the original data indicating a mapping relationship between a first virtual address and a plurality of physical addresses of a memory; parsing the original data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issuing a write request; storing the mapping relationship between the physical addresses and the second virtual addresses according to the write request; The mapping relationship between the second virtual addresses is a first mapping table, and the first mapping table is used to access the memory according to at least one read request corresponding to at least one channel of the direct memory access circuit; and the write request and the at least one read request are arbitrated to determine the order in which each of the write request and the at least one read request accesses a storage space used to store the first mapping table. A memory management method comprises: obtaining an original data through a direct memory access circuit, the original data indicating a mapping relationship between a first virtual address and a plurality of physical addresses of a memory; parsing the original data to sequentially map the physical addresses to a plurality of second virtual addresses including the first virtual address and issuing a write request; and storing the mapping relationship between the physical addresses and the second virtual addresses as a first mapping table according to the write request, and mapping the mapping relationship between the physical addresses and the second virtual addresses according to the first virtual address corresponding to the direct memory access circuit. At least one read request of at least one channel of the memory access circuit uses the first mapping table to access the memory, wherein the first mapping table is stored in a first storage space of a mapping circuit, and when the mapping circuit intends to store the first mapping table in the first storage space and the at least one read request intends to read a second storage space in the mapping circuit, the period during which the first mapping table is stored in the first storage space and the period during which the second storage space is read in response to the at least one read request at least partially overlap.

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