TWI847860B - Metrology method of overlay measurement for semiconductor manufacturing process - Google Patents

Abstract

A metrology method of an overlay measurement for a semiconductor manufacturing process includes measuring overlay marks of a wafer to obtain first overlay shifts and second overlay shifts respectively located in a first area and a second area of the wafer, in which the second area surrounds the first area of the wafer, and a center of the wafer and each of the overlay marks has a distance therebetween; when an overlay offset term and any one of the distances has a relation therebetween, extracting N of the first overlay shifts and M of the second overlay shifts based on the relation; and computing the overlay offset term by using the N of the first overlay shifts and the M of the second overlay shifts, such that the overlay offset term contains the influence of the distance on it.

Description

Metrology Method for Overlay Measurement in Semiconductor Processes

The present disclosure relates to a metrology method for overlay measurement in semiconductor manufacturing processes.

Generally speaking, the internal circuit of an integrated circuit chip includes various semiconductor components, such as diodes, transistors, capacitors and other components. The semiconductor components are interconnected through the overlay between layers to make different chips. Therefore, in the chip manufacturing process, the overlay shift between the stacking layers will affect the wafer yield, so the overlay measurement performed on the wafer is very important.

Currently, light or electron beams are usually used as measurement signals to perform overlay measurement on the overlay mark on the wafer before exposure. Based on the overlay offset detected on the wafer, the overlay compensation value (offset value) used to calibrate the machine can be calculated so that the pattern of the current layer can be more accurately aligned with the pattern of the previous layer in the subsequent process. Traditionally, the calculation of the overlay compensation value does not take into account the position of the overlay mark on the wafer, so there may still be inaccurate alignment after compensation.

One aspect of the present disclosure is a metrology method for overlay measurement in semiconductor manufacturing processes.

According to some embodiments of the present disclosure, a metrology method for stack pair measurement of a semiconductor process includes measuring a plurality of stack pair marks of a wafer to obtain a plurality of first stack pair offsets and a plurality of second stack pair offsets respectively located in a first region and a second region of the wafer, wherein the second region of the wafer surrounds the first region and each of the stack pair marks has a distance from a center point of the wafer; when any of the distances has a relationship with a stack pair compensation term, N of the first stack pair offsets and M of the second stack pair offsets are extracted according to the relationship, wherein N and M are positive integers; and the stack pair compensation term is calculated using the N of the first stack pair offsets and the M of the second stack pair offsets so that the stack pair compensation term includes the influence of the distance on it.

In some embodiments, the first region of the wafer has a first radius, the second region has a second radius away from the edge of the first region, the center point of the wafer is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, each of the overlapping marks is located in the xy coordinate system, and the relationship is that in the xy coordinate system, the overlapping complement term is proportional to the a power of one of the x coordinate and the y coordinate and proportional to the b power of the other of the x coordinate and the y coordinate, a and b are positive integers and a is greater than or equal to b, and the ratio of N/M is equal to the ratio of R1 ^a+1 /(R2 ^a+1 -R1 ^a+1 ), R1 is the first radius, and R2 is the second radius.

In some implementations, the above-mentioned metrology method for stack pair measurement of semiconductor process further includes extracting N first stack pair offsets and M second stack pair offsets when there is no correlation between any of the distances and the stack pair compensation term, where N and M are equal.

In some implementations, the stack complement term includes an inter-layer offset along an x-direction or an inter-layer offset along a y-direction, wherein the x-direction is perpendicular to the y-direction.

In some embodiments, the above-mentioned metrology method for overlay measurement of semiconductor process further includes obtaining a plurality of boundary overlay offsets in a boundary region contacting an edge of the wafer when measuring an overlay mark of the wafer.

In some implementations, the above-mentioned metrology method for stack pair measurement in semiconductor process further includes not extracting boundary stack pair offsets when extracting N of the first stack pair offsets and extracting M of the second stack pair offsets according to the relationship.

In some embodiments, the above-mentioned metrology method for overlay measurement in semiconductor process further includes obtaining a plurality of third overlay offsets located in a third area of the wafer surrounding the second area when measuring the overlay mark of the wafer.

In some implementations, the above-mentioned metrology method for stack pair measurement of semiconductor process further includes extracting the third stack pair offset according to the relationship while extracting the N first stack pair offsets and the M second stack pair offsets according to the relationship.

In some implementations, the calculating of the stack pair complement using the N first stack pair offsets and the M second stack pair offsets is to calculate the stack pair complement using an X offset, a Y offset, or a combination thereof of the N first stack pair offsets and an X offset, a Y offset, or a combination thereof of the M second stack pair offsets according to the stack pair complement.

In some implementations, the N first stacking pairs of offsets and the M second stacking pairs of offsets are in the same direction.

In the above-mentioned embodiment of the present disclosure, since the metrology method of overlay measurement includes extracting N of the first overlay offsets and M of the second overlay offsets according to the relationship, and using the N of the first overlay offsets and the M of the second overlay offsets to calculate the overlay compensation term, and the first overlay offset and the second overlay offset are respectively located in the first area and the second area of the wafer, the overlay compensation term includes the influence of the distance on it, so that the overlay compensation value (offset value) with the overlay compensation term is improved in accuracy by considering the position of the overlay mark on the wafer. The overlay compensation value can be used for machine calibration and can be used to improve the machine calibration process when the wafer is reworked, so that it better meets the device alignment requirements.

The embodiments disclosed below provide many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are only examples and are not intended to be limiting. In addition, the present invention may repeat component symbols and/or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein for descriptive purposes to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a flow chart of a metrology method for stacked measurement of semiconductor process according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of a metrology method for stacked measurement of semiconductor process according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 2 simultaneously, the metrology method for stacked measurement of semiconductor process includes the following process. In step S1, a plurality of overlay marks 101 of a wafer 100 are measured to obtain a plurality of first overlay shifts O1 and a plurality of second overlay shifts O2 respectively located in a first region 102 and a second region 103 of the wafer 100, wherein the second region 103 of the wafer 100 surrounds the first region 102, and each of the overlay marks 101 has a distance D from a center point 104 of the wafer 100. Next, in step S2, when any of the distances D has a relationship with an overlay complement term T, N of the first overlay shifts O1 and M of the second overlay shifts O2 are extracted according to the relationship, wherein N and M are positive integers. Then, in step S3, the stack pair offset O1 of N and the second stack pair offset O2 of M are used to calculate the stack pair compensation term T, so that the stack pair compensation term T includes the influence of the distance D. In some embodiments, the stack pair mark 101 can be located on the dicing street 105 of the wafer 100, or in the die area 106 of the wafer 100. The overlay mark 101 may include a box-in-box (BIB) mark, an advanced imaging metrology (AIM) mark, an advanced imaging metrology in-die (AIMid) mark, and other in-die marks for critical dimension scanning electron microscopy (CD-SEM) having different patterns, but the present disclosure is not limited thereto.

Specifically, since the measurement method of the overlay measurement includes extracting N of the first overlay offset O1 and M of the second overlay offset O2 according to the relationship, and using them to calculate the overlay compensation item T, and the first overlay offset O1 and the second overlay offset O2 are respectively located in the first area 102 and the second area 103 of the wafer 100, the overlay compensation item T includes the influence of the distance D thereon, so that the overlay compensation value (offset value) having the overlay compensation item T and which can be used for machine calibration is improved in accuracy by considering the position of the overlay mark 101 on the wafer 100, and accordingly, the machine calibration process using the overlay compensation value when the wafer 100 is reworked can be improved to make it more in line with the component alignment requirements.

In some embodiments, the first region 102 of the wafer 100 may have a first radius R1, and the second region 103 away from the edge of the first region 102 may have a second radius R2. The center point 104 of the wafer 100 may be located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101 may be located in the xy coordinate system, so the distance D may be expressed using the x coordinate and the y coordinate: In the xy coordinate system, if the relationship between any of the distances D and the stack complement term T (that is, the relationship between the x-coordinate and the y-coordinate and the stack complement term T) is that the stack complement term T is proportional to one of the x-coordinate and the y-coordinate to the power of a and to the other of the x-coordinate and the y-coordinate to the power of b, and a is greater than or equal to b, then the ratio N/M is equal to the ratio R1 ^a+1 /(R2 ^a+1 -R1 ^a+1 ), where a and b are positive integers.

In this embodiment, the ratio of the first radius R1/the second radius R2 may be 1/2. For example, if the stack complement term T is proportional to the square of the x-coordinate Tx20 (ie, Tx20 x ² , a=2, b=0), then the ratio of N/M is That is, in step S2, the distance D represented by the x-coordinate and the y-coordinate is related to the stack pair complement item T which is Tx20, and the N of the first stack pair offset O1 and the M of the second stack pair offset O2 can be extracted according to the aforementioned ratio of N/M (that is, 1/7). In this way, when the stack pair complement item T which is Tx20 is calculated using the N of the first stack pair offset O1 and the M of the second stack pair offset O2, the stack pair complement item T can include the influence of the distance D on it.

In addition, the metrology method for stack pair measurement of semiconductor process may further include extracting N of the first stack pair offset O1 and M of the second stack pair offset O2 when any of the distances D is unrelated to the stack pair compensation term T, wherein N and M are equal.

In some embodiments, when measuring the stack mark 101 of the wafer 100, a plurality of boundary stack offsets OB in the boundary region 107 contacting the edge of the wafer 100 may be obtained. Then, when N first stack offsets O1 are extracted and M second stack offsets O2 are extracted according to the relationship between any one of the distances D and the stack complement term T, the boundary stack offset OB is not extracted. Generally speaking, the overlap marks 101, wirings and other components in the area close to the edge of the wafer 100 may have more defects and may be less flat due to the limitations of each process stage. Therefore, not extracting the boundary overlap offset OB can avoid the defects and flatness in the boundary area 107 of the wafer 100 affecting the calculation of the subsequent overlap compensation term T, thereby improving the accuracy of the overlap compensation term T.

In addition, the metrology method for overlay measurement in semiconductor manufacturing process may further include obtaining a plurality of third overlay offsets O3 located in a third region 108 of the wafer 100 surrounding the second region 103 when measuring the overlay mark 101 of the wafer 100. In the present embodiment, the third region 108 of the wafer 100 may be located between the second region 103 and the boundary region 107. For example, the first radius R1 of the first region 102 of the wafer 100 may be 45 mm, the second radius R2 of the second region 103 may be 90 mm, the third radius R3 of the third region 108 may be 135 mm, and the fourth radius R4 of the boundary region 107 may be 150 mm. The fourth radius R4 may also be the radius of the wafer 100, but the present disclosure is not limited thereto.

Then, in some embodiments, when extracting the N of the first stack pair offset O1 and the M of the second stack pair offset O2 according to the relationship between any one of the distances D and the stack pair complement term T, the P of the third stack pair offset O3 can be extracted according to the aforementioned relationship. In this embodiment, the ratio of the first radius R1/the second radius R2 can be 1/2, and the ratio of the second radius R2/the third radius R3 can be 2/3. For example, if the stack pair complement term T is proportional to the square of the x coordinate Tx20 (i.e., Tx20 x ² , a=2, b=0), then the ratio of N/M is , and the ratio of (N+M)/P is That is, in step S2, the distance D represented by the x-coordinate and the y-coordinate is related to the stack pair complement term T which is Tx20, and the N of the first stack pair offset O1, the M of the second stack pair offset O2, and the P of the third stack pair offset O3 can be extracted according to the ratio of N/M and the ratio of (N+M)/P.

In addition, referring to FIG. 2 , each of the first stack pair offset O1, the second stack pair offset O2, the third stack pair offset O3 and the boundary stack pair offset OB may have an X offset (i.e., O1x, O2x, O3x and OBx) and a Y offset (i.e., O1y, O2y, O3y and OBy). When located at the position of one of the stack pair markers 101 in the xy coordinate system, the X offset and the Y offset represent the offset of the pattern of the current layer and the pattern of the previous layer along the x-axis and the y-axis, respectively.

It should be understood that the components and methods that have been described will not be repeated, and are described first. In the following description, the relationship between different stack complement terms T and the xy coordinate axis will be explained.

FIG. 3A to FIG. 3G show the relationship between some of the overlay complement terms T and the xy coordinate axis of FIG. 1. Referring to FIG. 3A, the center point 104 of the wafer 100 is located at the origin of the xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system, so the distance D can be expressed using the x coordinate and the y coordinate: The stack complement term T is proportional to the square of the x-coordinate Tx20 (that is, Tx20 x ² ). Since Tx20 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each stack marker 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx20 and the xy coordinate axis.

Referring to FIG. 3B , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 3B differs from FIG. 3A in that the overlay complement term T is proportional to the x coordinate multiplied by the y coordinate Tx11 (i.e., Tx11 Since Tx11 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each stack complement mark 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx11 and the xy coordinate axis.

Referring to FIG. 3C , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 3C differs from FIG. 3A in that the overlay complement term T is proportional to the square of the y coordinate Tx02 (i.e., Tx02 y ² ). Since Tx02 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each stack marker 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx02 and the xy coordinate axis.

Referring to FIG. 3D , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 3D differs from FIG. 3A in that the overlay complement term T is proportional to the cube of the x coordinate Tx30 (i.e., Tx30 x ³ ). Since Tx30 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each stack mark 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx30 and the xy coordinate axis.

Referring to FIG. 3E , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 3E differs from FIG. 3A in that the overlay complement term T is proportional to the square of the x coordinate multiplied by the y coordinate Tx21 (i.e., Tx21 Since Tx21 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. ² ), it is assumed that the X offset at each stack complement mark 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx21 and the xy coordinate axis.

Referring to FIG. 3F , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the stacked marks 101a is located in the xy coordinate system. FIG. 3F differs from FIG. 3A in that the stacked complement term T is proportional to the x coordinate multiplied by the square of the y coordinate Tx12 (i.e., Tx12 Since Tx12 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. ² ), it is assumed that the X offset at each stack mark 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx12 and the xy coordinate axis.

Referring to FIG. 3G , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 3G differs from FIG. 3A in that the overlay complement term T is proportional to the cube of the y coordinate Tx03 (i.e., Tx03 y ³ ). Since Tx03 is a stack complement term T applicable only to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each stack marker 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stack complement term T as Tx03 and the xy coordinate axis.

FIG. 4A to FIG. 4G show the relationship between other overlapping complement items T and xy coordinate axes of FIG. 1. Referring to FIG. 4A, the center point 104 of the wafer 100 is located at the origin of the xy coordinate system having x coordinates and y coordinates. Each of the overlapping marks 101a is located in the xy coordinate system, so the distance D can be expressed using the x coordinate and the y coordinate: The stack complement term T is proportional to the square of the y coordinate Ty20 (that is, Ty20 y ² ). Since Ty20 is an overlay compensation term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. 2 ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty20 and the xy coordinate axis.

Referring to FIG. 4B , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 4B differs from FIG. 4A in that the overlay complement term T is proportional to the x coordinate multiplied by the y coordinate Ty11 (i.e., Ty11 Since Ty11 is an overlay compensation term T applicable only to the Y offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty11 and the xy coordinate axis.

Referring to FIG. 4C , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 4C differs from FIG. 4A in that the overlay complement term T is proportional to the square of the x coordinate Ty02 (i.e., Ty02 x ² ). Since Ty02 is an overlay compensation term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. 2 ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty02 and the xy coordinate axis.

Referring to FIG. 4D , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 4D differs from FIG. 4A in that the overlay complement term T is proportional to the cube of the y coordinate Ty30 (i.e., Ty30 y ³ ). Since Ty30 is an overlay complement term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. 2 ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay complement term T as Ty30 and the xy coordinate axis.

Referring to FIG. 4E , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the stacked marks 101a is located in the xy coordinate system. FIG. 4E differs from FIG. 4A in that the stacked complement term T is proportional to the x coordinate multiplied by the square of the y coordinate Ty21 (i.e., Ty21 Since Ty21 is an overlay compensation term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. ² ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty21 and the xy coordinate axis.

Referring to FIG. 4F , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 4F differs from FIG. 4A in that the overlay complement term T is proportional to the x coordinate squared multiplied by the y coordinate Ty12 (i.e., Ty12 Since Ty12 is an overlay compensation term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. ² ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty12 and the xy coordinate axis.

Referring to FIG. 4G , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, and each of the overlay marks 101a is located in the xy coordinate system. FIG. 4G differs from FIG. 4A in that the overlay complement term T is proportional to the cube of the x coordinate Ty03 (i.e., Ty03 x ³ ). Since Ty03 is an overlay compensation term T applicable only to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. 2 ), it is assumed that the Y offset at each overlay marker 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the overlay compensation term T as Ty03 and the xy coordinate axis.

FIG. 5A and FIG. 5B show the relationship between some other overlapping complement items and the xy coordinate axis of FIG. 1. Referring to FIG. 5A, the center point 104 of the wafer 100 is located at the origin of the xy coordinate system having the x coordinate and the y coordinate, and each of the overlapping marks 101a is located in the xy coordinate system, so any distance D can be expressed using the x coordinate and the y coordinate: FIG. 5A is different from FIGS. 3A to 3G in that the stacking complement term T is an interlayer offset XSHIFT that is unrelated to any of the distances D. Since the interlayer offset XSHIFT is a stacking complement term T that is only applicable to the X offset (i.e., the X offsets O1x, O2x, O3x, and OBx in FIG. 2 ), it is assumed that the X offset at each of the stacking markers 101a is a fixed value toward the -x coordinate axis to illustrate the relationship between the stacking complement term T, which is the interlayer offset XSHIFT, and the xy coordinate axis.

Referring to FIG. 5B , the center point 104 of the wafer 100 is located at the origin of an xy coordinate system having an x coordinate and a y coordinate. Each of the overlapping marks 101a is located in the xy coordinate system, so any distance D can be expressed using the x coordinate and the y coordinate: . FIG. 5B differs from FIGS. 4A to 4G in that the stacking compensation term T is an inter-layer offset YSHIFT that is unrelated to any of the distances D. Since the inter-layer offset YSHIFT is an stacking compensation term T that is only applicable to the Y offset (i.e., the Y offsets O1y, O2y, O3y, and OBy in FIG. 2), it is assumed that the Y offset at each of the stacking marks 101a is a fixed value toward the -y coordinate axis to illustrate the relationship between the stacking compensation term T, which is the inter-layer offset YSHIFT, and the xy coordinate axis.

Accordingly, referring to FIG. 1 and FIG. 2 simultaneously, in some implementations, the stack pair complement T is calculated using the N first stack pair offsets O1 and the M second stack pair offsets O2. The stack pair complement T can be calculated using the X offset O1x, the Y offset O1y, or a combination thereof of the N first stack pair offsets O1 and the X offset O2x, the Y offset O2y, or a combination thereof of the M second stack pair offsets O2 according to the stack pair complement T. For example, when a stack pair complement T as Tx20 (see FIG. 3A ) is calculated using the N first stack pair offsets O1 and the M second stack pair offsets O2, the stack pair complement T can be calculated using the X offset O1x of the N first stack pair offsets O1 and the X offset O2x of the M second stack pair offsets O2 according to the stack pair complement T as Tx20. That is, in the present embodiment, the stack pair complement T is calculated using the N first stack pair offsets O1 and the M second stack pair offsets O2 along the same direction.

In summary, in the present embodiment, the ratio of the first radius R1 of the first region 102 to the second radius R2 of the second region 103 of the wafer 100 is 1/2, and the ratio of the second radius R2 of the second region 103 to the third radius R3 of the third region 108 is 2/3. According to different stack pair complement terms T, the X offsets (i.e., X offsets O1x, O2x, O3x, and OBx), the Y offsets (i.e., Y offsets O1y, O2y, O3y, and OBy) or their combinations of the N first stack pair offsets O1, the M second stack pair offsets O2, and the P third stack pair offsets O3 are extracted, as shown in Table 1 below. Table 1 Overlap offset overlap complement O1x O2x O3x O1y O2y O3y M N P M N P XSHIFT 1 1 1 0 0 0 YSHIFT 0 0 0 1 1 1 Tx20 1 7 19 0 0 0 Ty20 0 0 0 1 7 19 Tx11 1 3 5 0 0 0 Ty11 0 0 0 1 3 5 Tx02 1 7 19 0 0 0 Ty02 0 0 0 1 7 19 Tx30 1 15 65 0 0 0 Ty30 0 0 0 1 15 65 Tx21 1 7 19 0 0 0 Ty21 0 0 0 1 7 19 Tx12 1 7 19 0 0 0 Ty12 0 0 0 1 7 19 Tx03 1 15 65 0 0 0 Ty03 0 0 0 1 15 65 WAFROTX 1 3 5 1 3 5 WAFERORTHO 1 3 5 1 3 5 WAFMAGX 1 3 5 0 0 0 WAFMAGY 0 0 0 1 3 5

In addition, referring to FIG. 1 and FIG. 2 at the same time, in step S1, the overlay mark 101 of the wafer 100 can be measured using an image-based overlay (IBO) measurement method, an optical diffraction-based overlay (DBO) measurement method, or an in-die overlay measurement method using a critical dimension scanning electron microscope (CD-SEM), but the present disclosure is not limited thereto.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present disclosure.

100: wafer 101,101a: stack mark 102: first zone 103: second zone 104: center point 105: cutting path 106: die zone 107: boundary zone 108: third zone D: distance O1,O2,O3,OB: stack offset O1x,O2x,O3x,OBx: X offset O1y,O2y,O3y,OBy: Y offset R1,R2,R3,R4: radius S1,S2,S3: step T: stack complement XSHIFT,YSHIFT: layer offset

The disclosure is best understood from the following embodiments when read in conjunction with the accompanying illustrations. Note that various features are not drawn to scale in accordance with standard practice in the industry. In fact, the sizes of various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a flow chart of a metrology method for overlay measurement of semiconductor processes according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of a metrology method for overlay measurement of semiconductor processes according to an embodiment of the disclosure. FIGS. 3A to 3G are diagrams showing the relationship between some of the overlay compensation items of FIG. 1 and the xy coordinate axis. FIGS. 4A to 4G are diagrams showing the relationship between other overlay compensation items of FIG. 1 and the xy coordinate axis. Figures 5A and 5B show the relationship between some of the overlapping complement items in Figure 1 and the xy coordinate axes.

S1: Steps

S2: Step

S3: Step

Claims (10)

A metrology method for stacking measurement of semiconductor process, comprising: Measuring a plurality of stacking pair marks of a wafer to obtain a plurality of first stacking pair offsets and a plurality of second stacking pair offsets respectively located in a first area and a second area of the wafer, wherein the second area of the wafer surrounds the first area, and each of the stacking pair marks has a distance from a center point of the wafer; When any of the distances has a relationship with a stacking pair complement term, extracting N of the first stacking pair offsets and M of the second stacking pair offsets according to the relationship, wherein N and M are positive integers; and The stack pair compensation term is calculated using the N of the first stack pair offsets and the M of the second stack pair offsets, so that the stack pair compensation term includes the effect of the distance on it. A metrology method for overlay measurement of semiconductor process as described in claim 1, wherein the first area of the wafer has a first radius, the second area away from the edge of the first area has a second radius, the center point of the wafer is located at the origin of an xy coordinate system having an x coordinate and a y coordinate, each of the overlay marks is located in the xy coordinate system, the relationship is that in the xy coordinate system the overlay complement term is proportional to the a power of one of the x coordinate and the y coordinate and proportional to the b power of the other of the x coordinate and the y coordinate, a and b are positive integers and a is greater than or equal to b, and the ratio of N/M is equal to the ratio of R1 ^a+1 /(R2 ^a+1 -R1 ^a+1 ), R1 is the first radius, and R2 is the second radius. The metrology method for stack pair measurement of semiconductor process as described in claim 1 further includes: When any of the distances is unrelated to the stack pair compensation term, extracting N of the first stack pair offsets and M of the second stack pair offsets, where N and M are equal. A metrology method for overlay measurement of a semiconductor process as described in claim 3, wherein the overlay compensation term includes an inter-layer offset along an x-direction or an inter-layer offset along a y-direction, wherein the x-direction is perpendicular to the y-direction. The metrology method for overlay measurement of semiconductor process as described in claim 1 further includes: When measuring the overlay marks of the wafer, a plurality of boundary overlay offsets in a boundary area contacting the edge of the wafer are obtained. The metrology method for stack pair measurement of semiconductor process as described in claim 5 further includes: When extracting the N of the first stack pair offsets and extracting the M of the second stack pair offsets according to the relationship, the boundary stack pair offsets are not extracted. The metrology method for overlay measurement in semiconductor process as described in claim 1 further includes: When measuring the overlay marks of the wafer, a plurality of third overlay offsets located in a third area of the wafer surrounding the second area are obtained. The metrology method for stacking pair measurement of semiconductor process as described in claim 7 further includes: When extracting the N of the first stacking pair offsets and the M of the second stacking pair offsets according to the relationship, the third stacking pair offsets are extracted according to the relationship at the same time. The metrology method for stack pair measurement of a semiconductor process as claimed in claim 1, wherein the stack pair compensation term is calculated using the N first stack pair offsets and the M second stack pair offsets by using an X offset, a Y offset, or a combination thereof of the N first stack pair offsets and an X offset, a Y offset, or a combination thereof of the M second stack pair offsets according to the stack pair compensation term. A metrology method for stack-pair measurement in semiconductor manufacturing processes as described in claim 1, wherein the N offsets of the first stack-pairs and the M offsets of the second stack-pairs are in the same direction.

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