TWI801261B - Power supply device with fast discharge function - Google Patents

Abstract

A power supply device with a fast discharge function includes a bridge rectifier, a boost inductor, a power switch element, a detection and control circuit, a first output stage circuit, a voltage divider circuit, a switching circuit, a discharge circuit, a transformer, a resonant capacitor, and a second output stage circuit. The detection and control circuit detects whether any input current flows through the bridge rectifier, so as to generate a first PWM (Pulse Width Modulation) voltage, a first control voltage, a second control voltage, and a logic voltage. The discharge circuit selectively performs discharging operations on the first output stage circuit and the switching circuit according to the second control voltage and the logic voltage.

Description

Fast-discharge power supply

This invention relates to a power supply, and more particularly to a power supply capable of rapid discharge.

In traditional power supplies, the output capacitors typically have large capacitance values. Even after removing one of the external input power sources, these output capacitors can still provide power for a period of time, which can easily cause the corresponding system to misjudge and perform incorrect mode switching. In view of this, it is necessary to propose a completely new solution to overcome the shortcomings of previous technologies.

In a preferred embodiment, the present invention provides a fast-discharge power supply, comprising: a bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; a boost inductor that receives the rectified potential; a power switch that selectively couples the boost inductor to a ground potential based on a first pulse width modulation potential; a detection and control circuit that detects whether any input current flows through the bridge rectifier and generates the first pulse width modulation potential, a first control potential, a second control potential, and a logical potential accordingly; and a first output stage circuit coupled to the boost inductor, wherein the first output stage circuit selectively generates an intermediate voltage based on the first control potential. The circuit includes: a voltage divider circuit that generates a voltage divider potential based on the intermediate potential; a switching circuit that is powered by the voltage divider potential, wherein the switching circuit generates the switching potential based on the intermediate potential; a discharge circuit that selectively performs discharge operations on the first output stage circuit and the switching circuit based on the second control potential and the logical potential; a transformer including a main coil, a first auxiliary coil, and a second auxiliary coil, wherein the transformer has a built-in leakage inductor and a magnetizing inductor, and the main coil receives the switching potential through the leakage inductor; a resonant capacitor coupled to the magnetizing inductor; and a second output stage circuit coupled to the first auxiliary coil and the second auxiliary coil, and generating an output potential.

To make the purpose, features and advantages of this invention clearer and easier to understand, specific embodiments of this invention are given below, and detailed explanations are provided in conjunction with the accompanying drawings.

Certain terms are used in this specification and the scope of the patent application to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and the scope of the patent application do not distinguish components by name, but by functional differences. The terms "comprising" and "including" used throughout this specification and the scope of the patent application are open-ended and should be interpreted as "including but not limited to". The term "generally" means that, within an acceptable range of error, those skilled in the art can solve the described technical problem and achieve the described basic technical effect within a certain range of error. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

Figure 1 is a schematic diagram showing a power supply 100 according to an embodiment of the present invention. For example, the power supply 100 can be applied to a desktop computer, a laptop computer, or an all-in-one computer. As shown in Figure 1, the power supply 100 includes: a bridge rectifier 110, a boost inductor 100, a power switch 120, a detection and control circuit 130, a first output stage circuit 140, a voltage divider circuit 150, a switching circuit 160, a discharge circuit 170, a transformer 180, a resonant capacitor CR, and a second output stage circuit 190. It should be noted that, although not shown in Figure 1, the power supply 100 may also include other components, such as a voltage regulator or (and) a negative feedback circuit.

The bridge rectifier 110 generates a rectified potential VR based on a first input potential VIN1 and a second input potential VIN2, wherein an AC voltage with arbitrary frequency and amplitude can be formed between the first input potential VIN1 and the second input potential VIN2. For example, the frequency of the AC voltage can be approximately 50Hz or 60Hz, and the root mean square value of the AC voltage can be approximately from 90V to 264V, but is not limited thereto. The boost inductor LU receives the rectified potential VR. The power switch 120 selectively couples the boost inductor LU to a ground potential VSS (e.g., 0V) based on a first pulse width modulation potential VM1. For example, if the first pulse width modulation potential VM1 is a high logical level (i.e., logical "1"), then the power switch 120 can couple the boost inductor LU to the ground potential VSS (i.e., the power switch 120 can be approximated as a short-circuit path); conversely, if the first pulse width modulation potential VM1 is a low logical level (i.e., logical "0"), then the power switch 120 will not couple the boost inductor LU to the ground potential VSS (i.e., the power switch 120 can be approximated as an open-circuit path). The detection and control circuit 130 can detect whether any input current IIN passes through the bridge rectifier 110, and can generate a first pulse width modulation potential VM1, a first control potential VC1, a second control potential VC2, and a logical potential VG accordingly. The first output stage circuit 140 is coupled to the boost inductor LU, wherein the first output stage circuit 140 can selectively generate an intermediate potential VE based on the first control potential VC1. The voltage divider circuit 150 can generate a voltage divider potential VD based on the intermediate potential VE. The switching circuit 160 can be powered by the voltage divider potential VD, wherein the switching circuit 160 can further generate a switching potential VW based on the intermediate potential VE. The discharge circuit 170 can selectively perform discharge operations on the first output stage circuit 140 and the switching circuit 160 according to the second control potential VC2 and the logical potential VG. The transformer 180 includes a main coil 181, a first auxiliary coil 182, and a second auxiliary coil 183. The transformer 180 may also have a built-in leakage inductor LR and a magnetizing inductor LM, wherein the leakage inductor LR, the magnetizing inductor LM, and the main coil 181 can all be located on the same side of the transformer 180, while the first auxiliary coil 182 and the second auxiliary coil 183 can both be located on the opposite side of the transformer 180. The main coil 181 receives the switching potential VW via the leakage inductor LR, while the first auxiliary coil 182 and the second auxiliary coil 183 respond to the switching potential VW to perform operation. The resonant capacitor CR is coupled to the magnetizing inductor LM. The second output stage circuit 190 is coupled to the first auxiliary coil 182 and the second auxiliary coil 183 and can generate an output potential VOUT. For example, the output potential VOUT can be a DC potential with a potential level between 18V and 20V, but is not limited to this. In this design, the power supply 100 can determine whether its external power supply has been removed by analyzing the input current IIN, and then selectively perform the corresponding fast discharge operation, thereby effectively improving its overall reliability and stability.

The following embodiments will describe the detailed structure and operation of the power supply 100. It must be understood that these figures and descriptions are merely illustrative and are not intended to limit the scope of the invention.

Figure 2 shows a circuit diagram of a power supply 200 according to an embodiment of the present invention. In the embodiment of Figure 2, the power supply 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes: a bridge rectifier 210, a boost inductor LU, a power switch 220, a detection and control circuit 230, a first output stage circuit 240, a voltage divider circuit 250, a switching circuit 260, a discharge circuit 270, a transformer 280, a resonant capacitor CR, and a second output stage circuit 290. The first input node NIN1 and the second output node NIN2 of the power supply 200 can receive a first input potential VIN1 and a second input potential VIN2 respectively from an external input power source (not shown), while the output node NOUT of the power supply 200 can be used to output an output potential VOUT to an electronic device (not shown).

The bridge rectifier 210 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The first diode D1 has an anode and a cathode, wherein the anode of the first diode D1 is coupled to a first input node NIN1, and the cathode of the first diode D1 is coupled to a first node N1 to output a rectified potential VR. The second diode D2 has an anode and a cathode, wherein the anode of the second diode D2 is coupled to a second input node NIN2, and the cathode of the second diode D2 is coupled to a first node N1. The third diode D3 has an anode and a cathode, wherein the anode of the third diode D3 is coupled to a second node N2, and the cathode of the third diode D3 is coupled to a first input node NIN1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to a third node N3, and the cathode of the fourth diode D4 is coupled to a second input node NIN2.

The boost inductor LU has a first terminal and a second terminal, wherein the first terminal of the boost inductor LU is coupled to a first node N1 to receive a rectified potential VR, and the second terminal of the boost inductor LU is coupled to a fourth node N4.

The power switch 220 includes a first transistor M1. For example, the first transistor M1 may be an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET). The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the first transistor M1 is used to receive a first pulse width modulation potential VM1, the first terminal of the first transistor M1 is coupled to a ground potential VSS, and the second terminal of the first transistor M1 is coupled to a fourth node N4.

The detection and control circuit 230 includes a first resistor R1, a second resistor R2, a first error amplifier (EA) 232, a second error amplifier 234, an AND gate 236, and a first pulse width modulation integrated circuit (PWM IC) 238. The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to a second node N2 to output a first potential V1, and the second terminal of the first resistor R1 is coupled to a ground potential VSS. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to a third node N3 to output a second potential V2, and the second terminal of the second resistor R2 is coupled to a ground potential VSS. In some embodiments, both the first resistor R1 and the second resistor R2 have extremely small resistance values (e.g., less than 5 ohms). The first error amplifier 232 can compare the first potential V1 with the ground potential VSS to generate a first comparison potential VB1. For example, if the first potential V1 equals the ground potential VSS (i.e., ...), If the first error amplifier 232 generates a first comparison potential VB1 with a high logical level, then the first error amplifier 232 can generate a first comparison potential VB1 with a high logical level; conversely, if the first potential V1 is not equal to the ground potential VSS (i.e., ...), If the first error amplifier 232 generates a first comparison potential VB1 with a low logical level, then the second error amplifier 234 can compare the second potential V2 with the ground potential VSS to generate a second comparison potential VB2. For example, if the second potential V2 equals the ground potential VSS (i.e., ...), If the second error amplifier 234 generates a second comparison potential VB2 with a high logical level, then the second error amplifier 234 can generate a second comparison potential VB2 with a high logical level; conversely, if the second potential V2 is not equal to the ground potential VSS (i.e., ...), If the first error amplifier 232 and the second error amplifier 234 are used, the second error amplifier 234 can generate a second comparison potential VB2 with a low logical level. In some embodiments, the sampling period of the first error amplifier 232 and the second error amplifier 234 is at least 16.67 ms to correspond to a typical mains operating frequency of 60 Hz. The gate 236 has a first input, a second input, and an output, wherein the first input of the gate 236 is used to receive the first comparison potential VB1, the second input of the gate 236 is used to receive the second comparison potential VB2, and the output of the gate 236 is used to output a logical potential VG. For example, gate 236 will only generate a logical potential VG with a high logical level if both the first comparison potential VB1 and the second comparison potential VB2 are at high logical levels; otherwise, gate 236 will generate a logical potential VG with a low logical level. The first pulse width modulation integrated circuit 238 can generate a first pulse width modulation potential VM1, a first control potential VC1, and a second control potential VC2 based on the logical potential VG. Its operating principle will be explained in detail in subsequent embodiments.

The output stage circuit 240 includes a fifth diode D5, a first capacitor C1, and a second transistor M2. The fifth diode D5 has an anode and a cathode, wherein the anode of the fifth diode D5 is coupled to a fourth node N4, and the cathode of the fifth diode D5 is coupled to a fifth node N5. The first capacitor C1 has a first terminal and a second terminal, wherein the first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to ground potential VSS. The second transistor M2 may be an N-type metal-oxide-semiconductor field-effect transistor. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the second transistor M2 is used to receive a first control potential VC1. The first terminal of the second transistor M2 is coupled to a sixth node N6 to selectively output an intermediate potential VE. The second terminal of the second transistor M2 is coupled to a fifth node N5.

The voltage divider circuit 250 includes a third resistor R3 and a fourth resistor R4. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the sixth node N6 to receive the intermediate potential VE, and the second terminal of the third resistor R3 is coupled to the seventh node N7 to output a voltage divider potential VD. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the seventh node N7, and the second terminal of the fourth resistor R4 is coupled to the ground potential VSS.

The switching circuit 260 includes a second pulse width modulation (PWM) integrated circuit 268, a third transistor M3, and a fourth transistor M4. The second PWM integrated circuit 268 can be powered by a voltage divider potential VD. For example, if the voltage divider potential VD is at a high logical level, the second PWM integrated circuit 268 can be enabled to generate a second PWM potential VM2 and a third PWM potential VM3; conversely, if the voltage divider potential VD is at a low logical level, the second PWM integrated circuit 268 can be disabled and no PWM potentials will be generated. The second pulse width modulation potential VM2 and the third pulse width modulation potential VM3 can have complementary logical levels. The third transistor M3 and the fourth transistor M4 can each be an N-type metal-oxide-semiconductor field-effect transistor. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the third transistor M3 is used to receive the second pulse width modulation potential VM2. The first terminal of the third transistor M3 is coupled to an eighth node to output the switching potential VW, and the second terminal of the third transistor M3 is coupled to a sixth node N6 to receive the intermediate potential VE. The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fourth transistor M4 is used to receive the third pulse width modulation potential VM3. The first terminal of the fourth transistor M4 is coupled to the ground potential VSS, and the second terminal of the fourth transistor M4 is coupled to the eighth node N8.

The discharge circuit 270 includes a fifth transistor M5, a sixth transistor M6, a fifth resistor R5, and a sixth resistor R6. The fifth transistor M5 and the sixth transistor M6 can each be an N-type metal-oxide-semiconductor field-effect transistor. The fifth transistor M5 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fifth transistor M5 is used to receive a second control potential VC2. The first terminal of the fifth transistor M5 is coupled to a ninth node N9, and the second terminal of the fifth transistor M5 is coupled to the fifth node N5. The fifth resistor R5 has a first terminal and a second terminal. The first terminal of the fifth resistor R5 is coupled to the ninth node N9, and the second terminal of the fifth resistor R5 is coupled to a ground potential VSS. The sixth transistor M6 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the sixth transistor M6 is used to receive a logical potential VG. The first terminal of the sixth transistor M6 is coupled to a tenth node N10, and the second terminal of the sixth transistor M6 is coupled to an eighth node N8. The sixth resistor R6 has a first terminal and a second terminal. The first terminal of the sixth resistor R6 is coupled to the tenth node N10, and the second terminal of the sixth resistor R6 is coupled to a ground potential VSS.

Transformer 280 includes a main coil 281, a first auxiliary coil 282, and a second auxiliary coil 283. Transformer 280 also integrates a leakage inductor LR and a magnetizing inductor LM. The leakage inductor LR and magnetizing inductor LM are inherent components generated during the manufacturing of transformer 280 and are not external independent components. The leakage inductor LR, main coil 281, and magnetizing inductor LM can all be located on the same side of transformer 280 (e.g., the primary side), while the first auxiliary coil 282 and second auxiliary coil 283 can both be located on the opposite side of transformer 280 (e.g., the secondary side, which can be isolated from the primary side). The leakage inductor LR has a first terminal and a second terminal, wherein the first terminal of the leakage inductor LR is coupled to the eighth node N8 to receive the switching potential VW, and the second terminal of the leakage inductor LR is coupled to the eleventh node N11. The main coil 281 has a first terminal and a second terminal, wherein the first terminal of the main coil 281 is coupled to the eleventh node N11, and the second terminal of the main coil 281 is coupled to the twelfth node N12. The magnetizing inductor LM has a first terminal and a second terminal, wherein the first terminal of the magnetizing inductor LM is coupled to the eleventh node N11, and the second terminal of the magnetizing inductor LM is coupled to the twelfth node N12. The resonant capacitor CR has a first terminal and a second terminal, wherein the first terminal of the resonant capacitor CR is coupled to the twelfth node N12, and the second terminal of the resonant capacitor CR is coupled to the ground potential VSS. For example, the leakage inductor LR, the magnetizing inductor LM, and the resonant capacitor CR can together form a resonant tank in the power supply 200. The first sub-coil 282 has a first end and a second end, wherein the first end of the first sub-coil 282 is coupled to a thirteenth node N13, and the second end of the first sub-coil 282 is coupled to a common node NCM. For example, the common node NCM can be considered as another ground potential, which may be the same as or different from the aforementioned ground potential VSS. The second sub-coil 283 has a first end and a second end, wherein the first end of the second sub-coil 283 is coupled to the common node NCM, and the second end of the second sub-coil 283 is coupled to a fourteenth node N14.

The second output stage circuit 290 includes a sixth diode D6, a seventh diode D7, and a second capacitor C2. The sixth diode D6 has an anode and a cathode, wherein the anode of the sixth diode D6 is coupled to the thirteenth node N13, and the cathode of the sixth diode D6 is coupled to the output node NOUT. The seventh diode D7 has an anode and a cathode, wherein the anode of the seventh diode D7 is coupled to the fourteenth node N14, and the cathode of the seventh diode D7 is coupled to the output node NOUT. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal of the second capacitor C2 is coupled to the output node NOUT, and the second terminal of the second capacitor C2 is coupled to the common node NCM.

In some embodiments, the power supply 200 can operate in a normal power supply mode or a power outage mode, and its operating principles can be described as follows.

In normal power supply mode, power supply 200 is coupled to an external input power source, where a non-zero input current flows into bridge rectifier 210. For example, this input current can either form a first current I1 through the first resistor R1 or a second current I2 through the second resistor R2. According to Ohm's law, the first potential V1 is proportional to the first current I1, and the second potential V2 is proportional to the second current I2. Since exactly one of the first current I1 and the second current I2 is zero, one of the first comparison potential VB1 and the second comparison potential VB2 will be a low logical level, while the other will be a high logical level. At this time, the logic potential VG will be at a low logic level to disable the sixth transistor M6. In response to the low logic level logic potential VG, the first pulse width modulation circuit 238 will normally output the first pulse width modulation potential VM1. In addition, the first pulse width modulation circuit 238 will also output a first control potential VC1 with a high logic level to enable the second transistor M2, and output a second control potential VC2 with a low logic level to disable the fifth transistor M5. That is, the first output stage circuit 240 will normally provide power to the second pulse width modulation integrated circuit 268, but the discharge circuit 270 will not perform any discharge operation on the first output stage circuit 240 and the switching circuit 260.

In power-off mode, the aforementioned external input power supply has been removed, so no input current enters the bridge rectifier 210. At this time, both the first current I1 through the first resistor R1 and the second current I2 through the second resistor R2 are equal to 0, and both the first comparison potential VB1 and the second comparison potential VB2 are at high logical levels. Therefore, the logical potential VG will be at a high logical level, enabling the sixth transistor M6. In response to the high logical level logical potential VG, the first pulse width modulation integrated circuit 238 will stop outputting the first pulse width modulation potential VM1. Furthermore, the first pulse width modulation integrated circuit 238 will output a first control potential VC1 with a low logical level to disable the second transistor M2, and output a second control potential VC2 with a high logical level to enable the fifth transistor M5. That is, the first output stage circuit 240 will stop supplying power to the second pulse width modulation integrated circuit 268. The discharge circuit 270 will perform a fast discharge operation on the first capacitor C1 of the first output stage circuit 240. Furthermore, the discharge circuit 270 will also perform another discharge operation on the switching potential VW of the switching circuit 260, so that the aforementioned resonant slot will no longer supply energy to the second capacitor C2 of the second output stage circuit 290.

Figure 3 shows the potential waveform of the output potential VOUT of the power supply 200 according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents the potential level. According to the measurement results in Figure 3, if the external input power supply of the power supply 200 is removed at a specific time point TS, the output potential VOUT stored in the second capacitor C2 will have a duration TH between 8ms and 15ms. After the duration TH expires, the output potential VOUT drops to a low logic level. Compared to the traditional design where the duration is often as long as 60ms or 70ms, the fast discharge design proposed in this invention can significantly shorten the duration TH of the output potential VOUT of the power supply 200.

This invention proposes a novel power supply that effectively shortens the duration of the power supply's output potential, thereby reducing the probability of mode switching errors. Based on actual measurement results, the power supply using the aforementioned design exhibits significantly improved stability and reliability, making it well-suited for various applications.

It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters mentioned above are not limiting conditions of this invention. Designers can adjust these settings according to different needs. The power supply of this invention is not limited to the state illustrated in Figures 1-3. This invention may include only any one or more features of any one or more embodiments of Figures 1-3. In other words, not all features illustrated need to be implemented simultaneously in the power supply of this invention. Although the embodiments of this invention use metal-oxide-semiconductor field-effect transistors as examples, this invention is not limited to this. Those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, without affecting the effect of this invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., are not sequential and are only used to distinguish two different elements with the same name.

Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended patent application.

100, 200: Power Supply 110, 210: Bridge Rectifier 120, 220: Power Switch 130, 230: Detection and Control Circuit 140, 240: First Output Stage Circuit 150, 250: Voltage Divider Circuit 160, 260: Switching Circuit 170, 270: Discharge Circuit 180, 280: Transformer 181, 281: Main Coil 182, 282: First Auxiliary Coil 183, 283: Second Auxiliary Coil 190, 290: Second Output Stage Circuit 232: First Error Amplifier 234: Second Error Amplifier 236: Gate 238: First Pulse Width Modulation Integrated Circuit 268: Second Pulse Width Modulation Integrated Circuit C1: First Capacitor C2: Second Capacitor CR: Resonant Capacitor D1: First Diode D2: Second Diode D3: Third Diode D4: Fourth Diode D5: Fifth Diode D6: Sixth Diode D7: Seventh Diode I1: First Current I2: Second Current IIN: Input Current LM: Magnetizing Inductor LR: Leakage Inductor LU: Boost Inductor M1: First Transistor M2: Second Transistor M3: Third Transistor M4: Fourth Transistor M5: Fifth Transistor M6: Sixth Transistor N1: First Node N2: Second Node N3: Third Node N4: Fourth Node N5: Fifth Node N6: Sixth Node N7: Seventh Node N8: Eighth Node N9: Ninth Node N10: Tenth Node N11: Eleventh Node N12: Twelfth Node N13: Thirteenth Node N14: Fourteenth Node NCM: Common Node NIN1: First Input Node NIN2: Second Input Node NOUT: Output Node R1: First Resistor R2: Second Resistor R3: Third Resistor R4: Fourth Resistor R5: Fifth Resistor R6: Sixth Resistor TH: Duration TS: Specific Time Point V1: First Potential V2: Second Potential VB1: First Comparison Potential VB2: Second Comparison Potential VC1: First Control Potential VC2: Second Control Potential VD: Voltage Divider Potential VE: Intermediate Potential VG: Logic Potential VIN1: First Input Potential VIN2: Second Input Potential VM1: First Pulse Width Modulation Potential VM2: Second Pulse Width Modulation Potential VM3: Third Pulse Width Modulation Potential VOUT: Output Potential VR: Rectified Potential VSS: Ground Potential VW: Switching Potential

Figure 1 is a schematic diagram showing a power supply according to an embodiment of the present invention. Figure 2 is a circuit diagram showing the power supply according to an embodiment of the present invention. Figure 3 is a potential waveform diagram showing the output potential of the power supply according to an embodiment of the present invention.

100: Power Supply

110: Bridge rectifier

120: Power Switch

130: Detection and Control Circuits

140: First output stage circuit

150: Voltage divider circuit

160: Switching Circuit

170: Discharge circuit

180: Transformer

181: Main Story Circle

182: First coil

183: Second coil

190: Second output stage circuit

CR: Resonant Capacitor

IIN: Input Current

LM: Magnetizing Inductor

LR: Leakage Inductor

LU: Boost Inductor

VC1: First control potential

VC2: Second control potential

VD: Voltage divider potential

VE: intermediate potential

VG: Logical Potential

VIN1: First input potential

VIN2: Second input potential

VM1: First pulse width modulation potential

VOUT: Output potential

VR: Rectified Potential

VSS: Grounding Potential

VW: Switching potential

Claims (10)

A fast-discharge power supply includes: a bridge rectifier that generates a rectified potential based on a first input potential and a second input potential; a boost inductor that receives the rectified potential; a power switch that selectively couples the boost inductor to a ground potential based on a first pulse width modulation potential; a detection and control circuit that detects whether any input current flows through the bridge rectifier and generates the first pulse width modulation potential, a first control potential, a second control potential, and a logical potential accordingly; a first output stage circuit coupled to the boost inductor, wherein the first output stage circuit selectively generates an intermediate potential based on the first control potential; A voltage divider circuit generates a voltage divider potential based on the intermediate potential; A switching circuit is powered by the voltage divider potential, wherein the switching circuit generates the switching potential based on the intermediate potential; A discharge circuit selectively performs discharge operations on the first output stage circuit and the switching circuit based on the second control potential and the logical potential; A transformer includes a main coil, a first auxiliary coil, and a second auxiliary coil, wherein the transformer integrates a leakage inductor and a magnetizing inductor, and the main coil receives the switching potential via the leakage inductor; A resonant capacitor is coupled to the magnetizing inductor; and A second output stage circuit is coupled to the first and second sub-coils and generates an output potential. The power supply according to claim 1, wherein the bridge rectifier comprises: a first diode having an anode and a cathode, wherein the anode of the first diode is coupled to a first input node to receive the first input potential, and the cathode of the first diode is coupled to a first node to output the rectified potential; a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a second input node to receive the second input potential, and the cathode of the second diode is coupled to the first node; A third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a second node, and the cathode of the third diode is coupled to the first input node; and a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to a third node, and the cathode of the fourth diode is coupled to the second input node; a boost inductor having a first terminal and a second terminal, wherein the first terminal of the boost inductor is coupled to the first node to receive the rectified potential, and the second terminal of the boost inductor is coupled to the fourth node. The power supply according to claim 2, wherein the power switch comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is used to receive the first pulse width modulation potential, the first terminal of the first transistor is coupled to the ground potential, and the second terminal of the first transistor is coupled to the fourth node. The power supply of claim 2, wherein the detection and control circuit comprises: a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the second node to output a first potential, and the second terminal of the first resistor is coupled to the ground potential; a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the third node to output a second potential, and the second terminal of the second resistor is coupled to the ground potential; a first error amplifier comparing the first potential with the ground potential to generate a first comparison potential; a second error amplifier comparing the second potential with the ground potential to generate a second comparison potential; A gate has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the gate is used to receive a first comparison potential, the second input terminal of the gate is used to receive a second comparison potential, and the output terminal of the gate is used to output a logical potential; and a first pulse width modulation integrated circuit generates the first pulse width modulation potential, the first control potential, and the second control potential based on the logical potential. The power supply of claim 2, wherein the first output stage circuit comprises: a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the fourth node, and the cathode of the fifth diode is coupled to a fifth node; a first capacitor having a first terminal and a second terminal, wherein the first terminal of the first capacitor is coupled to the fifth node, and the second terminal of the first capacitor is coupled to the ground potential; and a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is used to receive the first control potential, the first terminal of the second transistor is coupled to a sixth node to selectively output the intermediate potential, and the second terminal of the second transistor is coupled to the fifth node. The power supply of claim 5, wherein the voltage divider circuit comprises: a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the sixth node to receive the intermediate potential, and the second terminal of the third resistor is coupled to a seventh node to output the voltage divider potential; and a fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the seventh node, and the second terminal of the fourth resistor is coupled to the ground potential. The power supply of claim 5, wherein the switching circuit comprises: a second pulse width modulation (PWM) integrated circuit, powered by the voltage divider potential, wherein the second PWM integrated circuit further generates a second PWM potential and a third PWM potential; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is used to receive the second PWM potential, the first terminal of the third transistor is coupled to an eighth node to output the switching potential, and the second terminal of the third transistor is coupled to the sixth node to receive the intermediate potential; and A fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is used to receive the third pulse width modulation potential, the first terminal of the fourth transistor is coupled to the ground potential, and the second terminal of the fourth transistor is coupled to the eighth node. The power supply of claim 7, wherein the discharge circuit comprises: a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is used to receive the second control potential, the first terminal of the fifth transistor is coupled to a ninth node, and the second terminal of the fifth transistor is coupled to the fifth node; a fifth resistor having a first terminal and a second terminal, wherein the first terminal of the fifth resistor is coupled to the ninth node, and the second terminal of the fifth resistor is coupled to the ground potential; a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is used to receive the logical potential, the first terminal of the sixth transistor is coupled to a tenth node, and the second terminal of the sixth transistor is coupled to the eighth node; and A sixth resistor has a first terminal and a second terminal, wherein the first terminal of the sixth resistor is coupled to the tenth node, and the second terminal of the sixth resistor is coupled to the ground potential. As in the power supply of claim 8, wherein the leakage inductor has a first terminal and a second terminal, the first terminal of the leakage inductor being coupled to the eighth node to receive the switching potential, and the second terminal of the leakage inductor being coupled to an eleventh node; the main coil has a first terminal and a second terminal, the first terminal of the main coil being coupled to the eleventh node, and the second terminal of the main coil being coupled to a twelfth node; the magnetizing inductor has a first terminal and a second terminal, the first terminal of the magnetizing inductor being coupled to the eleventh node, and the second terminal of the magnetizing inductor being coupled to... The twelfth node, the resonant capacitor has a first end and a second end, the first end of the resonant capacitor is coupled to the twelfth node, the second end of the resonant capacitor is coupled to the ground potential, the first sub-coil has a first end and a second end, the first end of the first sub-coil is coupled to a thirteenth node, the second end of the first sub-coil is coupled to a common node, the second sub-coil has a first end and a second end, the first end of the second sub-coil is coupled to the common node, and the second end of the second sub-coil is coupled to a fourteenth node. The power supply of claim 9, wherein the second output stage circuit comprises: a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the thirteenth node, and the cathode of the sixth diode is coupled to an output node to output the output potential; a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the fourteenth node, and the cathode of the seventh diode is coupled to the output node; and a second capacitor having a first terminal and a second terminal, wherein the first terminal of the second capacitor is coupled to the output node, and the second terminal of the second capacitor is coupled to the common node.