TWI792288B - memory testing device - Google Patents

Abstract

A memory testing device includes a test substrate, several memory modules to be tested (device under test, DUT), a central processing unit (central processing unit, CPU), a basic input/output system (Basic Input/Output) Output System, BIOS) firmware, a serial presence detect (SPD) chip, and a Hyper server. In this way, the parameters stored in the SPD chip can be changed through the externally connected Hyper server, and various test actions can be provided, such as the setting of voltage offset, the persistence of data storage, etc., and the BIOS firmware will read it after booting The internal parameters of the SPD chip can be partially corrected or fully corrected at least one of several BIOS settings, so as to quickly control a large number of test substrates, save the time for setting one by one, and improve better testing. Convenience and increase test efficiency.

Description

memory testing device

The invention relates to a memory detection device, in particular to a device through an external connection The hyper server of the junction can be used to change the parameters stored in the serial presence detect (SPD) chip, which can provide a variety of test actions. The basic input/output system (Basic Input/Output System, BIOS) firmware will be activated after booting To read the parameters inside the SPD chip, so as to partially correct or fully correct at least one of several BIOS settings, especially to quickly control a large number of test substrates, saving the time to set one by one, thereby improving Better test convenience and increase test efficiency.

A computer may consist of a host system and one or more memory devices attached to the host system body subsystem. The host system may have a central processing unit (CPU) that communicates with one or more memory subsystems to store and/or retrieve data and instructions. The memory subsystem can be a memory module, such as a dual in-line memory module (Dual In-line Memory Module, DIMM), which refers to a series of dynamic random access memory (Dynamic Random Access Memory, DRAM) modules. The DIMM is usually in the form of several to dozens of DRAM chips soldered and installed on a printed circuit board with a circuit, and is used in personal computers, workstations, and servers.

At present, the BIOS of the host system is controlled by the flash memory (Flash memory) on the circuit board. Execution, which records the basic input and output settings of the computer. The circuit board also includes an SPD for controlling the DRAM. In the configuration file of the BIOS program, there are many parameters corresponding to the parameter settings of each hardware and information such as whether the hardware is started or not. In the traditional case, when computers are manufactured, these BIOS program configuration files are mostly pre-burned in the memory, and then rely on the operator to enter the BIOS menu when starting the computer, and manually configure the settings according to the hardware configuration of the current connected host system. Set various parameters in a timely manner, and finally save it as a configuration file, and reload the new BIOS configuration file after rebooting.

However, the above-mentioned manual setting of the BIOS setting file is very difficult for the research and development engineers and manufacturers of the computer. It is a cumbersome and inefficient job for both computer and testers, because it is necessary to check each hardware configured in the host system one by one, which is not conducive to the efficiency of design, manufacturing and testing. In addition, general computer users are also prone to difficulties in setting various parameters in the BIOS menu. If the settings are improper, it may cause abnormal conditions in the host system and fail to boot smoothly. Furthermore, since the prior art stores the configuration files loaded by the BIOS program in the host system during startup, the configuration files are prone to be damaged or improperly tampered with, which will affect the subsequent startup operations of the host system. Therefore, general users cannot meet the needs of users in actual use.

The main purpose of the present invention is to overcome the above-mentioned problems encountered in the prior art and provide Provide a hyper server connected externally to change the parameters stored inside the SPD chip, and provide a variety of test actions. After booting, the BIOS firmware will read the parameters inside the SPD chip, so as to set at least one of several BIOS settings. Partial calibration or full calibration can be performed to quickly control a large number of test substrates, saving the time required to set up one by one, thereby improving the convenience of testing and increasing the efficiency of testing.

For reaching above purpose, the present invention is a kind of memory detection device, and system comprises: a test a test substrate; several memory modules to be tested (device under test, DUT), arranged on the test substrate; a central processing unit, arranged on the test substrate, and electrically connected to the several memory modules to be tested Set; a BIOS firmware, arranged on the test substrate, and electrically connected to the central processing unit, configured to provide the test substrate to screen several memory modules to be tested installed thereon; an SPD The chip is arranged on the test substrate and is electrically connected to the BIOS firmware and the several memory modules to be tested. There are several parameters stored inside it, including the main set value, extended set value, and The BIOS command set can be used for the BIOS firmware to read these parameters from the SPD chip; and a Hyper server is externally connected to the SPD chip of the test substrate for at least One of the BIOS command sets and setting values are written into the SPD chip, so that when the structured BIOS firmware starts and reads the BIOS command set from the SPD chip, the several BIOSes are directly changed based on the BIOS command set At least one of the settings will take effect at the next boot.

In the above-mentioned embodiments of the present invention, each memory module to be tested is a DIMM, and the DIMM It is used to set at least one memory chip.

In the above embodiments of the present invention, the memory chip is a DRAM.

Please refer to "Fig. 1", which is a schematic block diagram of the present invention. As shown in the picture: this The invention is a memory testing device 100, which includes a test substrate 1, several memory modules to be tested (device under test, DUT) 2, a central processing unit (CPU) 3, a basic input/ The output system (Basic Input/Output System, BIOS) firmware 4 , a serial presence detection (serial presence detect, SPD) chip 5 , and a Hyper server 6 are formed.

The aforementioned memory module under test (device under test, DUT) 2 is set in on the test substrate 1; wherein, each memory module 2 to be tested can be a dual in-line memory module (Dual In-line Memory Module, DIMM), the DIMM is used to set at least one memory chip, and the The memory chip can be a dynamic random access memory (Dynamic Random Access Memory, DRAM).

The central processing unit 3 is arranged on the test substrate 1, and is electrically connected to the several waiting Measuring memory module 2.

The BIOS firmware 4 is set on the test substrate 1 and electrically connected to the central processor 3. The BIOS firmware 4 is configured to provide the test substrate 1 to screen several memory modules 2 to be tested installed thereon.

The SPD chip 5 is disposed on the test substrate 1 and electrically connected to the BIOS firmware 4 and the number of memory modules 2 to be tested. The SPD chip 5 internally stores several parameters, including the main setting value of the memory module, the extended setting value, and the BIOS command set, which can be used by the BIOS firmware 4 to read these parameters from the SPD chip 5 .

The Hyper server 6 is externally connected to the SPD chip 5 of the test substrate 1, It is used to write the BIOS command set and setting value of at least one of several BIOS settings to be changed into the SPD chip 5, so that the structured BIOS firmware 4 can read the BIOS command set from the SPD chip 5 after starting When, at least one of the several BIOS settings is directly changed based on the BIOS command set, and it will take effect when the device is turned on next time. If so, a brand new memory testing device 100 is formed by the structure disclosed above.

The main purpose of the present invention is to make the BIOS firmware 4 structured so that it can be The BIOS firmware 4 controlled by the Hyper server 6, and this structure can also directly change the flash memory (Flash memory). In this embodiment, the method used to make the BIOS firmware 4 structurable is to change the SPD chip 5 through the externally connected Hyper server 6 .

When used, the present invention connects the unused space in the SPD chip 5 to On the external Hyper server 6, when the BIOS firmware 4 starts and reads the SPD chip 5, the SPD chip 5 will be connected to the Hyper server 6, and the Hyper server 6 will send the data to be changed to the BIOS The command set and setting value are written into the SPD chip 5, and the BIOS firmware 4 is provided to directly change at least one of several BIOS settings based on the BIOS command set. In other words, the present invention moves some BIOS settings to the SPD chip 5. After being defined, the BIOS settings to be changed will directly affect at least one of the several BIOS settings inside the BIOS firmware 4 through the SPD chip 5. . In this way, the parameters stored in the SPD chip can be changed through the externally connected Hyper server, and various test actions can be provided, such as the setting of voltage offset, the persistence of data storage, etc., and the BIOS firmware will read it after booting The internal parameters of the SPD chip can be partially corrected or fully corrected at least one of several BIOS settings, so as to quickly control a large number of test substrates, save the time for setting one by one, and improve better testing. Convenience and increase test efficiency.

In summary, the present invention is a memory detection device, which can effectively improve the commonly used This shortcoming is to change the parameters stored inside the SPD chip through the externally connected Hyper server, which can provide a variety of test actions. The BIOS firmware will read the parameters inside the SPD chip after booting, so that at least one of several BIOS settings Partial correction or full correction is performed to quickly control a large number of test substrates, saving the time needed to set up one by one, thereby improving the convenience of testing and increasing the efficiency of testing, and thus making the present invention If the product is more advanced, more practical, and more in line with the needs of users, and has indeed met the requirements for invention patent application, the patent application shall be filed in accordance with the law.

However, what is described above is only a preferred embodiment of the present invention, and should not be limited thereto. The scope of implementation of the present invention; therefore, all simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the description of the invention should still fall within the scope covered by the patent of the present invention.

100:Memory detection device 1: Test substrate 2: The memory module to be tested 3: CPU 4:BIOS firmware 5: SPD chip 6:Hyper server

Figure 1 is a schematic block diagram of the present invention.

100:Memory detection device

1: Test substrate

2: The memory module to be tested

3: CPU

4:BIOS firmware

5: SPD chip

6:Hyper server

Claims (3)

A memory testing device, comprising: a test substrate; Several memory modules under test (device under test, DUT) are arranged on the test substrate; a central processing unit (central processing unit, CPU), arranged on the test substrate, and electrically connected to the plurality of memory modules to be tested; A basic input/output system (Basic Input/Output System, BIOS) firmware is set on the test substrate and is electrically connected to the central processing unit, and is configured to provide the test substrate with a pair of waiting devices installed on it. Test the memory module for screening; A serial presence detection (serial presence detect, SPD) chip is arranged on the test substrate and is electrically connected to the BIOS firmware and the memory modules to be tested. Several parameters are stored inside it, including memory modules. A set of main setting values, extended setting values, and a BIOS command set for the BIOS firmware to read the parameters from the SPD chip; and A Hyper server is externally connected to the SPD chip of the test substrate, and is used to write the BIOS command set and setting value of at least one of several BIOS settings to be changed into the SPD chip, so that the structured BIOS When the firmware is started and the BIOS command set is read from the SPD chip, at least one of the several BIOS settings is directly changed based on the BIOS command set, and it becomes effective when the device is turned on next time. According to the memory testing device described in item 1 of the scope of the patent application, each of the memory modules to be tested is a dual in-line memory module (Dual In-line Memory Module, DIMM), and the DIMM is used for At least one memory chip is set. According to the memory testing device described in item 2 of the scope of the patent application, the memory chip is a dynamic random access memory (Dynamic Random Access Memory, DRAM).

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