TWI640910B - Display screen, capacitive touch circuit and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000010292 electrical insulation Methods 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 claims description 65
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 239000011159 matrix material Substances 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 2
- 239000007769 metal material Substances 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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Abstract
一種電容式觸控電路及其製法,係在一基板表面以第一次製程佈設二相鄰之第一電極區塊、一第一導線及二相鄰之第二電極區塊,該第一導線係連接該等第一電極區塊,且該等第二電極區塊係分置於該第一導線雙側,以第二次製程於該第一導線上覆蓋一絕緣層,並以第三次製程於該等第二電極區塊之間連接一金屬製之第二導線,而使該第一導線與該第二導線之間形成電性絕緣,以構成一觸控電路圖形。 A capacitive touch circuit and a method for manufacturing the same are disposed on a surface of a substrate by a first process of arranging two adjacent first electrode blocks, a first wire and two adjacent second electrode blocks, the first wire Connecting the first electrode blocks, and the second electrode blocks are disposed on both sides of the first wire, and the second wire is covered on the first wire with an insulating layer for a third time. The process connects a second metal wire between the second electrode blocks to form electrical insulation between the first wire and the second wire to form a touch circuit pattern.
Description
本發明係提供一種顯示面板、電容式觸控電路及其製法,特別是涉及一種在透明基板表面形成之觸控電路圖形及其佈設技術。 The invention provides a display panel, a capacitive touch circuit and a manufacturing method thereof, in particular to a touch circuit pattern formed on a surface of a transparent substrate and a layout technique thereof.
按,目前坊間之觸控面板(Touch Panel)的觸控輸入方式,包括有電阻式、電容式、光學式、電磁感應式、音波感應式等;其中,電阻式及電容式是藉由使用者以手指或感應筆對面板表面進行觸碰,而於受觸碰位置的面板內部產生電壓及電流的變化,據以偵測出面板表面接受觸碰的位置,以達到觸控輸入的目的。 According to the current touch panel input mode, including resistive, capacitive, optical, electromagnetic induction, sonic induction, etc.; Touching the surface of the panel with a finger or a sensor pen, and generating a change in voltage and current inside the panel subjected to the touched position, thereby detecting the position at which the panel surface is touched to achieve the purpose of touch input.
且知,為了要偵測出使用者以手指或感應筆觸碰於觸控板上之位置,業者研發出各種不同之電容式觸碰感測技術。舉如一種呈格狀之電容式觸控電路圖形之結構,包括有兩組電容感應層,其間以一中間絕緣層分隔,以形成電容效應,每一電容感應層包括實質平行排列之導電元件,兩個電容感應層實質上彼此垂直,每一個導電元件包括一序列呈菱形之電極區塊,係利用透明之導電材料(舉如氧化銦錫Indium Tin Oxide,ITO)製成,且該等電極區塊係藉由狹窄之導線連接在一起, 每一電容感應層上之導電元件係電連接至一周邊線路,一控制電路透過該等周邊線路分別提供訊號至兩組導電元件,能在該表面被觸碰時接收由電極區塊所產生之觸控訊號,以判斷在每一層之觸控位置。 Moreover, in order to detect the position of the user touching the touchpad with a finger or a sensor pen, the manufacturer has developed various capacitive touch sensing technologies. For example, a structure of a capacitive capacitive touch circuit pattern includes two sets of capacitive sensing layers separated by an intermediate insulating layer to form a capacitive effect, and each capacitive sensing layer includes substantially parallel arranged conductive elements. The two capacitive sensing layers are substantially perpendicular to each other, and each of the conductive elements comprises a sequence of diamond-shaped electrode blocks made of a transparent conductive material (such as Indium Tin Oxide, ITO), and the electrode regions are The blocks are connected by narrow wires, The conductive elements on each of the capacitive sensing layers are electrically connected to a peripheral circuit, and a control circuit respectively provides signals to the two sets of conductive elements through the peripheral lines, and can receive the generated by the electrode blocks when the surface is touched. Touch the signal to determine the touch position on each layer.
此外,上述傳統之電容式觸控電路圖形結構的製法,係以第一次製程形成第一組電容感應層之複數電極區塊,以第二次製程形成一周邊線路,而與該第一組電容感應層之複數電極區塊相連接,以第三次製程形成一整面之絕緣層,以第四次製程形成第二組電容感應層之複數電極區塊,以第五次製程形成另一周邊線路,而與該第二組電容感應層之複數電極區塊相連接;惟其缺點在於,上述兩組電容感應層之複數電極區塊、絕緣層及兩組周邊線路必須耗費五次製程,造成其製程上較為繁瑣之問題,且連接該等電極區塊之導線也是利用氧化銦錫製成,致使各電極區塊與周邊線路之間的阻抗難以有效降低,導致各電極區塊與周邊線路間之訊號傳遞靈敏度難以提升的問題,故亟需加以改善。 In addition, the conventional capacitive touch circuit pattern structure is formed by forming a plurality of electrode blocks of the first group of capacitive sensing layers in a first process, and forming a peripheral line by the second process, and the first group The plurality of electrode blocks of the capacitive sensing layer are connected, forming a whole surface insulating layer in a third process, forming a plurality of electrode blocks of the second group of capacitive sensing layers in a fourth process, forming another in the fifth process The peripheral circuit is connected to the plurality of electrode blocks of the second group of capacitive sensing layers; but the disadvantage is that the plurality of electrode blocks, the insulating layer and the two sets of peripheral lines of the two sets of capacitive sensing layers must take five processes, resulting in The manufacturing process is relatively cumbersome, and the wires connecting the electrode blocks are also made of indium tin oxide, so that the impedance between the electrode blocks and the peripheral lines is difficult to be effectively reduced, resulting in a gap between the electrode blocks and the surrounding lines. The signal transmission sensitivity is difficult to improve, so it needs to be improved.
為克服上述先前技術中所揭之問題,本發明之一目的旨在提供一種電容式觸控電路圖形及其製法,尤其是可將雙軸向電極區塊整合在單一次製程中完成,進而簡化佈設觸控電路圖形所需之製程的次數。 In order to overcome the problems disclosed in the prior art, an object of the present invention is to provide a capacitive touch circuit pattern and a method for fabricating the same, in particular, the biaxial electrode block can be integrated in a single process, thereby simplifying The number of processes required to lay out the touch circuit pattern.
為實現上述之目的,本發明之一電容式觸控電路圖形,包括:一基板,該基板上形成至少二相鄰之透明第一電極區塊、一透明第一導線及至少二相鄰之透明第二電極區塊; 該第一導線係形成於該等相鄰之第一電極區塊之間,以連接該等相鄰之第一電極區塊,該等相鄰之第二電極區塊係分置於該第一導線雙側;一金屬製之第二導線,係橫跨該第一導線,並連接該等相鄰之第二電極區塊;一絕緣隔點,形成於該第一導線與該第二導線之間,而使該第一導線與該第二導線之間形成電性絕緣;該基板之二相鄰端邊,分別形成一第一周邊線路及一第二周邊線路,該第一周邊線路係連接該第一電極區塊,且該第二周邊線路係連接該第二電極區塊。 To achieve the above objective, a capacitive touch circuit pattern of the present invention includes: a substrate on which at least two adjacent transparent first electrode blocks, a transparent first wire, and at least two adjacent transparent layers are formed. Second electrode block; The first wire is formed between the adjacent first electrode blocks to connect the adjacent first electrode blocks, and the adjacent second electrode blocks are placed in the first a second wire of the wire, spanning the first wire and connecting the adjacent second electrode blocks; an insulating spacer formed on the first wire and the second wire Between the first wire and the second wire is electrically insulated; two adjacent end sides of the substrate respectively form a first peripheral line and a second peripheral line, and the first peripheral line is connected The first electrode block is connected to the second electrode block.
此外,該電容式觸控電路圖形之一製法,包括:以第一次製程一次佈設形成二相鄰之第一電極區塊、一第一導線及二相鄰之第二電極區塊於一基板表面;該第一導線係佈設於該等相鄰之第一電極區塊之間,以連接該等相鄰之第一電極區塊;該等相鄰之第二電極區塊係分置於該第一導線雙側;以第二次製程於該基板表面佈設形成一絕緣層,覆蓋該第一導線;以第三次製程於該絕緣層上佈設形成一金屬製之第二導線,連接該等相鄰之第二電極區塊,而使該第一導線與該第二導線之間形成電性絕緣,以構成一觸控電路圖形。 In addition, the method for manufacturing the capacitive touch circuit pattern comprises: forming a second adjacent first electrode block, a first wire, and two adjacent second electrode blocks on a substrate in a first process. a surface of the first electrode is disposed between the adjacent first electrode blocks to connect the adjacent first electrode blocks; the adjacent second electrode blocks are disposed The first wire is double-sided; a second process is disposed on the surface of the substrate to form an insulating layer covering the first wire; and a third process is arranged on the insulating layer to form a second wire made of metal, and the connection is made. An adjacent second electrode block forms electrical insulation between the first wire and the second wire to form a touch circuit pattern.
其中,更加包含於形成該第二導線的同時,分別佈設形成一第一周邊線路及一第二周邊線路於該基板之二相鄰端邊,而使該第一周邊線路連接該第一電極區塊,並使該第二周邊線路連接該第二電極區塊。 The method further includes forming a second peripheral line and forming a first peripheral line and a second peripheral line on two adjacent end sides of the substrate, and connecting the first peripheral line to the first electrode area. Blocking and connecting the second peripheral line to the second electrode block.
該絕緣層係為一絕緣隔點,且該第二導線係橫跨該絕緣隔點。或者,該絕緣層並覆蓋該等相鄰之第一電極區塊及該等相鄰之第二電極區塊,且該絕緣層表面具二相鄰之通 孔,分別形成於該等相鄰之第二電極區塊上方,該第二導線係位於該等相鄰的通孔之間,並疊置於該等相鄰之通孔上,而連接該等相鄰之第二電極區塊。 The insulating layer is an insulating spacer and the second wire is spanned across the insulating spacer. Or the insulating layer covers the adjacent first electrode blocks and the adjacent second electrode blocks, and the surface of the insulating layer has two adjacent channels. The holes are respectively formed on the adjacent second electrode blocks, the second wires are located between the adjacent through holes, and are stacked on the adjacent through holes, and connected Adjacent second electrode block.
另外,該電容式觸控電路圖形之另一製法,包括:以第一次製程佈設形成一金屬製之第二導線於一基板表面;以第二次製程於該基板表面佈設形成一絕緣層,覆蓋該第二導線;以第三次製程一次佈設形成二相鄰之第一電極區塊、一第一導線及二相鄰之第二電極區塊於該基板上;該等相鄰之第二電極區塊係分別連接該第二導線雙端;該等相鄰之第一電極區塊係分置於該第二導線雙側;該第一導線係位於該絕緣層上,並連接該等相鄰之第一電極區塊,而使該第一導線與該第二導線之間形成電性絕緣,以構成一觸控電路圖形。 In addition, another method for fabricating the capacitive touch circuit pattern includes: forming a second metal wire on a surface of the substrate by using a first process; and forming an insulating layer on the surface of the substrate by a second process. Covering the second wire; forming a second adjacent first electrode block, a first wire, and two adjacent second electrode blocks on the substrate in a third process; the adjacent second The electrode blocks are respectively connected to the two ends of the second wire; the adjacent first electrode blocks are respectively disposed on both sides of the second wire; the first wire is located on the insulating layer and is connected to the phase Adjacent to the first electrode block, the first wire and the second wire are electrically insulated to form a touch circuit pattern.
其中,更加包含於形成該第二導線的同時,分別佈設形成一第一周邊線路及一第二周邊線路於該基板之二相鄰端邊,而使該第一電極區塊連接該第一周邊線路,並使該第二電極區塊連接該第二周邊線路。 The method further includes forming a second peripheral line and forming a first peripheral line and a second peripheral line on two adjacent end sides of the substrate, so that the first electrode block is connected to the first periphery. a line and connecting the second electrode block to the second peripheral line.
該絕緣層係為一絕緣隔點,且該第一導線係橫跨該絕緣隔點。或者,該絕緣層表面具二相鄰之通孔,分別形成於該第二導線之雙端上方,該等相鄰之第一電極區塊及該等相鄰之第二電極區塊係位於該絕緣層上,且該等相鄰之第二電極區塊係分別疊置於該通孔上,而分別連接該第二導線雙端。 The insulating layer is an insulating spacer and the first conductive line spans the insulating spacer. Alternatively, the surface of the insulating layer has two adjacent through holes formed respectively over the double ends of the second wires, and the adjacent first electrode blocks and the adjacent second electrode blocks are located at the On the insulating layer, the adjacent second electrode blocks are respectively stacked on the through holes, and the two ends of the second wires are respectively connected.
據此,該等第一與第二電極區塊能在單一次之製程中佈設形成,以簡化佈設觸控電路圖形所需之製程的次數。 Accordingly, the first and second electrode blocks can be formed in a single process to simplify the number of processes required to lay the touch circuit pattern.
然而,為能明確且充分揭露本發明,併予列舉出 較佳實施例,請配合參照圖式而詳細說明如後述。 However, in order to clearly and fully disclose the present invention, The preferred embodiment will be described in detail below with reference to the drawings.
1、1a、1b、1c‧‧‧第一電極區塊 1, 1a, 1b, 1c‧‧‧ first electrode block
10‧‧‧第一軸向導電元件 10‧‧‧First axial conductive element
11、11a、11b、11c‧‧‧第一導線 11, 11a, 11b, 11c‧‧‧ first wire
2、2a、2b、2c‧‧‧第二電極區塊 2, 2a, 2b, 2c‧‧‧ second electrode block
20‧‧‧第二軸向導電元件 20‧‧‧Second axial conductive element
21、21a、21b、21c、22‧‧‧第二導線 21, 21a, 21b, 21c, 22‧‧‧ second conductor
3、3a、3b、3c‧‧‧基板 3, 3a, 3b, 3c‧‧‧ substrate
4、4a‧‧‧絕緣隔點 4, 4a‧‧‧Insulated compartment
40b、40c‧‧‧絕緣層 40b, 40c‧‧‧ insulation
41b、41c‧‧‧通孔 41b, 41c‧‧‧through holes
51、51a、51b、51c‧‧‧第一周邊線路 51, 51a, 51b, 51c‧‧‧ first peripheral line
52、52a、52b、52c‧‧‧第二周邊線路 52, 52a, 52b, 52c‧‧‧ second peripheral line
為了讓本發明之上述目的、特徵、及優點能更明顯易懂,以下配合所附圖式,作詳細說明如下:圖1至圖3:為本發明一實施例之實施步驟的示意圖。 The above-mentioned objects, features, and advantages of the present invention will be more apparent from the following description. FIG. 1 to FIG. 3 are schematic diagrams showing the implementation steps of an embodiment of the present invention.
圖4:為本發明一實施例之附加實施形態的示意圖。 Figure 4 is a schematic illustration of an additional embodiment of an embodiment of the invention.
圖5至圖7:為本發明另一實施例之實施步驟的示意圖。 5 to 7 are schematic views showing implementation steps of another embodiment of the present invention.
圖8至圖10:為本發明又一實施例之實施步驟的示意圖。 8 to 10 are schematic views showing implementation steps of still another embodiment of the present invention.
圖11至圖13:為本發明再一實施例之實施步驟的示意圖。 11 to 13 are schematic views showing implementation steps of still another embodiment of the present invention.
請參閱圖3,揭示出本發明之一電容式觸控電路圖形的平面圖,並配合圖1及圖2說明本發明係在一基板3表面形成至少二相鄰之透明第一電極區塊1、一透明第一導線11及至少二相鄰之透明第二電極區塊2,該第一導線11係形成於該等相鄰之第一電極區塊1之間,以連接該等相鄰之第一電極區塊1,該等相鄰之第二電極區塊2係分置於該第一導線11雙側,且該等相鄰之第二電極區塊2之間連接一利用金屬材料製成之第二導線21,橫跨該第一導線11,並於該第一與第二導線11、21之間形成一絕緣隔點4,而使該第一導線與該第二導線之間形成電性絕緣。 Referring to FIG. 3, a plan view of a capacitive touch circuit pattern of the present invention is disclosed. Referring to FIG. 1 and FIG. 2, the present invention is characterized in that at least two adjacent transparent first electrode blocks are formed on a surface of a substrate 3. a transparent first wire 11 and at least two adjacent transparent second electrode blocks 2, the first wire 11 being formed between the adjacent first electrode blocks 1 to connect the adjacent ones An electrode block 1, the adjacent second electrode block 2 is disposed on both sides of the first wire 11, and the connection between the adjacent second electrode blocks 2 is made of a metal material. a second wire 21 spanning the first wire 11 and forming an insulating spacer 4 between the first and second wires 11, 21 to form an electrical connection between the first wire and the second wire Sexual insulation.
其中,該基板3之二相鄰端邊,分別形成一第一周邊線路51及一第二周邊線路52(如圖3所示),該第一周邊線路51係連接該第一電極區塊1,且該第二周邊線路52係連接該第 二電極區塊2。該電容式觸控電路圖形之製法,在本實施例中可利用黃光製程加以實踐,包括下列步驟: The two adjacent ends of the substrate 3 respectively form a first peripheral line 51 and a second peripheral line 52 (shown in FIG. 3), and the first peripheral line 51 is connected to the first electrode block 1 And the second peripheral line 52 is connected to the first Two electrode block 2. The method for manufacturing the capacitive touch circuit pattern can be practiced in the embodiment by using a yellow light process, including the following steps:
(1)在一透明基板3表面以第一次黃光製程一次佈設形成二相鄰之第一電極區塊1、一第一導線11及二相鄰之第二電極區塊2(如圖1所示);該第一導線11係佈設於該等相鄰之第一電極區塊1之間,以連接該等相鄰之第一電極區塊1;該等相鄰之第二電極區塊2係分置於該第一導線11雙側;該第一、第二電極區塊1、2及第一導線11可由透明之導電材料製成,該透明之導電材料可以是選用氧化銦錫(ITO)。 (1) forming a first adjacent first electrode block 1, a first conductive line 11 and two adjacent second electrode blocks 2 on the surface of a transparent substrate 3 by a first yellow light process (Fig. 1) The first wire 11 is disposed between the adjacent first electrode blocks 1 to connect the adjacent first electrode blocks 1; the adjacent second electrode blocks 2 is placed on both sides of the first wire 11; the first and second electrode blocks 1, 2 and the first wire 11 can be made of a transparent conductive material, and the transparent conductive material can be selected from indium tin oxide ( ITO).
該第一、第二電極區塊1、2及第一導線11在本實施例上可分別以複數組實施;其中,該等第一電極區塊1係相互平行且呈矩陣間隔排列,且該等第二電極區塊2亦相互平行且呈矩陣間隔排列,而使該等第一導線11亦呈矩陣間隔排列。 The first and second electrode blocks 1 and 2 and the first wire 11 can be respectively implemented in a plurality of arrays in the embodiment; wherein the first electrode blocks 1 are arranged parallel to each other and arranged at a matrix interval, and the The second electrode blocks 2 are also arranged parallel to each other and arranged at a matrix interval, so that the first wires 11 are also arranged at a matrix interval.
(2)依據該等第一、第二電極區塊1、2及第一導線11的位置,以第二次黃光製程於該基板3表面佈設形成一絕緣隔點4(如圖2所示),覆蓋該第一導線11,該絕緣隔點4可由透明之絕緣材料製成,該絕緣材料可以是選用氧化矽或其他具備絕緣能力的等效材料,且該絕緣隔點4在本實施例上同樣可以複數組實施,而呈矩陣間隔排列。 (2) According to the positions of the first and second electrode blocks 1, 2 and the first wire 11, a second yellow light process is arranged on the surface of the substrate 3 to form an insulating spacer 4 (as shown in FIG. 2). Covering the first wire 11, the insulating spacer 4 may be made of a transparent insulating material, which may be selected from yttria or other equivalent insulating material, and the insulating spacer 4 is in this embodiment. The same can be implemented in a complex array, and arranged in a matrix interval.
(3)依據該絕緣隔點4的位置,以第三次黃光製程在該基板3表面一次佈設形成一利用金屬材料製成之第二導線21、一第一周邊線路51及一第二周邊線路52(如圖3所示);該第二導線21係連接於該等相鄰之第二電極區塊2之間,並橫跨於該絕緣隔點4上,而使該第一導線11與該第二導線21之間 形成電性絕緣;該第一及第二周邊線路51、52係分別佈設於該基板3之二相鄰端邊,而使該第一周邊線路51連接該第一電極區塊1,並使該第二周邊線路52連接該第二電極區塊2。 (3) Depending on the position of the insulating spacer 4, a second wire 21 made of a metal material, a first peripheral line 51 and a second periphery are formed on the surface of the substrate 3 at a time by a third yellow light process. a line 52 (shown in FIG. 3); the second wire 21 is connected between the adjacent second electrode blocks 2 and spans the insulating spacer 4 to make the first wire 11 Between the second wire 21 Electrically insulating is formed; the first and second peripheral lines 51 and 52 are respectively disposed on two adjacent end sides of the substrate 3, and the first peripheral line 51 is connected to the first electrode block 1 and the The second peripheral line 52 is connected to the second electrode block 2.
該第二導線21、第一及第二周邊線路51、52可選用導電性佳之金、銀、銅、鋁等金屬材料,且該第二導線21、第一及第二周邊線路51、52在本實施例上可分別以複數組實施。或者,該第二導線22在實施上亦可以疊置方式串連該等第二電極區塊2(如圖4所示)。 The second wire 21, the first and second peripheral lines 51, 52 may be made of a metal material such as gold, silver, copper, aluminum, etc., and the second wire 21, the first and second peripheral lines 51, 52 are This embodiment can be implemented in a complex array, respectively. Alternatively, the second wires 22 may be stacked in series to connect the second electrode blocks 2 (as shown in FIG. 4).
如此,該等第一電極區塊1及第一導線11構成一第一軸向導電元件10,各第一軸向導電元件10構成一電容感應層,該等第二電極區塊2及第二導線21構成一第二軸向導電元件20,各第二軸向導電元件20構成另一電容感應層,而使該等電容感應層、絕緣隔點4及周邊線路51、52構成一觸控電路圖形(如圖3及圖4所示)。此外,該基板3實際上可為玻璃、塑膠或其他透明之絕緣材料所構成。 Thus, the first electrode block 1 and the first wire 11 constitute a first axial conductive element 10, and each of the first axial conductive elements 10 constitutes a capacitive sensing layer, and the second electrode blocks 2 and 2 The wire 21 constitutes a second axial conductive element 20, and each of the second axial conductive elements 20 constitutes another capacitive sensing layer, so that the capacitive sensing layer, the insulating spacer 4 and the peripheral lines 51, 52 constitute a touch circuit. Graphics (as shown in Figures 3 and 4). In addition, the substrate 3 can be constructed of glass, plastic or other transparent insulating material.
本發明之觸控電路圖形實施在一顯示面板(Display Panel)內時,該等第二導線21、22能與顯示面板內之若干黑色矩陣(Black Matrix)排列的遮光用遮蔽層相互重疊;或者,亦可省略該遮蔽層,並以該等第二導線21、22作為該顯示面板之遮光元件,且該等利用金屬材料製成之第二導線21、22在實施上亦可減低各第二電極區塊2與第二周邊線路52之間的阻抗,以提升各電極區塊與周邊線路間之訊號傳遞的靈敏度;此外,該等絕緣隔點4呈矩陣間隔排列之設計,相較於上述傳統之整面絕緣層設計,亦具有提升面板穿透率之效益。 When the touch circuit pattern of the present invention is implemented in a display panel, the second wires 21, 22 can overlap with the blackout shielding layers arranged in a plurality of black matrixes in the display panel; or The shielding layer can also be omitted, and the second wires 21 and 22 are used as the light shielding elements of the display panel, and the second wires 21 and 22 made of metal materials can also be reduced in the second. The impedance between the electrode block 2 and the second peripheral line 52 is to improve the sensitivity of the signal transmission between the electrode blocks and the peripheral lines; in addition, the insulating spacers 4 are arranged in a matrix interval, compared to the above The traditional full-surface insulation design also has the benefit of improving panel penetration.
依據上述可知,本發明之第一與第二電極區塊1、2能在單一次製程中佈設形成於該透明基板3表面,進而能以三次製程完成該觸控電路圖形,以簡化佈設觸控電路圖形所需之黃光製程的次數。 According to the above, the first and second electrode blocks 1 and 2 of the present invention can be disposed on the surface of the transparent substrate 3 in a single process, and the touch circuit pattern can be completed in three processes to simplify the layout of the touch. The number of yellow light processes required for the circuit pattern.
請參閱圖7,揭示出本發明之另一電容式觸控電路圖形的平面圖,其配置形態係與圖3相類似,差異處僅在於佈設形成至基板表面的順序,該電容式觸控電路圖形之製法,在本實施例中可利用黃光製程加以實踐,包括下列步驟: Referring to FIG. 7 , a plan view of another capacitive touch circuit pattern of the present invention is disclosed. The configuration is similar to that of FIG. 3 . The difference is only in the order of the layout to the surface of the substrate. The capacitive touch circuit pattern The method of manufacturing can be practiced in the present embodiment by using a yellow light process, including the following steps:
(1)在該基板3a表面以第一次黃光製程一次佈設形成一利用金屬材料製成之第二導線21a、一第一周邊線路51a及一第二周邊線路52a(如圖5所示),且該第二導線21a、第一及第二周邊線路51a、52a在本實施例上可分別以複數組實施;其中,各第二導線21a係佈設成陣列。 (1) forming a second wire 21a made of a metal material, a first peripheral line 51a, and a second peripheral line 52a (shown in FIG. 5) on the surface of the substrate 3a by a first yellow light process. In this embodiment, the second wire 21a and the first and second peripheral lines 51a and 52a can be respectively implemented in a plurality of arrays; wherein the second wires 21a are arranged in an array.
(2)依據該等第二導線21a的位置,以第二次黃光製程於該基板3a表面佈設形成一絕緣隔點4a(如圖6所示),覆蓋於該第二導線21a上,且該絕緣隔點4a在本實施例上可以複數組實施。 (2) arranging an insulating spacer 4a (shown in FIG. 6) on the surface of the substrate 3a by a second yellow light process according to the position of the second wires 21a, covering the second wire 21a, and The insulating spacer 4a can be implemented in a multiple array in this embodiment.
(3)依據該等第二導線21a、絕緣隔點4a、第一及第二周邊線路51a、52a的位置,以第三次黃光製程在該基板3a表面一次佈設形成二相鄰之第一電極區塊1a、一第一導線11a及二相鄰之第二電極區塊2a(如圖7所示);該等相鄰之第二電極區塊2a係分別連接該第二導線21a雙端;該等第一電極區塊1a係分置於該第二導線21a雙側;該第一導線11a係橫跨於該絕緣隔點4a上,並連接該等相鄰之第一電極區塊1a,而使該第一 導線11a與該第二導線21a之間形成電性絕緣。 (3) Depending on the positions of the second wire 21a, the insulating spacer 4a, and the first and second peripheral lines 51a, 52a, the first yellow light process is disposed on the surface of the substrate 3a to form a second adjacent first. The electrode block 1a, a first wire 11a and two adjacent second electrode blocks 2a (shown in FIG. 7); the adjacent second electrode blocks 2a are respectively connected to the second wire 21a at both ends The first electrode block 1a is disposed on both sides of the second wire 21a; the first wire 11a spans the insulating spacer 4a and connects the adjacent first electrode blocks 1a And make the first Electrical insulation is formed between the wire 11a and the second wire 21a.
該第一、第二電極區塊1a、2a及第一導線11a在本實施例上可分別以複數組實施,而使該等第一及第二電極區塊1a、2a構成一觸控電路圖形,其餘構件組成及實施方式係等同於上述圖1至圖3之實施例。 In the embodiment, the first and second electrode blocks 1a, 2a and the first wire 11a can be respectively implemented in a complex array, and the first and second electrode blocks 1a, 2a form a touch circuit pattern. The remaining component compositions and implementations are equivalent to the embodiments of Figures 1 through 3 above.
請參閱圖10,揭示出本發明之又一電容式觸控電路圖形的平面圖,並配合圖8及圖9說明本發明係在一基板3b上形成二相鄰之第一電極區塊1b、一第一導線11b及二相鄰之第二電極區塊2b,該第一導線11b係形成於該等相鄰之第一電極區塊1b之間,以連接該等相鄰之第一電極區塊1b,該等相鄰之第二電極區塊2b係分置於該第一導線11b雙側,且該等相鄰之第二電極區塊2b之間連接一利用金屬材料製成之第二導線21b,橫跨該第一導線11b,並於該基板3b表面佈設一絕緣層40b,充實於該第一電極區塊1b、第二電極區塊2b、第一導線11b及第二導線21b之間,而使該第一導線11b與該第二導線21b之間形成電性絕緣。 Referring to FIG. 10, a plan view of another capacitive touch circuit pattern of the present invention is disclosed. The present invention is directed to form two adjacent first electrode blocks 1b and 1 on a substrate 3b in conjunction with FIGS. 8 and 9. a first wire 11b and two adjacent second electrode blocks 2b, the first wire 11b being formed between the adjacent first electrode blocks 1b to connect the adjacent first electrode blocks 1b, the adjacent second electrode block 2b is disposed on both sides of the first wire 11b, and a second wire made of a metal material is connected between the adjacent second electrode blocks 2b. 21b, spanning the first wire 11b, and an insulating layer 40b is disposed on the surface of the substrate 3b, and is enriched between the first electrode block 1b, the second electrode block 2b, the first wire 11b and the second wire 21b. And electrically insulating the first wire 11b and the second wire 21b.
其中,該基板3b之二相鄰端邊,分別形成一第一周邊線路51b及一第二周邊線路52b,該第一周邊線路51b係連接該第一電極區塊1b,且該第二周邊線路52b係連接該第二電極區塊2b。該電容式觸控電路圖形之製法,在本實施例中可利用黃光製程加以實踐,包括下列步驟: The first peripheral line 51b and the second peripheral line 52b are respectively formed on the adjacent end sides of the substrate 3b. The first peripheral line 51b is connected to the first electrode block 1b, and the second peripheral line is connected. 52b is connected to the second electrode block 2b. The method for manufacturing the capacitive touch circuit pattern can be practiced in the embodiment by using a yellow light process, including the following steps:
(1)以第一次黃光製程在該基板3b表面一次佈設形成一利用金屬材料製成之第二導線21b、一第一周邊線路51b及一第二周邊線路52b(如圖8所示),且該第二導線21b、第一 及第二周邊線路51b、52b在本實施例上可分別以複數組實施。 (1) forming a second wire 21b made of a metal material, a first peripheral line 51b, and a second peripheral line 52b (shown in FIG. 8) on the surface of the substrate 3b in a first yellow light process. And the second wire 21b, the first The second peripheral lines 51b, 52b can be implemented in a complex array in this embodiment.
(2)依據該等第二導線21b的位置,以第二次黃光製程於該基板3b表面佈設形成一絕緣層40b(如圖9所示),且該絕緣層40b表面具有二相鄰之通孔41b,分別形成於該第二導線21b之雙端上方;該絕緣層40b可由透明之絕緣材料製成,該絕緣材料可以是選用氧化矽或其他具備絕緣能力的等效材料,該等相鄰之通孔41b在本實施例上可以複數組實施。 (2) Depending on the position of the second wires 21b, an insulating layer 40b (shown in FIG. 9) is disposed on the surface of the substrate 3b by a second yellow light process, and the surface of the insulating layer 40b has two adjacent layers. The through holes 41b are respectively formed on the double ends of the second wires 21b; the insulating layer 40b may be made of a transparent insulating material, and the insulating material may be selected from cerium oxide or other equivalent materials having insulating properties. The adjacent via holes 41b can be implemented in a multiple array in this embodiment.
(3)依據該等相鄰之通孔41b的位置,以第三次黃光製程在該基板3b表面之絕緣層40b上一次佈設形成二相鄰之第一電極區塊1b、一第一導線11b及二相鄰之第二電極區塊2b(如圖10所示);該等相鄰之第二電極區塊2b係分別疊置於絕緣層40b表面之各通孔41b上,而分別連接該第二導線21b雙端,該等相鄰之第一電極區塊1b係分置於該等通孔41b之間的雙側;該第一導線11b係形成於該等通孔41b之間的絕緣層40b表面,並連接該等相鄰之第一電極區塊1b之間,而使該第一導線11b與該第二導線21b之間形成電性絕緣。 (3) arranging two adjacent first electrode blocks 1b and a first wire on the insulating layer 40b on the surface of the substrate 3b in a third yellow light process according to the position of the adjacent through holes 41b. 11b and two adjacent second electrode blocks 2b (as shown in FIG. 10); the adjacent second electrode blocks 2b are respectively stacked on the respective through holes 41b of the surface of the insulating layer 40b, and are respectively connected The second wire 21b is double-ended, and the adjacent first electrode block 1b is disposed on both sides between the through holes 41b; the first wire 11b is formed between the through holes 41b. The surface of the insulating layer 40b is connected between the adjacent first electrode blocks 1b to form electrical insulation between the first wire 11b and the second wire 21b.
該第一、第二電極區塊1b、2b及第一導線11b在本實施例上可分別以複數組實施,而使該等第一及第二電極區塊1b、2b構成一觸控電路圖形,其餘構件組成及實施方式係等同於上述圖1至圖3之實施例。 In the embodiment, the first and second electrode blocks 1b and 2b and the first wire 11b can be respectively implemented in a complex array, and the first and second electrode blocks 1b and 2b form a touch circuit pattern. The remaining component compositions and implementations are equivalent to the embodiments of Figures 1 through 3 above.
請參閱圖13,揭示出本發明之再一電容式觸控電路圖形的平面圖,其配置形態係與圖10相類似,差異處僅在於佈設形成至基板表面的順序,該電容式觸控電路圖形之製法,在本實施例中可利用黃光製程加以實踐,包括下列步驟: Referring to FIG. 13 , a plan view of another capacitive touch circuit pattern of the present invention is disclosed. The configuration is similar to that of FIG. 10 . The difference is only in the order of layout to the surface of the substrate. The capacitive touch circuit pattern is shown in FIG. The method of manufacturing can be practiced in the present embodiment by using a yellow light process, including the following steps:
(1)在一透明基板3c表面以第一次黃光製程一次佈設形成二相鄰之第一電極區塊1c、一第一導線11c及二相鄰之第二電極區塊2c(如圖11所示);該第一導線11c係佈設於該等相鄰之第一電極區塊1c之間,以連接該等相鄰之第一電極區塊1c;該等相鄰之第二電極區塊2c係分置於該第一導線11c雙側;該第一、第二電極區塊1c、2c及第一導線11c在本實施例上可分別以複數組實施;其中,該等第一電極區塊1c係相互平行且呈矩陣間隔排列,且該等第二電極區塊2c亦相互平行且呈矩陣間隔排列。 (1) forming a first adjacent first electrode block 1c, a first conductive line 11c and two adjacent second electrode blocks 2c on the surface of a transparent substrate 3c by a first yellow light process (Fig. 11). The first wire 11c is disposed between the adjacent first electrode blocks 1c to connect the adjacent first electrode blocks 1c; the adjacent second electrode blocks 2c is disposed on both sides of the first wire 11c; the first and second electrode blocks 1c, 2c and the first wire 11c are respectively implemented in a complex array in the embodiment; wherein the first electrode regions The blocks 1c are arranged parallel to each other and arranged at a matrix interval, and the second electrode blocks 2c are also arranged parallel to each other and arranged at a matrix interval.
(2)依據該等第一、第二電極區塊1c、2c及第一導線11c的位置,以第二次黃光製程於該基板3c表面佈設形成一絕緣層40c(如圖12所示),覆蓋該等第一、第二電極區塊1c、2c及第一導線11c,且該絕緣層40c表面具二相鄰之通孔41c,分別形成於該相鄰之第二電極區塊2c上方,且該等相鄰之通孔41c在本實施例上可以複數組實施。 (2) Depending on the positions of the first and second electrode blocks 1c, 2c and the first wire 11c, an insulating layer 40c is formed on the surface of the substrate 3c by a second yellow light process (as shown in FIG. 12). The first and second electrode blocks 1c, 2c and the first wire 11c are covered, and the surface of the insulating layer 40c has two adjacent through holes 41c formed respectively above the adjacent second electrode block 2c. And the adjacent through holes 41c can be implemented in a multiple array in this embodiment.
(3)依據該等相鄰之通孔41c的位置,以第三次黃光製程在該基板3c表面一次佈設形成一利用金屬材料製成之第二導線21c、一第一周邊線路51c及一第二周邊線路52c(如圖13所示);該第二導線21c係位於該等相鄰之通孔41c間的絕緣層40c表面,並疊置於該等相鄰之通孔41c上,以連接該等相鄰之第二電極區塊2c,而使該第一導線11c與該第二導線21c之間形成電性絕緣;該第一及第二周邊線路51c、52c係分別佈設於該基板3c之二相鄰端邊,而使該第一周邊線路51c連接該第一電極區塊1c,且該第二周邊線路52c連接該第二電極區塊2c。 (3) forming, according to the position of the adjacent through holes 41c, a second wire 21c made of a metal material, a first peripheral line 51c and a first surface on the surface of the substrate 3c by a third yellow light process. a second peripheral line 52c (shown in FIG. 13); the second lead 21c is located on the surface of the insulating layer 40c between the adjacent through holes 41c, and is superposed on the adjacent through holes 41c to Connecting the adjacent second electrode blocks 2c to electrically insulate the first wire 11c from the second wire 21c; the first and second peripheral lines 51c, 52c are respectively disposed on the substrate The second peripheral edge 51c is connected to the first electrode block 1c, and the second peripheral line 52c is connected to the second electrode block 2c.
該第二導線21c、第一及第二周邊線路51c、52c在本實施例上可分別以複數組實施,而使該等第一及第二電極區塊1c、2c構成一觸控電路圖形,其餘構件組成及實施方式係等同於上述圖8至圖10之實施例。 In the embodiment, the second wire 21c and the first and second peripheral lines 51c and 52c can be respectively implemented in a complex array, and the first and second electrode blocks 1c and 2c form a touch circuit pattern. The remaining component compositions and embodiments are equivalent to the embodiments of Figures 8 through 10 above.
雖然本發明已揭露較佳實施例如上,然其並非用以限定本發明,在此技術領域中具有通常知識者當可瞭解,在不脫離本發明之精神和範圍內,當可做些許更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。 While the present invention has been described in its preferred embodiments, it is not intended to limit the invention, and it is understood by those of ordinary skill in the art that Retouching. Accordingly, the scope of the invention is defined by the scope of the appended claims.
Claims (15)
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWM342558U (en) * | 2008-05-26 | 2008-10-11 | Young Fast Optoelectronics Co | Capacitive type touch panel |
| TW200842681A (en) * | 2007-04-27 | 2008-11-01 | Tpk Touch Solutions Inc | Touch pattern structure of a capacitive touch panel |
| TWM344544U (en) * | 2007-12-25 | 2008-11-11 | Cando Corp | Sensory structure of touch panel |
| TWM352088U (en) * | 2008-08-12 | 2009-03-01 | Cando Corp | Sensory structure of capacitive touch panel with predetermined sensing areas |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200842681A (en) * | 2007-04-27 | 2008-11-01 | Tpk Touch Solutions Inc | Touch pattern structure of a capacitive touch panel |
| TWM344544U (en) * | 2007-12-25 | 2008-11-11 | Cando Corp | Sensory structure of touch panel |
| TWM342558U (en) * | 2008-05-26 | 2008-10-11 | Young Fast Optoelectronics Co | Capacitive type touch panel |
| TWM352088U (en) * | 2008-08-12 | 2009-03-01 | Cando Corp | Sensory structure of capacitive touch panel with predetermined sensing areas |
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