TWI502648B - Method for manufacturing multi-gate transistor device - Google Patents

Description

Multi-gate polar crystal element manufacturing method

The invention relates to a method for fabricating a multi-gate transistor device, in particular to a method for fabricating a multi-gate transistor device with a raised source/drain.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a Fin Field effect transistor (FinFET) component replaces a planar transistor component.

Please refer to FIG. 1 , which is a perspective view of a conventional FinFET device. As shown in FIG. 1 , the conventional FinFET device 100 firstly patterns a single crystal germanium layer on the surface of the insulating substrate 102 by etching or the like to form a fin-shaped germanium film in the insulating substrate 102 ( The figure is not shown, and a high dielectric constant (high-k) insulating layer 104 covering a portion of the germanium film is formed on the germanium film, and the gate 106 is coated on the high dielectric constant insulating layer 104 and the germanium film, and finally The source/drain 108 is formed in the fin-shaped tantalum film not covered by the gate 106 by an ion implantation process and a tempering process. Since the process of the FinFET device 100 can be integrated with a conventional logic device process, it has considerable process compatibility. In addition, due to the special structure of the FinFET element 100, conventional isolation techniques such as shallow trench isolation can be omitted. More importantly, since the three-dimensional structure of the FinFET element 100 increases the contact area of the gate 106 with the fin-shaped base body, the carrier control of the gate 106 to the channel region can be increased, thereby reducing the number of small-sized components. The source induced induced drain induced barrier lowering (DIBL) effect and the short channel effect. Furthermore, since the gate 106 of the same length in the FinFET element 100 has a larger channel width, a doubled drain drive current can be obtained.

However, since the source/drain 108 of the FinFET element 100 is still fabricated by ion implantation, the lattice of the fin-shaped film is inevitably damaged. Although the lattice damage caused by the high temperature repair ion implantation can be utilized in the subsequent tempering process, the high temperature sufficient to repair the lattice damage affects the stability of the high dielectric constant insulating layer 104. In other words, due to the low thermal budget consideration of the high dielectric constant insulating layer 104, lattice damage caused by ion implantation may not result in sufficient high temperature repair. Therefore, there is still a need for a method of fabricating a multi-gate transistor element that solves the above dilemma.

Accordingly, it is an object of the present invention to provide a method of fabricating a multi-gate transistor device that avoids lattice damage caused by ion implantation.

According to the patent application scope of the present invention, there is provided a method of fabricating a multi-gate transistor device, which first provides a semiconductor substrate, and a first patterned semiconductor layer is formed on the semiconductor substrate. A gate dielectric layer and a gate layer are sequentially formed on the semiconductor substrate, and the gate dielectric layer and the gate layer cover a portion of the first patterned semiconductor layer. Subsequently, a portion of the first patterned semiconductor layer is removed to form a second patterned semiconductor layer, and after the second patterned semiconductor layer is formed, a selective epitaxial growth (SEG) process is performed. An epitaxial layer is formed on the surface of the second patterned semiconductor layer.

According to the method of fabricating the multi-gate transistor of the present invention, an epitaxial layer containing a doping type having a conductivity type is formed on the surface of the second patterned semiconductor layer by using an SEG process for use as a multi-gate transistor The raised source/drain of the component. Since the method for fabricating the multi-gate transistor device provided by the present invention replaces the conventional ion implantation process and the tempering process by the SEG process, the ion implantation process can be prevented from damaging the crystal lattice of the second patterned semiconductor layer. And can avoid the adverse effects of the high thermal budget process such as tempering process on the dielectric layer. In addition, by the epitaxial layer formed on the surface of the second patterned semiconductor layer, strain stress can be more efficiently supplied to the channel region of the multi-gate transistor element, so that the carrier mobility of the channel region can be further improved. , thereby improving the performance of the multi-gate transistor component.

Please refer to FIG. 2 to FIG. 7 . FIG. 2 to FIG. 7 are schematic diagrams showing a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention. As shown in FIG. 2, the preferred embodiment first provides a semiconductor substrate 200, which may include a silicon-on-insulator (SOI) substrate. As is known to those skilled in the art, the SOI substrate may include a substrate 202, a bottom oxide (BOX) layer 204, and a semiconductor layer formed on the bottom oxide layer 204 from bottom to top. Shown as a layer of germanium with a single crystal structure. However, in order to provide better heat dissipation and grounding effects, and to help reduce cost and suppress noise, the semiconductor substrate 200 provided by the preferred embodiment may include a bulk silicon substrate.

Please continue to see Figure 2. A patterned hard mask 208 is then formed over the semiconductor substrate 200 to define fin portions of at least one of the plurality of gate transistor elements. Subsequently, an etching process is performed to remove the semiconductor layer of the semiconductor substrate 200, and at least one first patterned semiconductor layer 206 is formed on the semiconductor substrate 200. The first patterned semiconductor layer 206 is at least included as shown in FIG. A fin portion 206a of a plurality of gate transistor elements. Fin portion 206a having a width D and a height h _{1 1,} while the width D ₁ has a height h ₁ ratio, the ratio may be 1: 1 to 1: 1.5. In addition, please refer to FIG. 3, which is a schematic diagram of a variation of the present invention. In this variation, the first patterned semiconductor layer 206 includes a plurality of fin portions 206a and at least one landing pad portion 206b. The connection pad portion 206b is electrically connected to at least one end of the front and rear ends of each fin portion 206a as shown in FIG. 3, and after the completion of the fabrication of the multi-gate transistor element, the source portion can be formed on the connection pad portion 206b. Bungee contact plug. Please refer to FIG. 2 again. When the preferred embodiment is applied to the bulk substrate, the first patterned semiconductor layer 206 is formed on the bulk substrate, and the bottom of the first patterned semiconductor layer 206 and the semiconductor substrate 200. The portion to be contacted, as circled by the circle 206c in FIG. 2, may selectively form a recess (not shown) or even form a pad oxide layer at the recess to reduce the first patterned semiconductor layer 206 and The area in which the bulk substrate contacts and thereby reduces leakage current.

Please refer to Figure 4. Next, a dielectric layer (not shown), a gate forming layer (not shown), and a patterned hard mask 213 are sequentially formed on the semiconductor substrate 200. Subsequently, the dielectric layer and the gate forming layer are patterned, and a gate dielectric layer 210 and a gate layer 212 covering a portion of the first patterned semiconductor layer 206 are formed on the semiconductor substrate 200. As shown in FIG. 4, the gate dielectric layer 210 and the gate layer 212 extend in a direction perpendicular to the extending direction of the fin portion 206a, and the gate dielectric layer 210 and the gate layer 212 cover a portion of the fin portion. The side wall of 206a. The gate dielectric layer 210 may comprise a dielectric material such as cerium oxide (SiO), cerium nitride (SiN), cerium oxynitride (SiON) or the like. In the preferred embodiment, the gate dielectric layer 210 may further comprise a high-k material, such as hafnium oxide (HfO), hafnium niobate (HfSiO) or aluminum, zirconium, hafnium, etc. Metallic metal oxides or metal silicates, etc., but are not limited thereto. In addition, when the gate dielectric layer 210 of the preferred embodiment is made of a high-K material, the present invention can be integrated with a metal gate process to provide sufficient control for matching the high-K gate dielectric layer. electrode. Accordingly, the gate layer 212 can be made of a different material depending on the gate-first process or the gate-last process of the metal gate. For example, when the preferred embodiment is integrated with the front gate process, the gate layer 212 may comprise a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), or the like. Alloys, metal nitrides such as tantalum nitride (TaN), titanium nitride (TiN), molybdenum nitride (MoN), etc., metal carbides such as tantalum carbide (TaC). And the selection of the metals is based on the principle of the conductive form of the multi-gate transistor element to be obtained, that is, the metal satisfying the required work function of the N-type or P-type transistor is the selection principle, and the gate layer 212 It may be a single layer structure or a multi-layered structure. When the preferred embodiment is integrated with the back gate process, the gate layer 212 acts as a dummy gate, which may comprise a semiconductor material such as a polysilicon or the like.

Please continue to see Figure 4. In the preferred embodiment, since the top of the first patterned semiconductor layer 206 is covered by the patterned hard mask 208, a channel region cannot be formed. In other words, the channel region of the transistor in the preferred embodiment is formed where only the gate layer 212 and the gate dielectric layer 210 cover the fin portion 206a, that is, the two opposite layers of the first patterned semiconductor layer 206. Whereas the sidewalls, the multi-gate transistor component provided by the preferred embodiment is a double-gate transistor component.

Please refer to Figure 5. After the fabrication of the gate dielectric layer 210 and the gate layer 212 is completed, the preferred embodiment can form a source/drain in the first patterned semiconductor layer 206 by using oblique ion implantation or the like as needed. The source/drain extension region 214 (shown in Figure 7). After forming the source/drain extension region 214, the sidewalls 215 are formed on the opposite sidewalls of the gate layer 212 and the gate dielectric layer 210. The sidewall spacers 215 may be a single layer structure or a composite layer structure.

Please continue to see Figure 5. Next, a portion of the first patterned semiconductor layer 206 is removed using a suitable etching method to form a second patterned semiconductor layer 216. It is worth noting that since the top of the first patterned semiconductor layer 206 is still protected by the patterned hard mask 208, only its sidewalls are removed. As shown, the width of the second patterned semiconductor layer 216 obtained after the etching of the lines ₅₂ d of FIG patterned hard mask 208 is smaller than the width of the first patterned semiconductor layer 206 d _1. For example, the width d ₂ of the second patterned semiconductor layer 216 is smaller than the width d ₁ of the first patterned semiconductor layer 206 under the gate dielectric layer 210 and the gate layer 212 by 100 to 200 angstroms (angstrom). ), but not limited to this.

Please refer to Figure 6. After forming the second patterned semiconductor layer 216, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 218 on the surface of the second patterned semiconductor layer 216, and the epitaxial layer 218 is used as the epitaxial layer 218. Source/drain of a multi-gate transistor component. So far, the fabrication of the dual gate transistor element 250 provided by the preferred embodiment has been completed. In the SEG process, the epitaxial layer 218 only grows along the surface of the germanium material. Therefore, in the preferred embodiment, the epitaxial layer 218 is grown only on the sidewall of the second patterned semiconductor layer 216. In addition, in the SEG process, a material having a lattice constant different from a lattice constant of the second patterned semiconductor layer 216 may be added according to a conductivity type of the multi-gate transistor element, and a doping having a conductivity type is added to the SEG process. Qualitative (dopant). In detail, when the double gate transistor device 250 of the preferred embodiment is a PMOS transistor device, germanium (SiGe) and boron (B) are added in the SEG process, so the epitaxial layer 218 includes SiGeB. , wherein the concentration of strontium is about 30-50%. When the double gate transistor element 250 of the preferred embodiment is an NMOS transistor component, bismuth carbon (SiC) and phosphorus (P) or arsenic (As) are added in the SEG process, so the epitaxial layer 218 is Contains SiCP in which the concentration of carbon is less than 3%. According to the preferred embodiment, since the doping material having the conductive type is simultaneously added in the SEG process, the epitaxial layer 218 is formed without using any ion implantation process to dope the doping required for the source/drain. quality.

In addition, in the preferred embodiment, after the second patterned semiconductor layer 216 is formed, an impurity pattern doping is implanted into the second patterned semiconductor layer 216 by using an ion implantation process. A doped region (not shown) is formed in the second patterned semiconductor layer 216. Then, the SEG process is performed to form an epitaxial layer 218 on the surface of the second patterned semiconductor layer 216, and a material having a lattice constant different from the lattice constant of the second patterned semiconductor layer 216 is added in the SEG process. The epitaxial layer 218 serves as the source/drain of the multi-gate transistor component.

Please refer to FIG. 6 and FIG. 7 , wherein FIG. 7 is a schematic cross-sectional view taken along line A-A' of FIG. 6; in addition, in order to clearly show the height of the epitaxial layer 218 and the gate dielectric layer 210 In the relationship, the gate dielectric layer 210 and the gate layer 212 and the first patterned semiconductor layer 206 which are originally covered by the sidewall spacers 215 in FIG. 6 are indicated by broken lines. In addition, in FIG. 7, the surface of the first patterned semiconductor layer 206 is further indicated by a broken line 211 for comparison between the gate dielectric layer 210, the second patterned semiconductor layer 216, and the epitaxial layer 218. Baseline. As shown in FIG. 6 and FIG. 7, in the preferred embodiment, the epitaxial layer 218 protrudes from the second patterned semiconductor layer 216, and more importantly, the surface of the epitaxial layer 218 also protrudes from the gate. Dielectric layer 210. Based on the surface 211 of the first patterned semiconductor layer 206, it can be seen that the surface of the epitaxial layer 218 has a height difference D from the gate dielectric layer 210, and the height difference D is about 50-200 angstroms. The surface of the crystal layer 218 protrudes 50-200 angstroms from the surface of the gate dielectric layer 210. Since the width d _{2 of the} second patterned semiconductor layer 216 is smaller than the width d _{1 of the} first patterned semiconductor layer 206, the surface 211 of the first patterned semiconductor layer 206 is used as a reference, and it is known that the epitaxial layer 218 of the present invention is Lower than the first patterned semiconductor layer 206, that is, growing below the gate dielectric layer 210, whereby the carrier of the channel region can be improved by the stress provided by the epitaxial layer 218 formed on the fin portion 206a. Mobility. In addition, since the epitaxial layer 218 protrudes from the surface of the second patterned semiconductor layer 216 and is higher than the gate dielectric layer 210, the epitaxial layer 218 provided in the preferred embodiment can be used as a double gate. The raised source/drain of the crystal 250. The protruding epitaxial layer 218 can further provide sufficient space for consumption in the subsequent metal silicide process, avoiding excessive consumption of the epitaxial layer 218 by the metal telluride and drilling into the second patterned semiconductor layer 216 or the first pattern. The semiconductor layer 206 causes an adverse effect such as electric leakage.

After the double gate transistor element 250 provided in the preferred embodiment is completed, an inter-layer dielectric (ILD) layer (not shown) may be formed on the semiconductor substrate 200. As described above, when the preferred embodiment is integrated with the gate process after the metal gate, the gate layer 212 as a dummy gate can be removed after forming the inner dielectric layer, and the gate layer 212 is removed therein. The electrical requirements of the dual gate transistor component 250 are filled with a metal that satisfies the required work function of the N-type or P-type transistor, and a metal with a low resistance or better hole-filling capability. In addition, the preferred embodiment can also be integrated with the high-K last process, that is, the gate dielectric layer 210 is removed after the gate layer 212 is removed, and the gate dielectric layer 210 is removed. A gate dielectric layer having a high dielectric constant material is formed. Since the above processes are well known to those skilled in the art, they will not be described again.

According to the method for fabricating the multi-gate transistor device provided in the first preferred embodiment, the epitaxial layer 218 including the doped material having the conductivity type is formed on the surface of the second patterned semiconductor layer 216 by using an SEG process. As the raised source/drain of the double gate transistor element 250. Since the method for fabricating the multi-gate transistor device provided by the preferred embodiment replaces the conventional ion implantation process and the tempering process by the SEG process, the lattice of the second patterned semiconductor layer 216 can be prevented from being damaged. And can avoid the adverse effects of the high thermal budget such as the tempering process on the gate dielectric layer 210. In addition, the epitaxial layer 218 formed on the surface of the second patterned semiconductor layer 216 in the first preferred embodiment provides stress to the channel region of the dual gate transistor element 250. Compared with the prior art, the first patterned semiconductor layer 206 is not removed, and the epitaxial layer higher than the gate dielectric layer 210 is formed directly on the surface of the first patterned semiconductor layer 206. The first preferred embodiment The epitaxial layer 218 is grown lower than the first patterned semiconductor layer 206, that is, lower than the gate dielectric layer 210, and is higher than the gate dielectric layer 210, so that the channel region can be effectively enhanced. The sub-mobility, in turn, further enhances the performance of the dual gate transistor element 250.

Please refer to FIG. 8 to FIG. 10 , and FIG. 8 to FIG. 10 are schematic diagrams showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention. It is to be noted that the material selection of each component in the second preferred embodiment is the same as that of the first preferred embodiment, so that those skilled in the art can learn from the first preferred embodiment. Therefore, the materials are not described in the second preferred embodiment. In the second preferred embodiment, the same steps and the description of the components of the first preferred embodiment will be described with reference to the drawings and the reference numerals of the first preferred embodiment. Please refer to Figure 2 first. The preferred embodiment first provides a semiconductor substrate 200 that can include a germanium insulating substrate. As described above, the SOI substrate may sequentially include a substrate 202, a bottom oxide layer 204, and a semiconductor layer (not shown) formed on the bottom oxide layer 204, such as a single crystal structure. Floor. However, in order to provide better heat dissipation and grounding effects, and to help reduce cost and suppress noise, the semiconductor substrate 200 provided by the preferred embodiment may include a germanium substrate. Subsequently, a patterned hard mask 208 is formed on the semiconductor substrate 200 for defining at least one fin portion of the multi-gate transistor element.

Please refer to Figures 2 and 8. Next, an etching process is performed to remove the semiconductor layer of the semiconductor substrate 200, and at least one first patterned semiconductor layer 206 is formed on the semiconductor substrate 200. The first patterned semiconductor layer 206 can include at least one fin portion 206a as shown in FIG. In addition, the preferred embodiment can also form a first patterned semiconductor layer 206 having a plurality of fin portions 206a and at least one connection pad portion 206b as shown in FIG. Next, as shown in FIG. 8, after the first patterned semiconductor layer 206 is formed, the patterned hard mask 208 is removed, and then a rounding step is performed to fillet the first patterned semiconductor. The top of the layer 206, in particular the top of the rounded fin portion 206a, obtains a first patterned semiconductor layer 306 having a curved top as shown in FIG. 8 for use as a multi-gate transistor element Fin portion 306a. As described above, the fin portion 306a having a width D ₁ and a height h _1, and the width D ₁ has a height h ₁ ratio, the ratio may be 1: 1 to 1: 1.5. Similarly, when the preferred embodiment is applied to a bulk substrate, the first patterned semiconductor layer 306 is formed on the bulk substrate, and the portion of the bottom of the first patterned semiconductor layer 306 that is in contact with the semiconductor substrate 200, such as The portion circled by the circle 306c in FIG. 8 forms a recess (not shown), or even a pad oxide layer is formed at the recess to reduce the area of contact of the first patterned semiconductor layer 306 with the bulk substrate, thereby reducing Leakage current.

Please continue to see Figure 8. Next, a dielectric layer (not shown), a gate forming layer (not shown) and a patterned hard mask 213 are sequentially formed on the semiconductor substrate 200, and then the dielectric layer and the gate are patterned by the gate layer. A gate is formed on the semiconductor substrate 200 to form a gate dielectric layer 210 and a gate layer 212 covering a portion of the first patterned semiconductor layer 306. As shown in FIG. 8, the gate dielectric layer 210 and the gate layer 212 extend in a direction perpendicular to the extending direction of the fin portion 306a, and the gate dielectric layer 210 and the gate layer 212 cover a portion of the fin portion. Side wall of 306a. It should be noted that in the preferred embodiment, since the patterned hard mask 208 has been removed, the transistor channel region is formed in any of the gate layer 212 and the gate dielectric layer 210 to cover the fin portion 306a. Where is the opposite sidewalls of the first patterned semiconductor layer 306 and its curved top. It can be seen that the multi-gate transistor component provided by the preferred embodiment is a tri-gate transistor component. In addition, it is noted that the three-gate transistor component provided by the preferred embodiment is more avoidable because the top of the first patterned semiconductor layer 306 is rounded and has a rounded curved top. 1 shows the problem of sharp corner discharge of a fin-shaped tantalum film with a rectangular cross section of a fin field effect transistor.

Please refer to Figure 9. After the fabrication of the gate dielectric layer 210 and the gate layer 212 is completed, the preferred embodiment can form a source/drain extension region in the first patterned semiconductor layer 306 by ion implantation or the like as needed. (shown in Figure 7) 214. After the source/drain extension region 214 is formed, sidewalls (also shown in FIG. 7) 215 are formed on the opposite sidewalls of the gate layer 212 and the gate dielectric layer 210, and the sidewall spacers 215 may be a single layer. Structure or composite layer structure. Next, a portion of the first patterned semiconductor layer 306 is removed by a suitable etching method to form another second patterned semiconductor layer 316 having a height h ₃ and a width d ₃ . It should be noted that in the preferred embodiment, the sidewalls and the top of the first patterned semiconductor layer 306 are etched, so that the etched second patterned semiconductor layer 316 is as shown in FIG. 9 and has a height h _{3 .} The width d ₃ is smaller than the height h ₁ and the width d _{1 of} the first patterned semiconductor layer 306. For example, the height h ₃ of the second patterned semiconductor layer 316 is 50 to 100 angstroms smaller than the height h _{1 of the} first patterned semiconductor layer 306; and the width d ₃ is greater than the width d of the first patterned semiconductor layer 306. ₁ small 100 to 200 angstroms, but is not limited to this. In general, the size of the second patterned semiconductor layer 316 is smaller than the size of the first patterned semiconductor layer 306 covered by the gate dielectric layer 210 and the gate layer 212. As shown in FIG. 9, in order to clearly disclose the difference in height and width between the second patterned semiconductor layer 316 and the first patterned semiconductor layer 306, the first patterned semiconductor layer 306 is indicated by a broken line in FIG.

Please refer to Figure 10. After the second patterned semiconductor layer 316 is formed, an SEG process is performed to form an epitaxial layer 318 on the surface of the second patterned semiconductor layer 316. In the SEG process, the epitaxial layer 318 is grown along the surface of the germanium material. Therefore, in the preferred embodiment, the epitaxial layer 318 is grown on both sidewalls and the curved top of the second patterned semiconductor layer 316 to serve as a multi-gate. Source/drain of the transistor component. So far, the fabrication of the three-gate transistor element 350 provided by the preferred embodiment has been completed. As described above, in the SEG process, a material having a lattice constant different from that of the second patterned semiconductor layer 316 can be added according to the conductivity type of the multi-gate transistor element, and at the same time, the conductive is added to the SEG process. Type of dopant. According to the preferred embodiment, since the doping material having the conductive type is simultaneously added in the SEG process, the epitaxial layer 318 is formed without using any ion implantation process to dope the doping required for the source/drain. quality.

As described above, in addition, in the preferred embodiment, after the second patterned semiconductor layer 316 is formed, the dopant having the conductive type is implanted into the second pattern by using an ion implantation process. In the semiconductor layer 316, doped regions (not shown) are formed in the second patterned semiconductor layer 316. Subsequently, the SEG process is performed to form an epitaxial layer 318 on the surface of the second patterned semiconductor 316, and a material having a lattice constant different from the lattice constant of the second patterned semiconductor layer 316 is added in the SEG process. The epitaxial layer 318 acts as the source/drain of the multi-gate transistor component.

In addition, reference may also be made to FIGS. 10 and 7, wherein FIG. 7 is a schematic cross-sectional view taken along line A-A' in FIG. It should be noted that the surface of the first patterned semiconductor layer 306 is further indicated by a broken line 211 in FIG. 7 to serve as a gate dielectric layer 210, a second patterned semiconductor layer 316, and an epitaxial layer 318. The height is compared to the baseline. In the preferred embodiment, the epitaxial layer 318 is protruded from the second patterned semiconductor layer 316. More importantly, the surface 211 of the first patterned semiconductor layer 306 is used as a reference, and the epitaxial layer of the present invention is known. The surface of 318 is higher than the gate dielectric layer 210, and the surface of the epitaxial layer 318 has a height difference D from the gate dielectric layer 210. The height difference D is also 50-200 angstroms, that is, the epitaxial layer. The surface of 318 is 50-200 angstroms above the surface of gate dielectric layer 210. Since the width d _{3 of the} second patterned semiconductor layer 316 is smaller than the width d _{1 of the} first patterned semiconductor layer 306, the surface 211 of the first patterned semiconductor layer 306 is used as a reference, and it is known that the epitaxial layer 318 is Lower than the first patterned semiconductor layer 306, ie, lower than the gate dielectric layer 210, until it is higher than the gate dielectric layer 210. Accordingly, the carrier mobility of the channel region can be improved by the stress provided by the epitaxial layer 318 formed on the fin portion 306a. In addition, since the epitaxial layer 318 is grown up to be higher than the gate dielectric layer 210, the epitaxial layer 318 provided in the preferred embodiment can be used as the elevated source/drain of the three-gate transistor 350. In addition, the raised epitaxial layer 318 can provide sufficient space for consumption in the subsequent metal silicide process, avoiding the metal telluride excessively consuming the epitaxial layer 318 and drilling into the second patterned semiconductor layer 316 or the first The patterned semiconductor layer 306 causes an adverse effect such as electric leakage.

As described above, after completing the three-gate transistor 350 element provided in the preferred embodiment, an inner dielectric layer (not shown) may be formed on the semiconductor substrate 200. As described above, when the preferred embodiment is integrated with the gate process after the metal gate, the gate layer 212 as a dummy gate can be removed after forming the inner dielectric layer, and the gate layer 212 is removed therein. The electrical requirements of the dual-gate transistor components are filled with metals that meet the required work function requirements of the N-type or P-type transistors, and conductors such as metals with low resistance values or better hole-filling capabilities. In addition, the preferred embodiment can also be integrated with the back gate dielectric layer process, that is, the gate dielectric layer 210 is removed after the gate layer 212 is removed, and a high dielectric is formed therein. A gate dielectric layer of a constant material. Since the above processes are well known to those skilled in the art, they are not described herein.

According to the second preferred embodiment of the present invention, a method for fabricating a multi-gate transistor device is formed on the surface of the second patterned semiconductor layer 316 by using an SEG process to form an epitaxial layer 318 comprising a dopant having a conductivity type. As the elevated source/drain of the three-gate transistor element 350. Since the method for fabricating the multi-gate transistor device provided by the preferred embodiment replaces the conventional ion implantation process and the tempering process by using the SEG process, the lattice of the second patterned semiconductor layer 316 can be prevented from being damaged. And can avoid the adverse effects of the high thermal budget such as the tempering process on the gate dielectric layer 210. In addition, the epitaxial layer 318 formed on the surface of the second patterned semiconductor layer 316 in the second preferred embodiment can provide stress to the channel region of the three-gate transistor element 350. Compared with the prior art, the first patterned semiconductor layer 306 is not removed, and the epitaxial layer higher than the gate dielectric layer 210 is formed directly on the surface of the first patterned semiconductor layer 306. The second preferred embodiment The epitaxial layer 318 is grown lower than the first patterned semiconductor layer 306, that is, lower than the gate dielectric layer 210, and is higher than the gate dielectric layer 210, so that the channel region can be effectively enhanced. The sub-mobility, in turn, further enhances the performance of the three-gate transistor element 350.

In summary, the method for fabricating a multi-gate transistor according to the present invention is to form an epitaxial layer containing a doped type having a conductivity type on the surface of the second patterned semiconductor layer by using an SEG process. Source/drain of a multi-gate transistor component. Since the method for fabricating the multi-gate transistor device provided by the present invention replaces the conventional ion implantation process and the tempering process by the SEG process, the lattice of the second patterned semiconductor layer can be avoided, and the back can be avoided. The adverse effects of high heat budgets such as fire processes on the dielectric layer. In addition, by the epitaxial layer formed on the surface of the second patterned semiconductor layer, stress can be provided to the channel region of the multi-gate transistor element, so that the carrier mobility of the channel region can be further improved, thereby further improving the multi-gate current. The performance of the crystal element.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Fin field effect transistor component

102. . . Overlying insulating substrate

104. . . High dielectric constant insulating layer

106. . . Gate

108. . . Source/bungee

200. . . Semiconductor substrate

202. . .矽 base

204. . . Bottom oxide layer

206. . . First patterned semiconductor layer

206a. . . Fin part

206b. . . Connection pad section

206c. . . Circle

208. . . Patterned hard mask

210. . . Gate dielectric layer

211. . . First patterned semiconductor layer surface

212. . . Gate layer

213. . . Patterned hard mask

214. . . Source/drain extension

215. . . Side wall

216. . . Second patterned semiconductive layer

218. . . Epitaxial layer

250. . . Double gate transistor component

306. . . First patterned semiconductor layer

306a. . . Fin part

306c. . . Circle

316‧‧‧Second patterned semiconductor layer

318‧‧‧ epitaxial layer

350‧‧‧Three-gate electro-optical components

Figure 1 is a perspective view of a conventional FinFET component;

2 to 7 are schematic views of a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention, wherein FIG. 3 is a schematic view showing a variation of the preferred embodiment;

Figure 7 is a schematic cross-sectional view taken along line A-A' in the sixth and tenth views;

8 to 10 are schematic views showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention.

206/306. . . First patterned semiconductor layer

210. . . Gate dielectric layer

212. . . Gate layer

214. . . Source/drain extension

215. . . Side wall

216/316. . . Second patterned semiconductor layer

218/318. . . Epitaxial layer

250. . . Double gate transistor component

350. . . Three-gate transistor component

Claims (16)

A method of fabricating a multi-gate transistor device, comprising: providing a semiconductor substrate having a patterned hard mask formed thereon; removing a portion of the semiconductor substrate through the patterned hard mask to form a first Patterning the semiconductor layer; removing the patterned hard mask and rounding the first patterned semiconductor layer; sequentially forming a gate dielectric layer and a gate layer on the semiconductor substrate, and The gate dielectric layer and the gate layer cover a portion of the first patterned semiconductor layer; removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer; and performing a selective epitaxial growth process, An epitaxial layer is formed on the surface of the second patterned semiconductor layer. The method of claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The method of claim 1, wherein the gate dielectric layer comprises a high dielectric constant material. The method of claim 1, wherein the height and width of the second patterned semiconductor layer are less than the height and width of the first patterned semiconductor layer. The method of claim 1, wherein the first patterned semiconductor layer comprises at least one fin portion. The method of claim 1, wherein the first patterned semiconductor layer comprises at least one fin portion and a landing pad portion. The method of claim 1, wherein the epitaxial layer protrudes from the second patterned semiconductor layer, and a surface of the epitaxial layer is higher than the gate dielectric layer. The method of claim 7, wherein the surface of the epitaxial layer is higher than the gate dielectric layer by about 50-200 angstroms. The method of claim 1, wherein the epitaxial layer comprises a dopant having a conductivity type. The method of claim 9, wherein the epitaxial layer is at least A dopant comprising germanium (SiGe) and a p-type conductivity. The method of claim 10, wherein the dopant of the P-type conductivity comprises boron (B). The method of claim 9, wherein the epitaxial layer comprises at least tantalum carbon (SiC) and an N-type conductivity dopant. The method of claim 12, wherein the dopant of the N-type conductivity comprises phosphorus (P) or arsenic (As). The method of claim 9, wherein the doping is added to the SEG process. The method of claim 9, further comprising an ion implantation process for forming the dopant in the second patterned semiconductor layer after forming the second patterned semiconductor layer. A method of fabricating a multi-gate transistor device, comprising: providing a semiconductor substrate having a patterned hard mask formed thereon; removing a portion of the semiconductor substrate through the patterned hard mask to form at least one a patterned semiconductor layer; Forming a gate dielectric layer and a gate layer on the semiconductor substrate, the gate dielectric layer and the gate layer covering a portion of the patterned hard mask and a portion of the first patterned semiconductor layer, And the patterned hard mask is interposed between the gate dielectric layer and the top of the first patterned semiconductor layer; removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer; A selective epitaxial growth process is performed to form an epitaxial layer on the surface of the second patterned semiconductor layer.