TWI436342B - Control method and image display system utilizing the same - Google Patents

Description

Control method and image display system

The present invention relates to a control method, and more particularly to a control method for a display panel.

Because the image tube has the characteristics of excellent image quality and low price, it has been adopted as a display for televisions and computers. However, with the advancement of technology, new flat-panel displays have been developed. The main advantage of a flat panel display is that when the flat panel display has a large size display panel, the total volume of the flat panel display does not change significantly.

The invention provides a control method suitable for a pixel unit. The pixel unit is coupled to a gate line and a data line, and includes a storage capacitor and a liquid crystal capacitor. The storage capacitor and the liquid crystal capacitor are connected in series between a common line and a control line. The control method of the present invention includes, during a first period, generating a scan signal to the gate line, and making the level of the common line and the control line equal to a ground level; and during a second period, The level of the common line changes from the ground level to a first level, and the level of the control line changes from the ground level to a second level.

The invention further provides an image display system comprising a gate driver, a pixel unit and a first power module. The gate driver generates a scan signal during a first period. The pixel unit has a storage capacitor and a liquid crystal capacitor. The storage capacitor and the liquid crystal capacitor are connected in series between a common line and a control line. The first power module is used to control the level of the common line and the control line. During the first period, the level of the common line and the control line is equal to a ground level. During a second period, the level of the common line changes from the ground level to a first level, and the level of the control line changes from the ground level to a second level.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Figure 1 is a schematic illustration of an image display system in accordance with the present invention. As shown, the image display system 100 includes a conversion device 110 and a display panel 130. The conversion device 110 converts the level or format of the input voltage V _IN to produce an output voltage V _OUT . The display panel 130 receives the output voltage V _OUT and presents an image. The display panel 130 can be a liquid crystal display panel.

In the present embodiment, the output voltage V _OUT is a direct current (DC) voltage. The invention does not limit the type of input voltage V _IN . In other possible embodiments, the input voltage V _IN is an alternating current (AC) voltage or a direct current voltage. In addition, the image display system 100 can be a personal digital assistant (PDA), a cellular phone, a digital camera, a television, a global positioning system (GPS), a vehicle display, an aerial display, a digital photo frame, Notebook or desktop computer.

Figure 2 is a schematic illustration of a display panel in accordance with the present invention. As shown, the display panel 130 includes a gate driver 210, a source driver 230, a power module 250, 270, a timing controller 290, and a pixel unit (pixel). ) P ₁₁ ~P _mn .

In a possible embodiment, the output voltage V _OUT generated by the conversion device 110 can be such that the gate driver 210, the source driver 230, the power module 250, 270, the clock controller 290, or the pixel unit P ₁₁ ~ P _Mn normal action. In this example, the display panel 130 can further include a voltage conversion module (not shown) for converting the output voltage V _OUT into other components (such as the gate driver 210, the source driver 230, and the power module 250, 270). The level required by the clock controller 290 or the pixel unit P ₁₁ ~P _mn ).

The gate driver 210 is configured to generate a scan signal to the gate lines GL ₁ to GL _n . In this embodiment, before the power module 250 has output voltage to the common lines COL ₁ to COL _n and the control lines (CS lines) CSL ₁ to CSL _n , the gate driver 210 first generates a scan signal to the gate. Polar line GL ₁ ~ GL _n . In a possible embodiment, after the gate driver 210 generates the scan signal, the power module 250 generates a common voltage and a control voltage, wherein the common voltage is supplied to the common lines COL ₁ to COL _n , and the control voltage is supplied to the control. Line CSL ₁ ~ CSL _n .

In addition, in the present embodiment, the gate driver 210 receives the gate levels VGH and VGL, and generates a scan signal to the gate lines GL ₁ to GL _n according to the start signal STV. When the level of the gate line is equal to the gate level VGH, the corresponding pixel unit receives the data signal. When the level of the gate line is equal to the gate level VGL, the corresponding pixel unit stops receiving the data signal.

In the present embodiment, the gate positions VGH and VGL are provided by the power module 270, but are not intended to limit the present invention. In other possible embodiments, the gates VGH and VGL may be generated by the power module 250. Therefore, the power modules 250 and 270 can be integrated into an integrated circuit.

Further, in the present embodiment, the start signal STV is generated by the clock controller 290, but is not intended to limit the present invention. Start signal STV is used to enable the gate driver 210, so that the gate driver 210 generates the scan start signal to the gate line GL ₁ ~ GL _n.

The source driver 230 is configured to generate a data signal to the data lines DL ₁ to DL _m . In this embodiment, after the power module 250 generates the common voltage to the common lines COL ₁ to COL _n and generates the control voltage to the control lines CSL ₁ to CSL _n , the source driver 230 generates the data signal to the data line DL ₁ ~ DL _m .

The pixel units P ₁₁ to P _{mn are} coupled to the common lines COL ₁ to COL _n and the control lines CSL ₁ to CSL _n , and receive the data lines DL ₁ to DL _m according to the scanning signals on the gate lines GL ₁ to GL _n . The transmitted data signal is then displayed according to the received data signal. Since the circuit structures of the pixel units P ₁₁ to P _mn are the same, FIG. 2 shows only the circuit structure of the single pixel unit (P ₁₁ ).

In the present embodiment, the pixel unit P ₁₁ has switching transistors T1, T2, a storage capacitor Cst, and a liquid crystal capacitor Clc. The switching transistors T1 and T2 receive the data signal according to the scanning signal, and transmit the data signal to the storage capacitor Cst and the liquid crystal capacitor Clc. Storage capacitor Cst and the liquid crystal capacitor Clc connected in series between the common line COL ₁ and the control line CSL _1.

The present invention does not limit the circuit structure of the pixel unit, as long as it is a pixel unit having a storage capacitor Cst and a liquid crystal capacitor Clc, and the storage capacitor Cst and the liquid crystal capacitor Clc are connected in series between a common line and a control line, Both can be used as the pixel unit shown in Fig. 2.

In addition, in the present embodiment, each column (horizontal direction) of pixel units is coupled to different common lines and control lines. For example, the pixel units of the pixel units P ₁₁ , P ₂₁ , . . . , P _m1 are coupled to the common line COL ₁ and the control line CSL ₁ . The pixel units of the pixel units P ₁₂ , P ₂₂ , . . . , P _m2 are coupled to the common line COL ₂ and the control line CSL ₂ . In other possible embodiments, all of the pixel units are coupled to the same common line and control line.

The power module 250 controls the levels of the common lines COL ₁ to COL _n and the control lines CSL ₁ to CSL _n . Fig. 3 is a timing chart showing the control of the display panel according to the present invention. During the period P ₁ , the voltage levels of the common lines COL ₁ to COL _n and the control lines CSL ₁ to CSL _n are equal to the ground level GND (eg, 0 V). During this time, the gate driver 210 is enabled, and therefore, the scan signals (such as V _GL1 GL _GLn ) on the gate lines GL ₁ GL GL _n may be the gate level VGH or VGL. The gate level VGL can be equal to the ground level GND. During P _1, yet the source driver 230 generates the data signals to the data lines DL ₁ ~ DL _m, so the data lines DL ₁ ~ DL _m of the level V _{DL1 ~ DLm} at a low level (e.g., ground level GND).

During the period P ₂ , the power module 250 controls the levels of the common lines COL ₁ to COL _n and the control lines CSL ₁ to CSL _n such that the levels of the common lines COL ₁ to COL _n are low (eg, the ground level GND). Change to the first level (such as VCOM), and change the level of the control lines CSL ₁ ~ CSL _n from the low level to the second level (such as VCSH). In this embodiment, the levels of the common lines COL ₁ to COL _n and the control lines CSL ₁ to CSL _n are simultaneously changed (from a low level to a first level and a second level). In other possible embodiments, the first level may be less than or equal to the second level.

In the present embodiment, the period P ₂ has a reset period P _R and a pre-set period P _S . During the reset period P _R , the power module 250 sets the levels of the control lines CSL ₁ -CSL _n to a third level. In this embodiment, the third level is equal to the second level VCSH. In another embodiment, the third level can be equal to the ground level GND.

During the preset period P _S , the power module 250 controls the levels of the control lines CSL ₁ to CSL _n according to the polarity signal S _P . Figure 4A shows the relationship between the polarity signal S _P and the level of the control line. The symbol V _GL represents the scan signal on a certain gate line. The symbol V _CSL represents the level on the control line CSL. In a possible embodiment, the levels of the different control lines correspond to different polarity signals S _P . In the present embodiment, the single polarity signal S _{P is taken} as an example.

During the period P ₁ , the gate driver 210 generates a scan signal. Therefore, the scan signal of the gate line has a pulse. At this time, the level V _{CSL of the} control line CSL remains at a low level. During the reset period P _R , the control line CSL will be pulled up to a high level by the low level, so that the level difference between the control line and the common line can be prevented from being excessively large.

Next, during the set period P _S , the polarity signal S _P is at the first polarity level (high level), which means that the source driver 230 supplies the data signal to be supplied to the pixel unit as positive polarity. Therefore, when the gate driver 210 generates the scan signal again, the level V _{CSL of the} control line CSL changes from a high level to a low level (as indicated by the period P _SA1 ). Since the data signal is positive, the level V _{CSL of the} control line CSL changes from a low level to a high level (as indicated by the period P _SA2 ).

Conversely, when the polarity signal S _P is the polarity of a second level (e.g., a low level, as shown in FIG. 4B P _R of the second period), represents the source driver 230 provides the data signals to the pixel unit of a negative polarity. Therefore, when the gate driver 210 generates the scan signal again (as indicated by the period P _SB1 ), the level V _{CSL of the} control line CSL is maintained at a high level. Since the data signal is negative, during the period P _SB2 , the level V _{CSL of the} control line CSL changes again to the low level.

Please refer to FIG. 3, P _3, the source driver 230 provides the data signals to the pixel unit P ₁₁ ~ P _mn period. Therefore, the levels V _{DL1 to DLm of the} data lines DL ₁ to DL _m start to change. In a possible embodiment, the length of the period P ₁ is equal to the time at which the pixel units P _{11 to} P _mn present a frame. For example, if the pixel units P ₁₁ ~P _mn can display 75 pictures in 1 second, the time of the period P ₁ is approximately equal to second. In the present embodiment, the period P ₃ is located after the preset period P _S .

As can be seen from FIG. 3, when control signals (such as the scan signals V _{GL1 GL GLn} generated by the gate driver 210 or the signals STV, CKV) are generated, the control lines CSL ₁ to CSL _n and the common lines COL ₁ to COL _{n are} generated. The level is low, and then after one screen time, the control lines CSL ₁ ~ CSL _n and the common lines COL ₁ ~ COL _n are set (eg, from a low level to a high level). Therefore, the pixel units P ₁₁ to P _{mn can} be normally operated in accordance with the respective control signals (such as the scanning signal, the data signal) and the voltage levels (levels on the common line and the control line).

Further, as shown in Fig. 3, in the period P ₀ , only the gate positions VGH and VGL are generated. During this period, the gate driver 210 has not generated the scan signal to the gate lines GL ₁ to GL _n , so the levels V _GL1 GL _GLn on the gate line are low.

Figure 5A is a possible embodiment of a control method in accordance with the present invention. The control method according to the invention is applicable to a pixel unit. The pixel unit is coupled to a gate line and a data line, and includes a storage capacitor and a liquid crystal capacitor. The storage capacitor and the liquid crystal capacitor are connected in series between a common line and a control line.

First, a scan signal is generated to the gate line, and the level of the common line and the control line is equal to a ground level (step S510). In a possible embodiment, by enabling a gate driver, a scan signal can be provided to the gate line.

Then, the level of the common line is changed from the ground level to a first level, and the level of the control line is changed from the ground level to a second level (step S530). In an embodiment, the levels of the common line and the control line are simultaneously converted from the ground level to the first and second levels. The first position can be equal to or less than the second level.

In step S530, there is a reset period and a preset period. During the reset period, the level of the control line is set to a third level. The third level can be equal to the ground level or the second level. During the preset period, the level of the control line is controlled according to a polarity signal. When the polarity signal is at a first polarity level, it indicates that the data signal to be transmitted by the data line is positive. Therefore, the level of the control line is equal to the ground level. When the polarity signal is a second polarity level, it indicates that the data signal to be transmitted by the data line is negative. Therefore, the level of the control line is equal to the second level, wherein the second level is greater than the ground level.

It can be seen from the above that when the gate line starts to transmit the scan signal to the pixel unit (ie, step S510), neither the control line nor the common line transmits the voltage level to the pixel unit, and after the scan signal is transmitted, the control line and the common line The line transmits the voltage level to the pixel unit. Therefore, the pixel unit malfunction can be avoided.

In addition, in step S530, the level of the control line is reset first (for example, reset to a high level or a low level), and then the level of the control line is controlled according to the polarity signal, so that the control line and the common line can be avoided. The pressure difference between them is too large.

Figure 5B is another possible embodiment of a control method in accordance with the present invention. Fig. 5B is similar to Fig. 5A except that step 5B has steps S500 and S550. For the sake of brevity, only steps S500 and S550 will be described below.

Before the gate driver is enabled, a first gate level and a second gate level are generated to the gate driver (step S500). Therefore, the scan signal generated by the gate driver can be varied between the first and second gate levels. When the level of the gate line is equal to the first gate level, the pixel unit can receive the signal on the data line. When the level of the gate line is equal to the second gate level, the pixel unit stops receiving the signal on the data line. In addition, in step S500, the level of the common line and the control line is equal to the ground level.

In step S550, a data signal is supplied to the data line. In a possible embodiment, the data signal can be provided by enabling a source driver. In the present embodiment, the time of step S510 is equal to the time of step S550 (i.e., the time at which the source driver supplies the data signal to the data line).

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . Image display system

110. . . Conversion device

130. . . Display panel

210. . . Gate driver

230. . . Source driver

250, 270. . . Power module

290. . . Clock controller

P ₁₁ ~P _mn . . . Pixel unit

T1, T2. . . Switching transistor

Cst. . . Storage capacitor

Clc. . . Liquid crystal capacitor

S500~S550. . . step

Figure 1 is a schematic illustration of an image display system in accordance with the present invention.

Figure 2 is a schematic illustration of a display panel in accordance with the present invention.

Fig. 3 is a timing chart showing the control of the display panel according to the present invention.

Figures 4A and 4B show the relationship between the polarity signal S _P and the level of the control line.

Figure 5A is a possible embodiment of a control method in accordance with the present invention.

Figure 5B is another possible embodiment of a control method in accordance with the present invention.

S510, S530. . . step

Claims (28)

A control method is applicable to a pixel unit, the pixel unit is coupled to a gate line and a data line, and includes a storage capacitor and a liquid crystal capacitor, wherein the storage capacitor and the liquid crystal capacitor are connected in series with a common line and a Between the control lines, the control method includes: during a first period, generating a scan signal to the gate line, and making the level of the common line and the control line equal to a ground level; and during a second period The level of the common line is changed from the ground level to a first level, and the level of the control line is changed from the ground level to a second level, wherein the first of the liquid crystal capacitors The second end of the liquid crystal capacitor is directly connected to a first end of the storage capacitor, and a second end of the storage capacitor is directly connected to the control line. The control method of claim 1, wherein in the second period, the common line and the level of the control line are simultaneously converted from the ground level to the first and second levels. The control method of claim 1, wherein in the first period, a gate driver is enabled to provide the scan signal, and before the first period, a first gate level is generated and A second gate is granted to the gate driver. The control method of claim 3, wherein when the level of the gate line is equal to the first gate level, the pixel unit can receive the signal on the data line, when the level of the gate line When the second gate is equal, the pixel unit stops receiving signals on the data line. The control method of claim 3, wherein the common line and the level of the control line are equal to the ground level before the first period quasi. The control method of claim 1, further comprising: providing a data signal to the data line during a third period, wherein the third period is after the second period. The control method of claim 6, wherein in the third period, a source driver is enabled to provide the data signal, and the length of the first period is equal to the source driver providing the data signal The time for the information line. The control method of claim 6, wherein the second period has a reset period and a preset period during which the level of the control line is a third level. During the preset period, the level of the control line is controlled according to a polarity signal. The control method of claim 8, wherein the third level is equal to the ground level. The control method of claim 8, wherein the third level is equal to the second level. The control method of claim 8, wherein when the polarity signal is a first polarity level, the data signal of the data line is positive, and when the polarity signal is a second polarity level, The data signal of the data line is negative. The control method of claim 11, wherein when the polarity signal is a first polarity level, the level of the control line is equal to the ground level, when the data signal is a second polarity level. The level of the control line is equal to the second level, and the second level is greater than the ground level. For example, the control method described in claim 1 of the patent scope, wherein the One is equal to the second level. An image display system includes: a gate driver for generating a scan signal during a first period; a pixel unit having a storage capacitor and a liquid crystal capacitor, wherein the storage capacitor and the liquid crystal capacitor are connected in series with a common line a first end of the liquid crystal capacitor is directly connected to the common line, a second end of the liquid crystal capacitor is directly connected to a first end of the storage capacitor, and a second end of the storage capacitor is directly connected The control line; and a first power module for controlling the level of the common line and the control line. In the first period, the level of the common line and the control line is equal to a ground level, in a During the second period, the level of the common line changes from the ground level to a first level, and the level of the control line changes from the ground level to a second level. The image display system of claim 14, wherein the first power module simultaneously converts the common line and the level of the control line from the ground level to the first The second level. The image display system of claim 14, further comprising: a second power module for generating a first gate level and a second gate position for the gate before the first period driver. The image display system of claim 16, wherein the first power module sets the level of the common line and the control line to be equal to the ground level before the first period. The image display system as described in claim 17 of the patent application, further comprising: A source driver provides a data signal to the pixel unit during a third period. The image display system of claim 18, wherein when the level of the gate line is equal to the first gate level, the pixel unit receives the data signal, when the level of the gate line is equal to the When the second gate is on time, the pixel unit stops receiving the data signal. The image display system of claim 18, wherein the length of the first period is equal to the time that the source driver supplies the data signal to the pixel unit. The image display system of claim 18, wherein the second period has a reset period and a preset period during which the first power module sets the level of the control line to A third level, during the preset period, the first power module controls the level of the control line according to a polarity signal. The image display system of claim 21, wherein the third level is equal to the ground level. The image display system of claim 21, wherein the third level is equal to the second level. The image display system of claim 21, wherein when the polarity signal is a first polarity level, the data signal is positive, and when the polarity signal is a second polarity level, the data signal is Negative polarity. The image display system of claim 24, wherein when the polarity signal is a first polarity level, the first power module makes the level of the control line equal to the ground level, when the data signal For a second When the polarity level is correct, the first power module makes the level of the control line equal to the second level, and the second level is greater than the ground level. The image display system of claim 14, wherein the first level is equal to the second level. The image display system of claim 14, further comprising a conversion unit for converting an input voltage into an output voltage, wherein the gate driver and the first power module operate according to the output voltage. The image display system of claim 27, wherein the image display system is a number of assistants, a mobile phone, a digital camera, a television, a global positioning system, a vehicle display, and an aviation display. , a digital photo frame, a notebook computer or a desktop computer.