TWI387878B - A nand flash memory controller exporting a logical sector-based interface - Google Patents

Description

Output logical segment-based interface and flash memory controller

The present invention relates to memory devices (such as flash memory devices) and, more particularly, to a memory device whose controller outputs a logical segment based interface.

Flash memory devices have long been known to us. Typically, each unit of a flash memory stores an information bit. Traditionally, the way to store a bit is the two states of the support unit - one state represents logic "0" and the other state represents logic "1". In a flash memory cell, the two states are located above the channel of the cell (the source is connected to the source and drain elements of the cell of the cell) by a floating gate Two effective states of the amount of charge in the floating gate are implemented. Typically, a state has zero charge in the floating gate and is the initial unwritten state of the cell after being erased (generally defined as indicating a "1" state) and the other state is in the floating gate A certain amount of negative charge (usually defined as representing a "0" state). Having a negative charge in the gate results in an increase in the threshold voltage of the cell of the cell (i.e., the voltage that must be applied to the control gate of the transistor to cause the transistor to conduct). The stored bit can now be read by checking the threshold voltage of the cell - if the threshold voltage is in a higher state, the bit value is "0", and if the threshold voltage is in a lower state, Then the bit value is "1". In fact, there is no need to accurately read the threshold voltage of the cell - it is only necessary to correctly identify which of the two states the cell is currently in. For each purpose, it is sufficient to compare the reference voltage value in the middle between the two states, and thus the threshold voltage of the determining unit is lower or higher than the reference value.

Figure 1A illustrates how this system works. In particular, Figure 1A shows the distribution of threshold voltages for a large number of cells. Because the cells in a flash device are not identical in their characteristics and performance (for example, due to small changes in impurity concentration or defects in the germanium structure), applying the same stylized operation to all of these cells does not result in All of these units have exactly the same threshold voltage. (Note that for historical reasons, writing data to a flash memory is often referred to as "stylizing" the flash memory. The terms "write" and "stylized" are used interchangeably herein). The reality is that the threshold voltage is distributed in a manner similar to that shown in Figure 1A. A cell storing a value of "1" typically has a negative threshold voltage such that most cells have a threshold voltage close to the value shown by the left peak of Figure 1A, while some smaller number of cells have lower or lower High threshold voltage. Similarly, a cell storing a value of "0" typically has a positive threshold voltage such that most cells have a threshold voltage close to the value shown by the right peak of Figure 1A, while some smaller numbers of cells have Low or higher threshold voltage.

In recent years, a novel type of flash device has appeared on the market, using a technique known as "multi-level unit" or simply MLC. (This nomenclature can be misunderstood because the flash type of the previous type also has more than one level: it has two levels, as described above. Therefore, the two flash units are referred to herein. "Single Bit Unit" (SBC) and "Multiple Bit Unit" (MBC)). The improvement brought about by the MBC flash device is to store two bits in each cell. (In principle, MBC also includes more than two bits per cell. To simplify the explanation, the two-element condition is emphasized in this paper. However, it should be understood that the present invention is equally applicable to support more than two bits per cell. Flash memory device). In order for a single unit to store two information bits, the unit must be able to be in one of four different states. Since the "state" of a cell is represented by its threshold voltage, it is clear that an MBC cell should support four different valid ranges of its threshold voltage. Figure 1B shows the threshold voltage distribution of a typical MBC unit. As expected, Figure IB has four peaks, each peak corresponding to one of the states. For an SBC condition, each state is actually a threshold voltage range and is not a single threshold voltage. When reading the contents of the unit, it is only necessary to ensure that the range in which the threshold voltage of the unit is located is correctly identified. For a prior art example of one of the MBC flash devices, see U.S. Patent No. 5,434,825, the disclosure of which is incorporated herein in

Flash memory devices are typically divided into NOR devices and non-devices, which are derived from the manner in which individual memory cells are interconnected within a cell array. The NOR device is a random access device - the host computer accessing a NOR flash device can provide any address to the device on the address pin of the device and immediately retrieve it in the address of the device. Information. This is very similar to how SRAM or EPROM memory operates. On the other hand, the non-device is not a random access device but a serial access device. It is not possible to access any random address in the manner described above for NOR. Instead, the host must write a one-tuple sequence into the device that identifies the type of command requested (eg, read Fetch, write, erase, etc.) and the address to be used for the command. This address identifies a page (the smallest block of flash memory that can be written in a single operation) or a block (the smallest block of flash memory that can be erased in a single operation) rather than identifying A single byte or block. The read and write command sequence does include a single byte or block address, but in fact the flash device always reads the full page from the memory unit and writes the full page to the memory unit. After a page has been read from the array into a buffer located inside the device, the host can access the data bytes or groups continuously by using a strobe signal for successive clock outputs. The data bytes or groups of words.

Because of the non-random access nature of the device, these devices cannot be used to directly execute code from their flash memory. This is in contrast to NOR devices that support direct code execution (often referred to as "execution in place" or "XIP"). Therefore, NOR devices are devices that are commonly used for code storage. However, non-devices have the advantage of making them very useful for data storage. Non-devices are cheaper than NOR devices with the same bit capacity, or equivalently, non-devices provide much more storage bits than NOR devices of the same cost. Moreover, the write and erase performance of non-devices is much faster than the write and erase performance of NOR devices. These advantages make non-flash memory technology the technology of choice for storing data.

A typical SBC non-device is a TC58NVG1S3B (Toshiba Corporation, Tokyo, Japan) that provides 2 Gbit of storage capacity. A typical MBC non-device is a TC58NVG2D4B (also known as Toshiba Corporation, Tokyo, Japan) that provides a 4 Gbit storage capacity. A data sheet with two devices is attached as Appendix A and Appendix B.

As can be seen from the above data sheet, these two non-compliant devices have similar interfaces. These non-devices use the same electrical signals to coordinate the transfer of commands and data between the non-flash device and its host device. These signals include data lines and some control signals - ALE (address latch enable), CLE (command latch enable), WE\ (write enable), RE\ (read enable), and so on. SBC and MBC devices are not exactly the same in terms of performance, and writing an MBC page takes much longer than writing to an SBC page. However, the electrical signals used in the two devices and the functionality of the two devices are the same. This type of interface agreement is referred to in this technology as a "non-interface" protocol. Although the "non-interface" agreement has not been formally standardized by a standardization organization to date, manufacturers of non-flash devices still follow the same protocol for supporting a basic subset of non-flash functionality. This is done so that customers who use non-devices within their electronic products can use equipment from any manufacturer without having to tailor their hardware or software to operate with a particular vendor's equipment. Note that even non-commercial vendors that provide additional functionality beyond this basic functional subset are guaranteed to provide this basic functionality to at least some extent provide compatibility with agreements used by other vendors.

As used herein, the term "non-interface agreement" (or simply "non-interface") means an interface agreement between a device and a response device, even if the protocol is not fully compatible with all timing parameters. Does not support a wipe command, is not fully compatible with other commands that are not supported by the device, or contains additional commands that are not supported by the device. The interface agreement still generally follows the basic read described above. A protocol between a host device and a non-flash device that takes the write operation. In other words, the term "non-interface (agreement)" refers to any use of the transferred byte sequence (in terms of functionality and when creating interfaces with Toshiba TC58NVG1S3B non-devices and Toshiba TC58NVG2D4B non-devices for reading (opcode) 00H) and the byte sequence used in writing (opcode 80H) is equivalent) and also uses control signals (in terms of functionality and CLE, ALE, CE, WE and RE signals of these two non-devices) Equivalent) interface agreement.

It should be noted that "non-interface agreements" are not symmetrical. The host device always initiates interaction via a non-interface and the flash memory device never initiates interaction.

If a given device (eg, controller, flash device, host device, etc.) includes the necessary to support a non-interface protocol (eg, for interacting with another device using the non-interface protocol) An element (eg, a hardware, a soft body, a firmware, or any combination thereof) is referred to as including, including, or having the "non-interface".

Since the non-interface protocol is not symmetrical, the terms "host type non-interface" and "flash type interface" are used herein to distinguish between the two sides of a non-interface agreement. Since the host initiates an interaction, if a given device includes a host side for implementing a non-interface agreement (ie, for presenting a non-host and initiating a non-compliant interaction) For the body and / or firmware and / or software, the device is said to have a "host type and interface" or output a "host type and interface" or "support" - "host type and interface". Similarly, since the flash device never initiates interaction, if a given device includes the hardware necessary to implement the non-compliant flash side (ie, for presenting a non-flash device) And / or firmware and / or software, the device is said to have a "flash type and interface" or "output" - "flash type and interface" or "support" - "flash" interface".

As used herein, the term "host device" (or simply "host") means any device that has processing power and is capable of establishing an interface with a flash memory device. Examples of typical host devices include personal computers, PDAs, mobile phones, game consoles, and the like.

In general, it is relatively difficult to establish interfaces and operate with non-devices. One of the reasons is the agreement for accessing relatively complex devices (compared to NOR devices), as described above. Another difficulty is that there is an error in the data read from the device (as opposed to a NOR device that can be assumed to always return the correct data). This inherent non-reliability of equipment requires the use of error detection code (EDC) and error correction code (ECC).

Manufacturers of SBC non-flash devices typically recommend that the user apply an error correction code that corrects one bit error in each page having 512 data bytes. However, the MBC non-flash device data sheet generally suggests the application of an ECC capable of correcting 4 bit errors in each page with 512 data bytes. For pages of 2048 bytes in size (such as in the case of the non-devices mentioned above (commonly referred to as "large block devices"), it is recommended for each 512 bits of the page. The tuple part is applied with error correction. As used herein, the term "N-bit ECC" refers to an ECC mechanism capable of correcting N bit errors in 512 data bytes, regardless of the size of one page of the 512 bytes, less than one page. Still larger than one page.

Due to the complexity of the device, the convention uses a "non-controller" for controlling the use of a non-device in an electronic system. It is true that a host device can be operated directly and used without a device and without a intervention, and there is a system that actually operates similarly. However, this architecture suffers from many drawbacks. First, the host must individually manipulate each of the non-device control signals (eg, CLE or ALE), which is cumbersome and time consuming for the host. Second, the support for EDC and ECC imposes a severe burden on the host. The parity bit must be calculated for each page being written, and the error detection calculation must be performed by the host (and sometimes the error is also performed). Correction calculation). All this makes this "no controller" architecture relatively slow and inefficient.

When using a non-device, using a non-controller significantly simplifies the task of the host. The processor uses a much more convenient protocol (a request to write a page can be sent as a single command code after the address and data, without having to program the control line and the complex code of the command code. Difficult to interact with the controller. The controller then converts the host-controller contract into an equivalent non-contract sequence, while the host is free to perform other tasks (or just wait for completion of the inaction (if so).

There are several options in the prior art regarding the location of the controller and the system within the system. A first method is shown in FIG. Here, a non-controller 114 entity is located within one of the host devices 110A's host processor 112A. If host processor 112A is implemented as a single die, controller 114A is incorporated on the same die. This is for example the case in some OMAP processors manufactured and sold by Texas Instruments of Dallas TX USA. In a system that uses this shelf, the host processor 112A typically interacts with the controller 114 using a proprietary protocol because the interaction is internal to the host processor 112A and uses a standard protocol. There are benefits.

A second prior art method is illustrated in Figures 3A-3B. Here, a non-controller 116 is a separate physical component resident between one of the host processor 112B and a non-compliant device 120A. This is the case, for example, in a portable USB flash drive (UFD) such as the DiskOnKey manufactured and sold by SanDisk Corporation of Milpitas CA USA. In this UFD, there is a non-controller 116 that is packaged inside the UFD and uses a device side non-interface 124 on one side to interact with the non-device 120A and on the other side. (Using a host side USB interface 122 using the USB protocol) interacts with the host processor 112B. In a system that uses this shelf construction, host processor 112B typically interacts with controller 116 without using a standard protocol (such as USB or ATA) because the interaction is external to processor 112B and is directed to other It is more convenient to use a standard protocol that has been supported by processor 112B.

A third prior art method is illustrated in FIG. Here, the non-controller 118 entity is located within a non-device 120B. The non-device 120B and the controller 118 can even be implemented on the same die. This is the case, for example, in certain MDOC storage devices manufactured and sold by SanDisk Corporation and OneNAND devices manufactured and sold by Suwon, South Korea's Samsung Electronics. In a system that uses this shelf construction, host processor 112B typically interacts with controller 118 without using a standard protocol (such as USB) or a semi-standard protocol (such as for MDOC and OneNAND devices).

It can be inferred from the above that a prior art stand-alone controller (which is not integrated with a non-device or host processor) typically has a standard interface on its host side and has a flash memory device side on its side. A non-interface (as in Figure 3B). In fact, we can find many interface types in the market, such as USB, SD (safe digital), MMC (multimedia card), etc. A non-controller having a non-contact interface on both sides is disclosed in U.S. Patent Application Serial No. 11/326,336, the disclosure of which is incorporated herein by reference.

Another function provided by the controller is to output a logical address space to the host instead of a physical address space. Flash devices have certain limitations that make it somewhat problematic to use such devices at physical address levels. In a flash device, one of the previously written areas of the memory is overwritten without previously erasing the area (i.e., the units must be erased before the flash unit can be programmed again) (for example, stylized to "1")) is impractical. Can only be used for relatively large groups of cells commonly referred to as "erase blocks" (usually 16 Kbytes to 128 Kbytes in current commercial and non-device sizes, and larger in NOR devices) Execute the erase. Therefore, updating the content of a single byte or even a block of 1 kilobyte requires a "housekeeping" operation, and the portion of the erased block that is not to be updated must first be moved elsewhere, so that The portion will be retained during the erase and then moved back to the appropriate location.

In addition, certain blocks of the device are unreliable "bad blocks" so that the use of such blocks should be avoided. A block is declared "bad block" by the manufacturer when initially testing the device or when the application software detects a failure of the block during use of the device in the field.

To overcome these limitations of non-devices, the Flash File System (FFS) has been introduced. One such FFS is described in U.S. Patent No. 5,404,485, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety herein in An FFS provides a data storage and manipulation system on the flash device that allows such devices to emulate a disk. In the prior art, an application or operating system interacts with a flash storage system that does not use physical addresses but uses logical addresses (sometimes referred to as virtual addresses). There is an intermediate software layer between the software application and the physical storage system that provides a mapping from one of the logical address to the physical address. Although a software can treat a storage system as having a contiguous, defect-free medium (which can be read or written randomly and without restriction), the physical addressing mechanism has "holes" in its address range (eg, Due to the bad blocks), the pieces of data that are adjacent to each other in the logical address range can be greatly separated in the physical address range. The intermediate software layer that performs the mapping described above can be a software driver that executes on the same CPU that the application executes on. Alternatively, the intermediate software layer can be embedded in a controller that controls the flash device of the storage system and acts as the interface of the host CPU of the host computer when the host computer accesses the storage system. This is the case, for example, in a removable memory card, such as a Secure Digital (SD) card or Multimedia Card (MMC), where the card has an on-board controller that executes a firmware program, in addition to the firmware program. This type of mapping is implemented in addition to other features.

Software or firmware implementations that perform such address mapping are often referred to as "flash management systems" or "flash file systems." The latter term is a misnomer because it does not have to support "files" (in the sense that files are used in operating systems or personal computers), but rather supports blocks similar to those exported by hard disk software drivers. The block device interface of the device interface. Nevertheless, the term "flash file system" is often used, and "flash file system" and "flash management system" are used interchangeably herein.

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If a host computer that establishes an interface with a storage device and accesses the device for reading and/or writing data does not know the physical address at which the data is stored, then the device is referred to herein as an output (or Simply "have" a logical interface. Data that is written to a specific logical address provided by the host/read from a specific logical address provided by the host can be stored in any physical location within the storage device, but this fact is invisible to the host of. In general, a storage device having a logical interface also means that the host considers the storage device to have an adjacency "non-porous" address space.

If a host computer that establishes an interface with a storage device and accesses the device for reading and/or writing data knows the physical address at which the data is stored and explicitly references the entity when issuing a command to the storage device The address is referred to herein as an output (or "with") entity interface.

More generally, in the case of a storage device having a logical interface, if it corresponds to a device having a "flash" type interface through "host" or "output" via its host type interface The host device does not know the physical address but only the logical address, and the device is referred to herein as a "having" or "output"-"logical" flash-type interface. The corresponding host type interface of the host device is referred to herein as a "logical" host type interface. Similarly, in the case of a storage device having a physical interface, if the corresponding host device knows the physical address, a device having "with" or "output" a flash-type interface is referred to herein. "Having" or "Output" - "Entity" host type non-interface. The corresponding host type interface of the host device is referred to herein as a "physical" host type interface. Note that one of the logical flash-type interfaces of one device must be paired with one of the logical host-type interfaces of the other device to enable the two devices to exchange data according to a non-conformity; and one of the devices is fast The flash-type interface must be paired with one of the other devices' physical host type interfaces to enable the two devices to exchange data in accordance with a non-compliant agreement.

Using the above terms, prior art non-flash devices can be classified as follows: A. Output to the host a device that is not an interface and is a logical interface interface. All devices that output USB, SD, or MMC interfaces are in this category because they require the use of logical addresses for their protocols (both non-non-interfaces).

B. Output a device that is a logical interface and interface to its host. This is, for example, the controller disclosed in US Pat.

C. Output to the host a device that is a non-interface of the physical interface. Standard non-devices, such as the two Toshiba non-devices mentioned above, are within this category.

There is a further problem with the potential complexity of having to interface with non-and-based flash memory devices. Write to non-devices in pages. In other words, a page can be written to the smallest block of data in the array of memory cells. In the past, most non-flash devices used pages of 0.5 Kbyte (512 bytes). Recently, most non-devices use 2 Kbyte pages. On the other hand, the operating system of the host computer and the application executing on the host computer usually access the stored data in units of "segments" (0.5 Kbytes in size). When using a device with a 0.5 Kbyte page, there is an exact match between the page size and the segment size, and no difficulty is expected. However, when using a non-device with 2 Kbyte pages (or other page size larger than the size of a segment), assigning multiple segments to a common flash page, and this creates some complexity, as follows The text will explain.

U.S. Patent No. 6,760,805 to Lasser teaches some of the complexity associated with flash management systems when the page size is larger than the segment size, and teaches a method for solving such problems. The method of U.S. Patent No. 6,760,805 deals with the manner in which the flash management system configures the physical address and is not directly related to the logical address known by the host.

A storage device that outputs a non-negative interface (such as USB, SD, or MMC) uses the segment as its base data transfer unit. Therefore, when using such devices, the host does not have to know the actual page size within the device and the controller handles all translations and mappings. This is logical because these controllers have already processed logical-physical address translations, and adding a section-page mapping is a natural extension. When a storage device that is also a non-interface of the physical interface is used, the basic data transfer unit between the host and the memory device is a page. If the page is larger than a segment, the data segment mapping and matching to the page load falls on the host.

We would expect that when using a storage device with a logical interface and a non-interface, the data transfer unit will be a segment because the use of logical addressing implies the presence of a logical-physical bit that can simply be added with a segment-page mapping. Address translation. However, this is not the case, and all prior art devices having a non-interface of logical interface use pages rather than segments as their basic data transfer unit.

This fact eliminates most of the benefits that will be gained due to the use of logical non-interfaces. The advantages of these interfaces and the main reason for their use are to simplify the access software on the host side. Because the logical interface handles bad blocks and other challenges of flash management, the host's access to the memory device becomes very simple, the host writes a logical page and reads a logical page. There is no need to focus on the physical location of the page or the waste collection work that must be performed in order to have sufficient free space for additional writing. However, if a non-logical logical interface uses the page as its base data transfer unit and the page size is different from the segment size, most of this simplicity will be lost.

To understand why this is the case, consider what happens when a host must write a stream with several 0.5 Kbyte logical segments to a device that outputs a page of 2 Kbytes each. Let us assume (as an example) that segments with logical addresses 0, 1, 2, and 3 will be written to the storage device one by one. Since the interface only supports 2 Kbyte page operations, when writing to the 0th segment, the host actually causes 2 Kbytes to be moved into the flash array of the cell. Then the first section should be written. However, the segment must be loaded into a common page along with the 0th segment. Therefore, the host must read back the 0th sector, merge the data of the two sections, and send a page write command containing the data of the two sections. This continues for the second segment and then continues for the third segment. In each case, the previous segment must be read out to the host and only rewritten after being combined with the newly acquired segment by the host. This process is highly inefficient and eliminates the primary advantage of having a logical interface as described above - accessing the memory device according to a simple access model without the host having to be exposed to the physical implementation details of the flash memory (such as page size) ) interference.

It is therefore widely recognized that there is a need and will be highly advantageous to have a convenient way to access a storage device having a logical non-interface and a host even by a host having a segment size different from the page size of the storage device.

According to the present invention, there is provided a controller for a flash memory device, comprising: (a) a host type non-interface for exchanging data pages with non-flash memory devices; and (b) a a flash-type non-interface for exchanging data segments with a host of the controller; wherein the data pages have a common data page size, and wherein the data segments have a common difference from a common data page size Data section size.

According to the present invention, there is provided a data storage system comprising: (a) a memory comprising a plurality of physical pages, the physical pages having a common physical page size; and (b) for outputting a flash type An interface of the interface for exchanging data segments with a host of a data storage system, wherein the data segments have a common data segment size different from the physical page size.

According to the present invention, there is provided a method of storing data comprising the steps of: (a) providing a memory comprising a plurality of physical pages, the physical pages having a common physical page size; and (b) outputting to a host A flash-type non-interface for exchanging data segments with the host, wherein the data segments have a common data segment size different from the physical page size.

The basic controller for controlling a flash memory device of the present invention comprises a host type interface for exchanging data pages with the flash memory device and a data area for exchanging data with a host of the controller The flash type of the segment is not the interface. The data pages have a common data page size, the data segments having a common data segment size, and the common data segment size is different from the common data page size. In this paper, the "size" of a data page is understood as the number of bits in a data page. In this paper, the "size" of a data section is understood as the number of bits in a data section. For example, a byte of length of 8 bits is used, a size of a 512-bit block is 4096 bits and a size of a 2 Kbyte page is 16,384 bits. Preferably, the common data segment size is less than the common data page size.

Preferably, the host type interface is a physical interface and the flash type interface is a logical interface.

Preferably, the controller also includes at least one host side interface. Note that a "host side" interface is not the same as a "host type" interface. For example, Figure 5A below shows a controller having two host side interfaces, one of which is a flash type interface.

Preferably, the controller also includes one or more functional modules, such as an error correction module, an encryption module, and/or an address mapping module.

One type of data storage system of the present invention includes a controller of the present invention and a flash memory device controlled by the controller. Preferably, the flash memory device is a non-flash memory device.

The choices for manufacturing controllers and flash memory devices include: manufacturing controllers and flash memory devices on different individual dies, in which case the host-type interface and the interface are inter-die interfaces; And manufacturing controllers and flash memory devices on a common die. If the controller and the flash memory device are fabricated on different dies, the package selection includes: packaging the controller and the flash memory device in the same multi-chip package; packaging the controller in a In the controller package, the flash memory device is packaged in a separate memory device package; the controller is packaged in a controller package, and the flash memory device die is directly mounted on the device a printed circuit board; the flash memory device is packaged in a memory device package, and the controller die is directly mounted on a printed circuit board; and the controller die and the flash memory are The device die is mounted directly on a printed circuit board.

One type of data processing system of the present invention includes the data storage system and its host.

Another basic data storage system of the present invention includes a memory comprising a plurality of physical pages, each of which has a common physical page size. The basic data storage system also includes circuitry for outputting a flash type interface that is used to exchange data segments with a host of the data storage system. The data segments have a common data segment size that is different from the common physical page size of the pages of the memory. The "size" of a physical page is understood herein as the maximum number of bits that can be stored in a physical page. For example, using a byte of 8 bits in length, a 2 Kbyte physical page has a size of 16,384 bits. Preferably, the common data segment size is smaller than the common physical page size.

Preferably, the flash type interface is a logical interface.

Preferably, each page includes a plurality of flash units. Most preferably, the flash units are not flash units.

Options for fabricating circuits and memories include fabricating circuits and memory on different individual dies and fabricating circuits and memories on a common die. If the circuit and the memory are fabricated on different dies, the package options include: packaging both the circuit and the memory in the same multi-chip package; packaging the circuit in a circuit package and packaging the memory in an independent package In the memory package; the circuit is packaged in a circuit package, and the memory die is directly mounted on a printed circuit board; the memory is packaged in a memory package, and the circuit die is directly mounted On a printed circuit board; and mounting both the circuit die and the memory die directly on a printed circuit board.

Another data processing system of the present invention includes the data storage system and a host of the data storage system.

The basic method for storing data of the present invention includes the steps of providing a memory comprising a plurality of physical pages (all having a common physical page size) and outputting a message to a host for exchanging data segments with the host Flash type and interface steps. The data segments have a common data segment size that is different from the common physical page size of the pages of the memory. Preferably, the common data segment size is smaller than the common physical page size.

Preferably, each physical page has a respective physical address range and each data segment has a respective logical sector address. Writing data to the memory by a number of steps includes: receiving one or more data segments from the host to write to the memory; mapping the logical sector addresses of each of the received data segments to a corresponding physical address; and writing the (etc.) data section to one or more physical pages, the (etc.) physical page having the mapping in its respective physical address range (etc. The (etc.) physical address of the logical sector address. Reading data from the memory by a number of steps, the steps comprising: receiving a command from the host to read one or more data segments from the memory; mapping the logical sector addresses of each data segment And corresponding to the physical address; and reading the (etc.) data section from one or more physical pages, the (etc.) physical page having the mapping in the respective physical address range of the (etc.) The (etc.) physical address of the logical sector address.

The principles and operation of accessing a memory device via a non-interface can be better understood with reference to the drawings and accompanying description.

The invention will now be described in terms of specific exemplary embodiments. It will be understood that the invention is not limited to the illustrative embodiments described hereinafter. It should also be understood that each of the controllers, the system including the controller, and the method of reading, and each of the features described herein, are not required to be implemented as claimed in any particular claim in the appended claims. this invention. Various elements and features of the device are described to enable full implementation of the invention. It is also to be understood that the steps of the method may be carried out in any order or concurrently, as illustrated or described in the context of the present disclosure.

The controller of the present invention outputs a logical non-interface and a controller to the host side. Even if the physical page of the non-device controlled by the controller has a size different from the size of the segment, the logical non-interface supports Use the section as a data transfer unit. The controller of the present invention processes the mapping of logical segments as seen by the host to physical pages as seen by the device.

A "non-flash memory device" is defined herein as an electronic circuit that includes a plurality of non-flash memory cells and any necessary data for storing data in the non-flash memory cells. Internal control circuitry (eg, circuitry for providing a flash interface). It should be noted that the "non-flash memory device" does not have to have its own dedicated housing and can reside in a single housing along with another "device" such as a controller. In some embodiments of the invention, "non-flash memory devices" are mounted directly on a printed circuit board without any intervening packages.

Referring again to the drawings, Figure 5A is a schematic block diagram of a controller 130 in accordance with some embodiments of the present invention. The controller 130 includes a flash memory device side interface 142 for establishing an interface to a non-flash device. The flash memory device side interface 142 is a host type non-interface (ie, adapted to initiate interaction via a non-interface and present a host device to a non-flash device).

The controller 130 also includes a host side interface 144 for establishing an interface to a host supporting a non-interface agreement. The host side interface 144 is a flash memory type interface (ie, the controller 130 is adapted to present a non-flash memory storage device to the host). The controller may optionally include one or more additional host side interfaces 146 for establishing the interface to the host using a non-non-interface (such as a USB or MMC interface).

As shown in FIG. 5A, the controller 130 further includes an ECC module 132 for detecting and correcting all or some of the errors in the data retrieved from the non-device by the device side interface 142. The ECC module 132 can include hardware, software, firmware, or any combination thereof. The ECC module 132 can correct all errors, and in this case, the controller 130 outputs a non-error-free device to the host. Alternatively, the ECC module 132 may only correct some of the errors found in the data retrieved from the non-compliant device via the flash memory device side interface 142.

The controller 130 also includes one or more addresses for providing other functionality, such as cryptographic functionality or mapping logical flash addresses received from the host to physical flash addresses that are sent to the flash device. Mapped) module 134 (eg, including hardware, software, firmware, or any combination thereof). Since controller 130 outputs a logical interface, controller 130 must include at least the functionality of logical-physical address translation. Other functional options are optional.

Figure 5B is a schematic block diagram of an exemplary system including the external non-controller 130 (i.e., a controller separate from the host device) as depicted in Figure 5A. The external non-controller 130 establishes an interface with the non-flash device 120A of FIGS. 2 and 3A via the device side interface 142. The controller 130 establishes an interface with the host device 110A of FIG. 2 via the host side interface 144.

An innovative feature of the present invention is that the controller 130 interacts with the host 110A using the data section. Host 110A writes the segment to controller 130 and reads the segment from controller 130 (using logical addresses in both cases). Controller 130, on the other hand, uses a profile page to interact with non-flash memory device 120A, where the page has a different size than the segment.

FIG. 6A illustrates an exemplary die configuration of the exemplary system depicted in FIG. 5A. Thus, the non-controller 130 includes an electronic circuit 135 fabricated on a controller die 131, and the non-flash device 120A includes an electronic circuit 137 fabricated on a flash die 133. The controller die 131 and the flash die 133 are different and independent dies.

It should be noted that the components in the controller 130 (ie, the ECC module 132, the flash type interface 144, the host type interface 142 and 146) are at least partially borrowed as illustrated in FIG. 5A. It is implemented by controller electronics 135 resident on controller die 131.

The interface 142 between the controller electronics 135 and the flash electronic circuit 137 is an "inter-die" interface. As used herein, an "inter-die interface" (eg, a inter-die interface) is operative to establish an interface between two different cells of an electronic circuit resident on different dies (eg, provide Necessary physical and logical infrastructure for enabling different units of an electronic circuit to communicate with each other, for example, using one or more specific protocols. Thus, the inter-die interface 142 includes the physical components (pads, output and input drivers, etc.) necessary to establish an interface between two different cells 135 and 137 of electronic circuitry resident on the individual dies 130 and 133. ).

In accordance with some embodiments of the present invention, an inter-die interface creates an interface between two electronic circuits fabricated on different dies that are packaged in a common package. This example is illustrated in FIG. 6B in which both the controller 130 and the non-flash device 120A reside in a common multi-chip package 139.

Alternatively, the inter-die interface establishes an interface between electronic circuits fabricated on two different dies that are packaged in different packages (eg, each of which is packaged in its own package). This example is illustrated in Figure 6C, which shows the non-controller 130 and non-flash device 120A resident in separate individual packages 141 and 143. The controller 130 is resident in the controller package 141, and the flash device 120A is not resident in the flash package 143. Thus, as illustrated in Figure 6C, interface 142 is an "inter-package interface."

Embodiments in which the dies are resident in a common package (eg, as shown in FIG. 6B) and the dies are resident in a separate package (eg, as shown in FIG. 6C) are not all possible configurations.

Thus, or in some embodiments, the inter-die interface establishes an interface between electronic circuits fabricated on two different dies, wherein one or both of these dies do not have a package at all. For example, in many applications, memory dies are provided (eg, mounted (eg, directly mounted)) on a board without packaging at all due to the need for space savings. Therefore, in an example, it should be noted that in a new generation of memory cards for telephones, the memory die is typically mounted on a board without packaging at all. As used herein, a die that is "directly mounted" on a printed circuit board is mounted on a printed circuit board without first being packaged. These embodiments are illustrated in Figures 6D, 6E and 6F. 6D shows the non-flash device 120A packaged in the controller package 141 and not directly to the controller 130 (as in FIG. 6C) and directly mounted on a printed circuit board 145. 6E shows the non-flash controller 120A (as in FIG. 6C) packaged in the flash package 143 and the non-controller 130 mounted directly on a printed circuit board 147. Figure 6F shows the non-controller 130 and non-flash device 120A, both mounted directly on a common printed circuit board 149.

Although it is common practice to implement an output-logic interface and a controller on a die that is separate from the device controlled by the controller, this is not critical to the invention. Therefore, the present invention is also applicable when the non-device and the non-controller are implemented on a common single die. Figure 6G shows that both the controller 130 and the non-flash device 120A are fabricated on a common die 151.

7 is a flow chart of a method by which a host 110A (ie, a host that includes a controller other than the controller 114) transmits data (eg, a profile via the external controller 130). The segment is written to the non-storage device 120A. As shown in FIG. 7, host 110A issues (block 410) a write command to external controller 130 (eg, a write command issued using a non-interface protocol, including command byte, address bits) A tuple and a data byte, where the command addresses a logical section).

The controller 130 receives the logical sector write command issued by the host 110A (e.g., via the host side interface 144). After receiving the write command, the controller 130 calculates (block 420) the number of physical pages that will store the segment data. If desired, the controller 130 can read the previously stored segments from the device 120A and merge the data of the segments with the newly received segment data, thus generating a page to be written to the calculated entity page. Information in the middle. The controller 130 then issues (block 430) a physical page write command to the non-device 120A (e.g., via the flash memory device side interface 142). Again, the order is issued in accordance with the non-interface agreement, which includes the command byte, the address byte, and the data byte. In block 440, the non-flash storage device 120A stores the data bytes it receives into the non-volatile memory unit of the specified physical page, thus implementing the request of the host 110A.

8 is a flow chart of a method by which a host 110A (ie, a host that includes a controller other than the controller 114) is read from the non-storage device 120A via the external controller 130. Take the data (for example, a data section). The host 110A issues (block 510) a read command to the external controller 130 (eg, a read command issued using a non-interface protocol, including a command byte and an address byte, wherein the command addresses one Logical section).

The external NOT controller 130 receives the logical segment read command issued by the host 110A (e.g., via the host side interface 144). After receiving the read command, the external controller 130 issues (block 520) a physical page read command to the non-compliant device 120A (eg, via the device side interface 142). Again, commands are issued based on non-interface protocols, including command bytes and address bytes. The physical page address embedded in the command is calculated by the controller 130 based on the logical sector address provided by the host 110A in block 510 and according to the mapping table maintained by the controller 130. In block 530, the non-flash storage device 120A retrieves the requested physical page material from its non-volatile cell array. In block 540, the data byte is sent to the external non-controller 130. This transmission is accomplished according to a non-interface protocol by a series of read strobes generated by controller 130, each of which reads a byte or a block in order (depending on the use of the strobe) And the interface width is 8 bits or 16 bits) read into the controller 130. The controller 130 can read all of the material of the physical page, or the controller 130 can selectively read only the data bytes corresponding to the requested logical segment. In block 550, the external controller 130 extracts logical segment data from the physical page data. This is only necessary if the controller 130 reads all of the material of the physical page in block 540. In block 560, the extracted data byte of the logical segment is sent to host 110A via host side non-interface 144. The transmission is performed again according to the non-interface protocol by a series of read strobes generated by the host 110A. Host 110A now has the same set of data bits that host 110A initially stores into the logical segments in the flash memory.

A flash memory storage system incorporating a flash memory device and a controller incorporating the method of the present invention can be constructed in any of the following ways: a. The memory system only accepts the manipulation logic segment The command, and does not accept the command to manipulate the logical page.

b. The memory system accepts both commands to manipulate the logical section and commands to manipulate the logical page. A mode change command switches the system between two modes (one mode for one type of command).

c. The memory system accepts both the command to manipulate the logical section and the command to manipulate the logical page. One of the modes is a preset mode, and a pre-command pre-order indicates that the command should be interpreted as a non-preset mode command.

d. The memory system accepts both the command to manipulate the logical section and the command to manipulate the logical page. An electrical signal applied to one of the contact pins of the system at the time of power supply selects one of the two modes. For example, selecting the "1" level indication at the pin should be interpreted as a segment-based command, and selecting the "0" level at the pin should interpret all commands as page-based. command.

e. The memory system accepts both the command to manipulate the logical section and the command to manipulate the logical page. An electrical signal that is applied to one of the contact pins of the system at the time of execution selects one of the two modes. For example, selecting the "1" level indication at the pin should interpret all commands executed at the current time as segment-based commands, and selecting the "0" level at the pin should indicate all at the current time. The executed command is understood to be a page-based command.

For all of the above implementations that support both segment-based and page-based commands in a system, the amount of data provided in a write command depends on whether the write command is a one-page command or According to a section command. In other words, when a page-based write command includes, for example, transmitting 2 Kbytes of data, a segment-based write command includes, for example, only transmitting 0.5 Kbytes. Similarly, the amount of data that the host can retrieve in a read command depends on whether the read command is a one-page command or a segment command.

In all types of logical interfaces, regardless of whether the logical interface is segment-based or page-based, the only data provided by the host to the storage system is user data. In other words, when storing a logical segment, exactly 512 bytes are transmitted by the host. This is in contrast to physical non-interfaces, some of which are sometimes provided by the host and stored in an "extra" or "alternate" area. These bytes can contain control information typically used for flash management algorithms. Since the logical interface hands over the burden of flash management to the memory system, the host is exempt from the task and does not need to process control information.

The structure of a section-based command can be the same as the structure of a page-based command. The same opcode for the read and write commands (operating codes 00H and 80H, respectively) can be used. The logical sector address provided within a sector-based command corresponds to a page address provided within a page-based command. A segment-based command may also allow a particular byte within the segment to be specified as a starting point, similar to a page-based non-and command that allows for the starting point to be specified. However, this is optional and a system can be implemented such that only the complete segment is written and read.

It can be seen that the present invention allows us to benefit from a logical interface even when a physical page other than the device is different in size from the operating system of the host computer.

In the description herein and in the appended claims, each of the verbs "comprising," "including," and "having" and verb variations thereof is used to indicate that one or more of the verbs are not necessarily A complete list of one of the components, components, components or components of one or more of the verbs.

The present invention has been described in detail with reference to the embodiments of the invention The described embodiments include different features, all of which are not required in all embodiments of the invention. Some embodiments of the invention utilize only some of these features or some possible combinations of such features. It will be readily apparent to those skilled in the art that variations of the embodiments of the invention described herein and the various combinations of the features recited in the described embodiments.

110A. . . Host device

110B. . . Host

112A. . . Host processor

112B. . . Host processor

114. . . Non-controller

116. . . Non-controller

118. . . Non-controller

120A. . . Non-flash device

120B. . . Non-device

122. . . Host side USB interface

124. . . Device side non-interface

130. . . Controller

131. . . Controller die

132. . . ECC module

133. . . Flash crystal

134. . . Module

135. . . electronic circuit

137. . . Flash electronic circuit

139. . . Multi-chip package

141. . . Controller package

142. . . Flash memory device side interface / host side non-interface

143. . . Flash package

144. . . Flash type non-interface/host side non-interface

145. . . A printed circuit board

146. . . Host side interface

147. . . A printed circuit board

149. . . Common printed circuit board

151. . . Common grain

Figure 1A illustrates the threshold voltage distribution of a flash cell that is programmed in a 1-bit mode; Figure 1B illustrates the threshold voltage distribution of a flash cell that is programmed in a 2-bit mode; Figure 2 is a A high-level schematic block diagram of a prior art data processing system, wherein a controller of a flash memory device is included in one of the flash memory devices; FIG. 3A and FIG. 3B are prior art data processing systems. a high-order schematic block diagram in which one controller of a flash memory device is independent of both the host of the flash memory device and the flash memory device; FIG. 4 is a high-order one of the prior art data processing systems Schematic block diagram, in which a controller of a flash memory device is included in the flash memory device; FIG. 5A is a high-order schematic block diagram of one of the controllers of the present invention; FIG. 5B is a diagram including FIG. 5A High-level schematic block diagram of the data processing system of the controller; Figures 6A through 6G illustrate various options for packaging the components of the data processing system of Figure 5B; Figure 7 is for writing data to a memory in accordance with the present invention. flow chart; Figure 8 is a flow diagram of a method of reading data from a memory in accordance with the present invention.

130. . . Controller

132. . . ECC module

134. . . Module

142. . . Flash memory device side non-interface and host side non-interface

144. . . Flash type non-interface/host side non-interface

146. . . Host side interface

Claims (35)

A controller for a flash memory device, comprising: (a) a host type non-interface for exchanging data pages with the flash memory device; and (b) a flash type An interface for exchanging data segments with a host of the controller; wherein the data pages have a common data page size, and wherein the data segments have a common data segment different from the common data page size The size, wherein the host type interface is a physical interface and the flash type interface is a logical interface. The controller of claim 1, wherein the common data segment size is smaller than the common data page size. The controller of claim 1, further comprising: (c) at least one other host side interface. The controller of claim 1, further comprising: (c) an error correction module. The controller of claim 1, further comprising: (c) an encryption module. The controller of claim 1, further comprising: (c) a bitmap mapping module. A data storage system comprising: (a) a controller as claimed in claim 1; and (b) a flash memory device as claimed in claim 1. The data storage system of claim 7, wherein the flash memory device is A non-flash memory device. The data storage system of claim 7, wherein the controller and the flash memory device are fabricated on different individual dies and wherein the host type interface is an inter-die interface. The data storage system of claim 9, further comprising: (c) a multi-chip package, the controller and the flash memory device being packaged therein. The data storage system of claim 9, further comprising: (c) a controller package for packaging the controller. The data storage system of claim 11, further comprising: (d) a memory device package for packaging the flash memory device independent of the controller package. The data storage system of claim 11, further comprising: (d) a printed circuit board on which the die is directly mounted, the flash memory device being fabricated on the die. The data storage system of claim 9, further comprising: (c) a memory device package for packaging the flash memory device. The data storage system of claim 14, further comprising: (d) a printed circuit board on which the die is directly mounted, the controller being fabricated on the die. The data storage system of claim 9, further comprising: (c) a printed circuit board on which the die is directly mounted. The data storage system of claim 7, wherein the controller and the flash memory device are fabricated on a common die. A data processing system comprising: (a) a data storage system of claim 7; and (b) a host of a data storage system of claim 7. A data storage system comprising: (a) a memory comprising a plurality of physical pages, the physical pages having a common physical page size; and (b) a circuit for outputting a flash type non-interface The flash non-interface is configured to exchange data segments with one of the data storage systems, wherein the data segments have a common data segment size different from the physical page size, wherein the flash non-interface A logical interface. The data storage system of claim 19, wherein the common data segment size is less than the common entity page size. The data storage system of claim 19, wherein each of the pages comprises a plurality of flash units. The data storage system of claim 21, wherein the flash units are not flash units. The data storage system of claim 19, wherein the memory and the circuit are fabricated on separate individual dies. The data storage system of claim 23, further comprising: (c) a multi-chip package in which the memory and the circuit are packaged. The data storage system of claim 23, further comprising: (c) a circuit package for packaging the circuit. The data storage system of claim 25, further comprising: (d) a memory for encapsulating the memory independent of the circuit package Package. The data storage system of claim 25, further comprising: (d) a printed circuit board on which the die is directly mounted, the memory being fabricated on the die. The data storage system of claim 23, further comprising: (c) a memory package for encapsulating the memory. The data storage system of claim 28, further comprising: (d) a printed circuit board on which the die is mounted directly, the circuit being fabricated on the die. The data storage system of claim 23, further comprising: (c) a printed circuit board on which the die is mounted directly. The data storage system of claim 19, wherein the memory and the circuit are fabricated on a common die. A data processing system comprising: (a) a data storage system of claim 19; and (b) a host of a data storage system of claim 19. A method of storing data, comprising the steps of: (a) providing a memory comprising a plurality of physical pages, the physical pages having a common physical page size; and (b) outputting a message to a host for use with the host a flash-type non-interface of the exchange data segment, wherein the data segments have a common data segment size different from the physical page size, wherein each of the physical pages has a respective physical address range; Each of the data sections has a respective logical sector address; (c) receiving at least one of the data sections from the host for writing to the memory; (d) mapping the logical sector address of each of the at least one data section to a corresponding physical address; and (e) writing the at least one data section to at least one physical page, the at least one physical page having the at least one of the at least one logical sector address mapped in the respective physical address range Physical address. The method of claim 33, wherein the common data segment size is less than the common entity page size. The method of claim 33, the method further comprising the steps of: (f) receiving, from the host, a command to read at least one of the data segments from the memory; (g) placing each of the at least one data region The logical sector address of the segment is mapped into a corresponding physical address; and (h) the at least one data segment is read from at least one of the physical pages, the at least one physical page being in its respective physical location The address range has the at least one physical address to which the at least one logical sector address has been mapped.