TW398084B - Multilayered indium-containing nitride buffer layer for nitride epitaxy - Google Patents

Multilayered indium-containing nitride buffer layer for nitride epitaxy Download PDF

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Publication number
TW398084B
TW398084B TW087122019A TW87122019A TW398084B TW 398084 B TW398084 B TW 398084B TW 087122019 A TW087122019 A TW 087122019A TW 87122019 A TW87122019 A TW 87122019A TW 398084 B TW398084 B TW 398084B
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Taiwan
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layer
buffer
buffer layer
indium
nitride
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TW087122019A
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Chinese (zh)
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Scott R Kern
Chang-Hua Chen
Werner Goetz
Gina L Christenson
Chih-Ping Kuo
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Hewlett Packard Co
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01Manufacture or treatment
    • H10H20/011Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/824Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/815Bodies having stress relaxation structures, e.g. buffer layers

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  • Recrystallisation Techniques (AREA)

Abstract

A semiconductor device includes a substrate (2) a buffer or nucleation structure, and an active structure (6) containing its circuit elements. The nucleation layer is fabricated at a relatively low temperature, and includes at least one layer made of a III-V nitride compound containing indium. In a multilayer structure (eg. F16.5). At least one of these layers, preferably the one (18) directly deposited on the substrate (2), is made of an indium-containing III-V nitride compound, and serves as a buffer layer. In subsequent AllnGaN epitaxy, the indium-containing layers relax. Reductions in stress and cracking result, allowing more flexibility in composition and doping modulation. Since the electrical and optical properties of the device depend on the stress and strain states present in its active structure, these properties can be tailored by controlling the composition and layer thickness of the nucleation layer. Indium-containing nitrides having advantageously high quality can be grown at relatively low temperatures.

Description

五、發明説明(1 ) 經濟部中央標準局員工消費合作社印製 發明領域 概略而言本發明係關於半導體器件領域及其製造。特 別本發明係關於薄膜沉積層於不縣材及/或既存各層上 之組合。本發明特別可應用於光電器件如S光二極 (LED)。 發明背景 基本構想 半導體製造過程概略始於基材如矽晶圓,及攙雜—系 列圖樣化層於晶圓上。各層包括攙雜半導體材料,絕緣層 如氧化物等。圖樣係使用光阻防蝕,蝕刻等技祷生產。 圖樣化層組成主動層其具有電路元件及電路設計者預 定的功能。圖樣界定電路器件及器件間之互連,因此結果 所得半導體器件具有功能。 1、膜組成 石夕(Si)及鍺(Ge)皆來自元素週期表1¥欄,為半導體製 造商之常用元素。特別多種基材係由矽製成。其中基材包 括監寳石(八丨2〇3) ’坤化鎵(GaAs)及碳化石夕(SiC)。 常用於製造半導體器件特別光電器件之材料為週期表 III及V欄元素的組合,俗稱,,ΠΙ_ν,,化合物。m攔元素包括 鋁(A1) ’鎵(Ga)及銦(In)。v攔元素包括砷(As),鱗(P)及氮 (N)。或許最常用的m_v化合物為砷化鎵(GaAs)。 一組III-V化合物合稱氮化物,用於生產圖樣化層。 特別證實氮化物可用於發光二極體(LED)技術。 氮化物化合物包括一或多種III攔元素連同V攔氮(N) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) (請先閱讀背面之注意事項本頁) 裝 訂 線 -4-V. Description of the invention (1) Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics Field of the Invention The present invention is roughly related to the field of semiconductor devices and their manufacturing. In particular, the present invention relates to a combination of thin film deposited layers on pre-existing materials and / or existing layers. The invention is particularly applicable to optoelectronic devices such as S-light diodes (LEDs). BACKGROUND OF THE INVENTION The basic idea The outline of a semiconductor manufacturing process begins with a substrate such as a silicon wafer and a doped-series patterning layer on the wafer. Each layer includes a doped semiconductor material, an insulating layer such as an oxide, and the like. The pattern is produced using photoresist, anti-corrosion, etching and other techniques. The patterning layer constitutes the active layer, which has the functions predetermined by the circuit elements and circuit designers. The pattern defines circuit devices and interconnections between devices, so the resulting semiconductor device is functional. 1. Membrane composition Shi Xi (Ge) and germanium (Ge) are from the column of the periodic table of the element 1 ¥, are common elements for semiconductor manufacturers. Particularly many substrates are made of silicon. Among them, the substrates include supervised gemstones (8, 203), gallium gallium (GaAs), and carbide carbide (SiC). The materials commonly used in the manufacture of semiconductor devices and special optoelectronic devices are the combination of elements of Periodic Table III and column V, commonly known as, ΠΙ_ν, compounds. The m element includes aluminum (A1) 'gallium (Ga) and indium (In). The v elements include arsenic (As), scale (P) and nitrogen (N). Perhaps the most commonly used m_v compound is gallium arsenide (GaAs). A group of III-V compounds are collectively called nitrides and are used to produce patterned layers. In particular, nitrides have proven useful in light-emitting diode (LED) technology. The nitride compound includes one or more III block elements together with V block nitrogen (N). This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back page first) Binding Line -4-

、發明説明(2) 。例如若僅使用得自III欄之鎵,則氮化物化合物為氮化 鎵(GaN)。但也常見含括III欄元素混合物。此種化合物例 如呈Ii^Ga^xN或AlxGai-χΝ]! ’此處下標(加總為1)之值反應 出使用之各種III攔元素之比。 上列多種材料用於沉積組成主動結構之圖樣化層。其 中一例Takeuchi等美國專利5,389,571,,使用含鋁及氮中間 層製造基於氮化鎵之半導體器件之方法,,敘述一種器件具 有(Ga^AlA.ylnyN氮化物材料晶體作為其主動結構之一部 分。 2、薄膜晶格性質 一般而言半導體材料係呈結晶晶格。表示組成材料的 原子係排列成規則圖樣如列、平面及單位儲存格。多種不 同晶袼構造皆討能。特定例之特定晶格之形成屬於組成 該晶格之材料特徵。多種因素例如組成材料之元素之離子 半控影響特定元素或化合物具有的結晶晶格構型種類。 特別當缚膜半導體材料沉積於基材時,形成主要為耳 面之薄膜-基材交界面形式。於氮化物化合物之例,最第 觀察得的晶格構型為六角形或稱,,纖維辞礦,、第i圖顯矛 六角形晶格單位之最簡單代表圖。單位儲存格具有六角形 稜aa开y式,平面上具有六角形截面(例如稱作,,水平方向” ,及垂直水平面於軸向方向行進(標示為,,垂直,,)。 為了描述六角形座標空間之特定位置使用四軸。其中 三軸係於水平面,彼此夾角⑽度,稱作&及〜。第四 軸標示為C係於垂直面。 五、發明説明(3 ) A7 B7 經濟部中央標準局員工消費合作社印製 、座標系統使用標示法(a,ia’心,4),此處 平面交又該抽之指定抽座標的倒數。 於-:面未交又一轴(亦即該平面平行該軸)時採用之值為 ^例如最簡單及最方便㈣的平面之—為頂面,其交叉 早位儲存格之頂面、六角形。該平面俗稱,,基面”平行全部三 軸。如此基面的平面標示為(0001)。 "於半導體器件組成薄膜之晶格常係以晶格參數描述。 氮化物膜概略形成於六角形晶格結構,基面平行基材表面 定向,及平行基材表面與膜間之交界面定向。如此於,,a_ 轴”表不三方向中之任_方向平行膜_基材交界面且彼此隔 開120度。” c_軸,,表示垂直薄膜_基材交界面之方向。 結晶晶格例如本說明書描述之膜層係以參數值說明例 如’’晶格常數,,及,,熱膨脹係數,,(容後詳述)。此等參數值係 以六角形座標系之a_軸及c —軸表示。 但多種薄膜晶體晶格參數於&_軸方向並無差異,因此 需要多一軸參數來作描述。如此一參數值足夠描述薄膜晶 格之交界面平行性質。於六角形晶體系統之例,例如氮化 物僅使用單一 a-軸參數。 但通常垂直薄膜-基材交界面方向之薄膜晶格性質與 平行交界面之方向之薄膜晶格性質不同。因此卜軸參數通 常具有與對應之a-轴參數不同的值。 薄膜晶格之a-抽及c-轴關聯的參數通常係有關沿各轴 規定方向之晶格結構中兩毗鄰同種原子間之間隔(亦即Ga-Ga或N-N間隔距離)。 本紙張尺度適用中國國家標準(CNS ) A4规格(210X:Z97公釐) 請 λ 聞 讀 背 之 注 意 事 項急 旁 裝 訂 線 -6- 對 不 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(4) 其中一種參數為晶格常數,此乃原子間隔之測量值。 另一種參數為熱膨脹係數,其為響應溫度變化時晶格 參數之膨脹或收縮,以每度溫度變化之間隔距離變化表示 〇 如前述,根據組成晶格之特定物質之性質形成晶格。 特別原子之離子半彳f可決定fa1距,如此決定a_軸及c_轴來 數值。 〆 但S —張膜新形成於基材上或形成於稍早沉積之膜上 時,新膜之a-轴參數傾向於遵照其下方之a_軸參數。下方 晶格強迫新一層的a_軸參數與新膜本來具有的&_軸參數不 同。因此對新膜加諸應力。 ^此外當新沉積膜之a-軸參數受下方晶格結構影響時, 薄膜的c.軸參數也同樣受影響。此處再度對新膜晶^加諸 為力。 ,,若晶格與其下方之晶格可相容,則稱呼新膜層為, 正 '換言之原子平面連續跨越兩種材料間之交界面而个 會扭曲。若晶格㈣,則薄㈣絲遭縣干應力而保持 對正:換言之组成薄膜晶格之原子可擠壓更為緊密或拉開 更為遠離’則將不存在有對正應力。 晶格被施加應力過度因此無法保持對正傾向於包括異 ,’異位屬於-型晶格結構瑕m材與薄膜間之_ 曰曰^,參數存在有夠大差異時,薄膜晶格傾向於藉由,,跳過 列或,插入額外一列,,原.子來異位應力, 一 晶格原子本身對正基材晶格。當異位至某種程度^ = 本紙張尺度適用X 2崎·Description of the invention (2). For example, if only gallium from column III is used, the nitride compound is gallium nitride (GaN). It is also common to include mixtures of elements from column III. Such compounds are, for example, Ii ^ Ga ^ xN or AlxGai-χN]! ’Here the value of the subscript (total 1) reflects the ratio of the various III elements used. Various materials listed above are used to deposit patterned layers that make up the active structure. One example is Takeuchi et al. US Patent No. 5,389,571, a method for manufacturing a gallium nitride-based semiconductor device using an intermediate layer containing aluminum and nitrogen, and describes a device having (Ga ^ AlA.ylnyN nitride material crystal as part of its active structure. 2 3. Thin film lattice properties Generally speaking, semiconductor materials are crystalline lattices. It means that the atomic systems that make up the material are arranged in a regular pattern such as columns, planes, and unit cells. Many different crystal structures are available. Specific lattices The formation is a characteristic of the material that composes the crystal lattice. Various factors such as the ionic semi-control of the elements that make up the material affect the type of crystal lattice configuration that a particular element or compound has. Especially when the film-bound semiconductor material is deposited on the substrate, it forms the main It is a film-substrate interface at the ear surface. In the case of nitride compounds, the most observed lattice configuration is hexagonal, or fiber, and the i-shaped hexagonal lattice unit is shown in Figure i. The simplest representative figure. The unit cell has hexagonal edges aa and y, and the plane has a hexagonal cross section (for example, called, horizontal ", And the vertical horizontal plane travels in the axial direction (labeled ,, vertical ,,). In order to describe the specific position of the hexagonal coordinate space, four axes are used. Among them, the three axes are in the horizontal plane and the angle between them is called & and ~. The fourth axis is marked as C on the vertical plane. V. Description of the invention (3) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, the coordinate system uses the labeling method (a, ia 'heart, 4), here Plane intersection and the reciprocal of the specified drawing coordinates. Yu-: The value used when the surface does not cross another axis (that is, the plane is parallel to the axis) is ^ For example, the simplest and most convenient plane—the top surface. The top surface of the intersecting early-stage cell is hexagonal. This plane is commonly known as, the base plane is parallel to all three axes. The plane of this base plane is labeled (0001). &Quot; The lattice of thin films that make up semiconductor devices is often It is described in terms of lattice parameters. The nitride film is roughly formed in a hexagonal lattice structure, the base surface is oriented parallel to the substrate surface, and the interface between the parallel substrate surface and the film is oriented. Thus, the "a_axis" indicates three directions Any of the _direction parallel film_ The material interface is 120 degrees apart from each other. "C_axis, which indicates the direction of the vertical film_substrate interface. Crystal lattices such as the film layer described in this specification are described with parameter values such as" lattice constant, And, the coefficient of thermal expansion, (detailed later). The values of these parameters are expressed by the a-axis and c-axis of the hexagonal coordinate system. However, there is no difference in the parameters of the crystal lattices in the & _ axis. Therefore, one more axis parameter is needed for description. Such a parameter value is sufficient to describe the parallel nature of the interface of the thin film lattice. In the case of a hexagonal crystal system, for example, nitride uses only a single a-axis parameter. However, usually the vertical thin film-based The properties of the thin film lattice in the direction of the interface of the material are different from the properties of the thin film lattice in the direction of the parallel interface. Therefore, the b-axis parameters usually have different values from the corresponding a-axis parameters. The a-pump and c-axis related parameters of the thin film lattice are usually related to the interval (ie, Ga-Ga or N-N separation distance) between two adjacent atoms of the same type in a lattice structure in a predetermined direction along each axis. This paper size applies to China National Standard (CNS) A4 (210X: Z97 mm) Please read the notes on the back side of the binding line -6- Printed on the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the Invention (4) One of the parameters is the lattice constant, which is a measurement of the atomic interval. The other parameter is the coefficient of thermal expansion, which is the expansion or contraction of the lattice parameter in response to a change in temperature, expressed as the change in the distance between each degree of temperature change. As mentioned above, a lattice is formed according to the properties of the specific substance that composes the lattice. In particular, the atomic half 彳 f can determine the fa1 distance, which determines the values of the a-axis and c_-axis. 〆 But when the S-sheet is newly formed on the substrate or formed on the earlier deposited film, the a-axis parameters of the new film tend to follow the a-axis parameters below it. The lower lattice forces the a_axis parameters of the new layer to be different from the & _axis parameters of the new film. Therefore, stress is applied to the new film. ^ In addition, when the a-axis parameters of the newly deposited film are affected by the underlying lattice structure, the c. Axis parameters of the film are also affected. Here again, force is applied to the new film crystal. If the crystal lattice is compatible with the crystal lattice below it, the new film layer will be called, "In other words, the atomic plane will cross the interface between the two materials continuously and will be distorted." If the lattice is lumped, the thin filaments will remain aligned due to the dry stress: in other words, the atoms that make up the thin film lattice can be squeezed closer or pulled apart further away, there will be no alignment stress. The lattice is overstressed and cannot be maintained. It tends to include heterogeneity. 'Ectopic belongs to the -type lattice structure defect between the material and the film _ said ^, when there is a large difference in parameters, the film lattice tends to By skipping the columns or inserting an additional column, the original heterogeneous stress causes a lattice atom itself to face the substrate lattice. When ectopic to some degree ^ = This paper size applies to X 2 Saki ·

-7- 五 ' I _ 、發明説明(5) 的曰日袼父界面所無法避免時,希望縮小異位。由於常用氮 化物材料與基材間有極大不匹配,故氮化物膜層常出現異 位。 、晶格結構形式也可能出現位置散亂之點瑕疵。點瑕疵 於原子所在位置之晶格可為一空位,雜質原子替代晶格母 值几素中之一個原子等。點瑕疵也須減至最低。製造設備 的乾淨及經過精密控制的製造環境條件可辅助減少點瑕疵 …造技術 常用於沉積各層之技術稱作,,蟲晶生長”。亦即各層係 以磊晶生長”方式沉積,各層本身稱作”磊晶生長,,層。此 種技術中材料層主要係逐原子由周圍環境沉積至基材表面 上。形成遙晶生長層之材料根據其本身之性質或根據下層 性質結晶化成為晶格,容後詳述。 此種技術實例包括有機金屬氣相磊晶生長,分子束磊 晶生長,及氫化物氣相遙晶生長。(相反地,非层晶生長 技術為材料丸粒置於基材上,加熱器件故丸粒於基材表面 熔化)。 。蟲晶生長及其他類型製造步驟概略係於比室溫高數百 度α)之溫度進行,但依據步驟類型及沉積材料類型而定 溫度可有顯著變化。 開發製造過程之-項議題為排序各步驟,因此稱後步 驟所需溫度不會有害稍早步驟的結果。 待解決之問題之陳述 本纸張尺度適财關家縣(CNS ) Α4規格⑺(^ 297公^· 8- 經濟部中央標準局員工消費合作社印製 A7 '______ B7 五、發明説明(6 ) 〜 開發半導體製法中,有多項議題需要解決俾便確保藉 該製法生產的半導體器件具有適當品質。通常,,品質,,—詞 當應用於半導體製造時表示製造出之半導體器件具有適當 功能及可靠性。 為了半導體製造品質,各層需彼此黏著及黏著於基材 ’需要具有良好電力特性及良好機械結構。 又半導體器件之品質係有關組成該器件之結晶晶格條 件。晶格結構的瑕疵對器件品質有害。因此若如前述晶格 應力加諸於被製造的膜層時,需要限制或至少控制應力對 膜晶格的影響。 處理氮化物磊晶生長之合併問題為裂痕問題。裂痕發 生於磊晶生長膜係於拉張條件下被拉扯以及受到前述應力 時發生。通常裂痕係垂直膜-基材交界面。 此種裂痕之可能原因有數種: ⑴組成基材與膜之物質間之晶格配置差異造成基材 與膜間之晶格不匹配, (ii) 組成基材與膜之材料間之熱膨脹係數不匹配, (iii) 材料之攙雜程度高,及 (W)由於氮化物器件生長期間蓄意引進的有意組成調 整,亦即組成製造材料之化學改變造成晶格不匹配。 例如AlInGaN層於典型高於1100〇c之生長溫度生長而 不具緩衝層效果,結果導致由六角形核鑲嵌組裝形成的膜 。各層具有極為粗糙之形態及極高背景給予者濃度。結果 其具有特徵⑴及(iii)且容易裂開。 本紙張尺度適用中國國家標準(CNS ) Α4» ( 21GX297公釐) (請先閱讀背面之注意事項一^寫本頁} 裝_ 訂 —線- ❿ -9 --7- When it is unavoidable that the sun-daddy father interface of the invention description (5) is unavoidable, it is desirable to reduce the ectopic. Because there is a great mismatch between commonly used nitride materials and the substrate, the nitride film layer often appears ectopic. 2. The lattice structure form may also have spot defects with scattered locations. Point defects The lattice at the position of the atom may be a vacancy, and an impurity atom replaces one atom in the lattice mother value. Point defects must also be minimized. Clean manufacturing equipment and precisely controlled manufacturing environment conditions can help reduce point defects ... The technology commonly used to deposit layers is called, worm crystal growth. "That is, each layer is deposited by epitaxial growth." Each layer itself is called "Epitaxial growth, layer. In this technique, the material layer is mainly deposited on the surface of the substrate atomically from the surrounding environment. The material forming the telecrystalline growth layer is crystallized into a crystal lattice according to its own properties or according to the underlying properties. Examples of such techniques include organic metal vapor phase epitaxial growth, molecular beam epitaxial growth, and hydride vapor phase telemorphic growth. (In contrast, non-stratified crystal growth technology uses material pellets on the substrate. On the material, the heating device so that the pellets are melted on the surface of the substrate.) The growth of worm crystals and other types of manufacturing steps is roughly performed at a temperature hundreds of degrees higher than room temperature α), but it depends on the type of step and the type of deposition material Significant changes can be made. One of the issues in the development and manufacturing process is to order the steps, so the temperature required for the later steps is not harmful to the results of the earlier steps. To be resolved Statement of the problem The paper size is suitable for financial affairs in Guanjia County (CNS) Α4 specification⑺ (^ 297 公 ^ · 8- Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7' ______ B7 V. Description of the invention (6) ~ Development of semiconductor In the manufacturing method, there are a number of issues that need to be resolved in order to ensure that the semiconductor device produced by the manufacturing method has the appropriate quality. Generally, quality, when used in semiconductor manufacturing, indicates that the manufactured semiconductor device has the proper function and reliability. For semiconductor manufacturing quality, the layers need to adhere to each other and to the substrate 'need to have good electrical characteristics and good mechanical structure. The quality of a semiconductor device is related to the crystal lattice conditions that make up the device. Defects in the lattice structure are detrimental to the quality of the device. Therefore, if the lattice stress is applied to the film layer as described above, it is necessary to limit or at least control the effect of the stress on the film lattice. The problem of combining the epitaxial growth of nitride is the problem of cracks. The cracks occur in the epitaxial growth film It occurs when it is pulled under tension and under the aforementioned stress. Usually the crack is the vertical film-substrate interface There are several possible reasons for such cracks: ⑴ The difference in the lattice configuration between the materials that make up the substrate and the film causes the lattice mismatch between the substrate and the film, (ii) the coefficient of thermal expansion between the material that makes up the substrate and the film Mismatches, (iii) high degree of doping of materials, and (W) intentional composition adjustments deliberately introduced during the growth of nitride devices, that is, lattice mismatches caused by chemical changes in the composition of the manufacturing materials. For example, the AlInGaN layer is typically higher than It grows at a growth temperature of 1100 ° C without a buffer layer effect, resulting in a film formed by hexagonal core mosaic assembly. Each layer has an extremely rough morphology and a high background donor concentration. As a result, it has characteristics ⑴ and (iii) and is easy The paper size is applicable to the Chinese National Standard (CNS) Α4 »(21GX297 mm) (Please read the precautions on the back first ^ write this page} Binding-Thread-❿ -9-

經濟部中央標準局員工消費合作社印製 晶格及熱膨脹係數不匹配 風半導體材料之特徵為晶格常數,材料之結晶結構之數 學特徵化。又如同任何其他材料,半導體材料具有隨著溫 度改變之熱膨脹係數,熱膨脹係數為材料如何膨脹或收縮 之測量值。 彼此毗鄰之各層具有相同或相容之晶格形式俾便獲得 良好黏著。晶格形式不相容導致黏著性不良,使各層分離 因而使電氣性質劣化。 又毗鄰各層之熱膨脹係數須儘可能類似,故當一層膨 脹比另一層更多時,温度變化不會導致層分離。此點^別 重要’原因為半導體器件之製造通f係於比較ϋ件儲存及 使用之溫度遠更高溫進行。當器件成品冷卻至室溫時出現 相當大熱收縮。 習知LED構造;緩衝層 基於氮化物之LED典型包含⑴基材,(ii)凝核或緩衝 結構,及(iii)主動結構。本發明係關於緩衝結構。如此附 圖顯示器件結構,全圖顯示緩衝結構為單層,及一,,放大 鏡對中於單層缓衝結構,提供缓衝結構之結構組成上的 放大細節視圖。 先前技術及本發明之附圖提供代表性層厚度,以埃單 位表示。可使用此等值或業界人士已知之其他值。 又於後文討論中各層彼此”堆疊”於其上^,,堆疊,,一 1 絕非意圖將結構限制於一層係製造於或設置於另一層頂端 之結構。該術語廣義而言包括藉任一種製造技術生產結構 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics. Lattice and thermal expansion coefficients do not match. The characteristics of wind semiconductor materials are the lattice constants and the mathematical characteristics of the material's crystal structure. As with any other material, a semiconductor material has a coefficient of thermal expansion that changes with temperature. The coefficient of thermal expansion is a measure of how the material expands or contracts. Adjacent layers have the same or compatible lattice form, and good adhesion is obtained. The incompatibility of the lattice forms leads to poor adhesion, which separates the layers and thus deteriorates the electrical properties. The thermal expansion coefficients of the adjacent layers must be as similar as possible, so when one layer expands more than the other layer, the temperature change will not cause the layers to separate. This point is important, because the semiconductor device is manufactured at a much higher temperature than the temperature at which it is stored and used. Considerable thermal shrinkage occurs when the finished device is cooled to room temperature. Known LED structures; buffer layers. Nitride-based LEDs typically include a plutonium substrate, (ii) a nuclei or buffer structure, and (iii) an active structure. The present invention relates to a buffer structure. The attached picture shows the device structure, the full picture shows that the buffer structure is a single layer, and one, the magnifying lens is centered on the single layer buffer structure, providing an enlarged detail view of the structural composition of the buffer structure. The prior art and drawings of the present invention provide representative layer thicknesses in Angstrom units. These values or other values known to those skilled in the art can be used. Also in the following discussion, the layers are "stacked" on top of each other ^, stacked ,, 1-1 is by no means intended to limit the structure to a structure that is manufactured or placed on top of another layer. The term broadly includes the use of any manufacturing technology to produce the structure. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm).

(請先閱讀背面之注意事項H -裝—I Γ本頁} 訂 —線 Φ -10- 經濟部中央標準局員工消費合作社印製 A7 —""~ ------ B7 五、發明説明(^ ' ~-- 日’ ^基於本說明書為業界人士已知或為適當結構。就本說 月書而吕唯一限制、明示或暗示的限制係有關缓衝層製造 及主動層磊晶生長等之相對低溫及高溫,如所述。 、因本發明可應用於LED技術,故對主動LED結構之略 為細節說明列舉作為範例說明例。led主動結構包括^型 層及P-型層間之主動層及接點。但需瞭解此等元件並非本 發明所必要而僅供舉例說明之用。 第2圖:習知器件 〃習知半導體器件特別俗稱氮化物LED之示意圖顯示於 第t圖。基材顯示為2,及凝核或缓衝結構顯示為4。基材2 為藍寶名(ΑΙΑ),碳化石夕(Sic)等。主動結構概略顯示為6 電路元件,互連體等製造於主動結構6内部。主動結 構之規格並非本發明所必要,故主動結構將不再詳細討論 ’僅於此處舉例說明。 本例顯示之典型LED之主動結構6包括一主動區8介於 型層10與n-型層12間。層1G及12包括電路元件,互連體 等且载有接點14及16。,,主動區,,一詞常用於LED領域。此 處,,主動結構,,-詞涵蓋層8、1〇及12,及接點14及16以及 其他含括於其他使用緩衝層之器件包括習知緩衝層或根據 此處所述本發明之緩衝層的電路元件及結構。 習用於控制裂開、形態及背景載子導電係數之有效方 法為插入緩衝結構4。緩衝結構4含有一層稱作緩衝層或凝 核層,二名詞乃同義字。 本紙張尺度適用中國國家標格(2丨ox297公5 I---,------ΜII (請先閲讀背面之注意事項再本頁) 訂 —線- -11- A7 B7 五、發明説明(9) 對於於藍寶石基材上製造的器件而言,缓衝層典型係 於400-900°C沉積。若基材為碳化矽(SiC),則緩衝層之沉 積係於又更高溫(例如高於900°C)進行。雖言如此,此種 溫度通常比其他類型沉積步驟如磊晶生長溫度更低,但無 需排除於高於其他沉積步驟使用之溫度更高溫進行沉積。 凝核層或緩衝層係於額外各層如主動結構6生長前沉 積。組成主動結構6之各層常係於比較緩衝層使用溫度更 高溫沉積。額外各層如磊晶生長氮化物膜之品質於缓衝層 已經於額外各層下方製造緩衝層時大為改善。 習知緩衝層包括二元化合物A1N及GaN之一,或某種 AlGaN組成介於兩種二元化合物之間。精律言之,中間組 成標不為A1 xG a 1 _XN ’此處X為0與1間之值。 插入此種低溫層可克服下列各者間之巨大差異:⑴ 晶格參數,(ii)熱膨脹,(iii)表面能,及(iv)藍寶石基材與 氮化物磊晶生長層間之晶相學。但習知緩衝層有其限制, 容後詳述。 攙雜及組成調整 典型基於氮化物之器件中,膜層經過重度攙雜。攙雜 劑濃度於典型光電子器件常超過1018-1019cm-3。 典型基於氮化物之器件也具有若干組成非均質磊晶生 長交界面。幾乎全部電子及光電子器件係由具有不同組成 之各層彼此沉積於其上組成。非均質交界面為具有不同組 成之兩層間之交界面。例如具有不同組成、導電類型及厚 度之GaN,AlGaN及InGaN,各層直接沉積於彼此之交界 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) -12-(Please read the precautions on the back H-installation—I Γ This page} Order—line Φ -10- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 — " " ~ ------ B7 V. DESCRIPTION OF THE INVENTION (^ '~-日' ^ Based on this description, it is known to the industry or is an appropriate structure. The only limitation, explicit or implied, in this book is related to buffer layer manufacturing and active layer epitaxy. The relatively low temperature and high temperature of growth, etc., are described. As the present invention can be applied to LED technology, a slightly detailed description of the active LED structure is given as an example. The LED active structure includes a ^ -type layer and a P-type layer. Active layer and contacts. However, it should be understood that these components are not necessary for the present invention and are provided for illustration purposes only. Figure 2: Known devices. Known semiconductor devices are commonly referred to as nitride LEDs. Figure t is shown. The substrate is shown as 2, and the nucleation or buffer structure is shown as 4. The substrate 2 is Sapphire (ΑΙΑ), carbonized stone (Sic), etc. The active structure is shown as 6 circuit elements, interconnects, etc. Inside the active structure 6. The specifications of the active structure are not the original As necessary, the active structure will not be discussed in detail. 'This is only illustrated here. The active structure 6 of a typical LED shown in this example includes an active area 8 between the type layer 10 and the n-type layer 12. Layer 1G and 12 includes circuit elements, interconnects, etc. and contains contacts 14 and 16. The term active area is commonly used in the field of LEDs. Here, the term active structure covers the layers 8, 10, and 12, And contacts 14 and 16 and other devices included in other buffer layers include conventional buffer layers or circuit elements and structures of the buffer layer of the present invention as described herein. Used to control cracking, morphology, and background carriers. An effective method for the conductivity is to insert a buffer structure 4. The buffer structure 4 contains a layer called a buffer layer or a nucleation layer, and the two nouns are synonymous. This paper scale applies to the Chinese national standard (2 丨 ox297 公 5 I ---, ------ ΜII (Please read the precautions on the back before this page) Order—line- -11- A7 B7 V. Description of the invention (9) For devices manufactured on sapphire substrates, the buffer layer Typically deposited at 400-900 ° C. If the substrate is silicon carbide (SiC), the buffer layer is deposited It is performed at a higher temperature (for example, higher than 900 ° C). However, this temperature is usually lower than other types of deposition steps, such as epitaxial growth, but it does not need to be excluded from higher temperatures used in other deposition steps The core layer or the buffer layer is deposited before the growth of additional layers such as the active structure 6. The layers constituting the active structure 6 are usually deposited at a higher temperature than the buffer layer. The additional layers such as epitaxial growth nitride film quality The buffer layer is greatly improved when the buffer layer has been manufactured under the additional layers. It is known that the buffer layer includes one of the binary compounds A1N and GaN, or an AlGaN composition between the two binary compounds. In essence, the middle component is not labeled A1 xG a 1 _XN ′ where X is a value between 0 and 1. The insertion of such a low temperature layer can overcome the huge differences between: ⑴ lattice parameters, (ii) thermal expansion, (iii) surface energy, and (iv) crystallography between the sapphire substrate and the nitride epitaxial growth layer. However, the conventional buffer layer has its limitations, which will be described in detail later. Doping and Composition Adjustment In typical nitride-based devices, the film is heavily doped. The dopant concentration in typical optoelectronic devices often exceeds 1018-1019cm-3. Typical nitride-based devices also have several heterogeneous epitaxial growth interfaces. Almost all electronic and optoelectronic devices consist of layers having different compositions deposited on each other. A heterogeneous interface is an interface between two layers with different compositions. For example, GaN, AlGaN, and InGaN with different compositions, conductivity types, and thicknesses are directly deposited on the boundary of each other. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -12-

經濟部中央襟準局員工消費合作社印製 面而生產光電子器件如LED。 攙雜及非均質交界面皆影響晶格參數。a-軸及c_軸晶 格參數資料’及氮化物及常用基材後切及藍寶石)之: 膨脹係數示於表1(第3圖)。 … 當GaN層為以石夕攙雜之n_型時,裂痕造成顯著問題。 石夕原子佔據晶格中Ga原子位置。Si之離子半徑比仏之離 子半徑小30°/。以上。結果si原子對於其於晶格内佔據之空 間而言’’過小” ’ Si原子周圍的額外空間藉由於晶體產生應 力與應變場而使晶格弱化。 ~ 當具有不同組成之各層彼此沉積於其上時也造成裂痕 問題。裂痕於生長於頂上該層具有比下方該層之&_軸晶格 參數更小時特別困擾,原因為⑴劣氮化物具有之彈性常 數極為剛硬故。 此外由氮化物層組成之非均質結構通常沿心軸對正, a-軸為基材-薄膜交界面之平行軸。如此當一層之關聯卜轴 參數比其下方該層之a_軸參數小時,於該層誘出抗拉應力 而使交界面保持對正。 結論 雖然晶格及熱不匹配關聯的問題可使用現有凝核層技 術以及經由控制生長時關聯的加熱與冷卻條件充分解決, 但因攙雜及組成起伏波動造成的裂痕無法藉此等方法解決 〇 因此仍然需要有一層半導體器件及此種器件之製造方 法’其可克服由於攙雜及組成起伏波動造成的裂痕問 本紙張尺度適用中國國家襟準(CNS ) A4規格(210X297公釐)Employees of the Cooperative Bureau of the Ministry of Economic Affairs print the surface of consumer cooperatives and produce optoelectronic devices such as LEDs. Both doped and heterogeneous interfaces affect the lattice parameters. a-axis and c_axis lattice parameter data ’and nitride and common substrate back-cut and sapphire): The expansion coefficients are shown in Table 1 (Figure 3). … When the GaN layer is of the n_ type doped with Shi Xi, cracks cause significant problems. Shi Xi atoms occupy Ga atom positions in the lattice. The ionic radius of Si is 30 ° / smaller than the ion radius of tritium. the above. As a result, the si atom is "too small" for the space it occupies in the crystal lattice. The extra space around the Si atom weakens the crystal lattice due to the stress and strain fields generated by the crystal. ~ When layers with different compositions are deposited on each other It also caused the problem of cracks when cracking. Cracks growing on top of this layer have a smaller & _axis lattice parameter than that of the layer below which is particularly troublesome because the elastic constants of inferior nitrides are extremely rigid. In addition, nitrogen The heterogeneous structure of the compound layer is usually aligned along the mandrel, and the a-axis is the parallel axis of the substrate-film interface. So when the associated axis parameter of a layer is smaller than the a_axis parameter of the layer below, The layer induces tensile stress and keeps the interface aligned. CONCLUSION Although the problems associated with lattice and thermal mismatch can be fully solved using existing core layer technology and by controlling the heating and cooling conditions associated with growth, the The cracks caused by the composition fluctuations cannot be solved by such methods. Therefore, there is still a need for a layer of semiconductor devices and a method of manufacturing such devices. The composition of the rift caused by fluctuations asked this paper applies China national scale quasi-breasted (CNS) A4 size (210X297 mm)

-13 - 經濟部十央橾準局員工消費合作社印製 ~~~----~~-------67 五、發明説明(11 ) ' --- 發明概述 因此本發明之—目的係提供-種III_V氮化物半導體 器件,其經配方可達到高品質層及器件,及克服此等層及 器件中因攙雜及組成起伏波動造成的裂痕問題。 、本發明之又-目的係提供一種半導體器件,其係調配 成可克服全部前述裂痕的問題。 為了達到此等及其他目的,根據本發明提供一種半導 體器件其概略具有基材,主動結構及緩衝結構介於基材鱼 主動層間。 緩衝結構包括-層或多層。特別於多層結構令,其中 至少-層較佳直接沉積於基材上該層係由m_v氮化物化 合物製成’其中ΙΠ攔含量全然或部分由銦組成。根據本 發明含銦層係作為緩衝層。 發現根據本發明之含銦出劣氮化物緩衝層由於主動 結構出現的應變受調整,故獲得裂痕減少的優點。 本發明可優異地用於A1InGaN蟲晶生長。藉由於緩衝 層上凝核氮化物膜’由於含InN之層鬆他使應力及裂痕減 少,結果使組成及攙雜調整上更有彈性變化。 因氮化物之電力及光學性質係依據應力與應變狀態決 定,故此等性質可藉由控制凝核層之組成及層厚度修改碉 111攔材料全然為銦,使缓衝層化合物變成InN。廣義 D之,緩衝層可為任一種適當鋁鎵銦氮化物中間物。此中 間物概略表示,此處Ogxgi及〇 j。 本紙張尺) A4規格( 21 OX 297 公釐)~ '~~~-13-Printed by the Consumers 'Cooperatives of the Shiyang Municipal Prospective Bureau of the Ministry of Economic Affairs ~~~ ---- ~~ ------------ 67 V. Description of Invention (11)' --- Summary of Invention Therefore, this invention- The purpose is to provide a type of III_V nitride semiconductor device, which can be formulated to achieve high-quality layers and devices, and to overcome the problems of cracks caused by doping and fluctuations in the composition of these layers and devices. Another object of the present invention is to provide a semiconductor device which is configured to overcome all the aforementioned problems of cracks. In order to achieve these and other objects, a semiconductor device according to the present invention is provided with a substrate, and an active structure and a buffer structure are interposed between the active layers of the substrate. The buffer structure includes one or more layers. Especially for multi-layer structures, at least one layer is preferably deposited directly on the substrate. The layer is made of m_v nitride compound, wherein the content of Ill is completely or partially composed of indium. The indium-containing layer according to the present invention serves as a buffer layer. It was found that the indium-containing inferior nitride buffer layer according to the present invention has the advantage of reducing cracks due to the adjustment of the strain occurring in the active structure. The invention can be used for A1InGaN vermiculite growth. By nucleating the nitride film on the buffer layer ', the stress and cracks are reduced by loosening the layer containing InN, resulting in more elastic changes in composition and doping adjustment. Because the electrical and optical properties of nitrides are determined based on the stress and strain states, these properties can be modified by controlling the composition and thickness of the nuclei layer. The material of 111 is completely indium, so that the buffer layer compound becomes InN. In the broad sense of D, the buffer layer can be any suitable aluminum gallium indium nitride intermediate. This intermediate is schematically shown here as Ogxgi and θj. This paper ruler) A4 size (21 OX 297 mm) ~ '~~~

-14- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(12 ) 多種III欄元素之特定性質將就本發明之多種具體例 之討論列舉如後。實驗驗證此等特定比例可產生效果良好 的緩衝結構。但本發明廣義而言含括其他組成及厚度。 此外因高品質InGaN層可於遠低於GaN,A1N及AlGaN 使用之溫度(低於800°C相對於高於l〇〇〇°C)之溫度生長, 故含InN及InGaN之緩衝層具有優異的高結構品質,此乃 先前業界製造技術所無法達成者。 進一步根據本發明,緩衝結構包括一蓋層於頂上。蓋 層可為GaN,A1N或適當AlInGaN中間層。一般而言,含 特定分量銦之III-V氮化物緩衝層可由含較少銦分量之III-V氮化物蓋層遮蓋,此處各分量係對隨後磊晶生長步驟溫 度做適當選擇。 蓋層提供之額外優點為於製造過程中,於緩衝結構沉 積之後接著為高溫主動結構沉積步驟時,蓋可保持其餘緩 衝結構定位,且保護緩衝結構不受高溫造成的有害影響。 也相信使用多步驟式凝核層造成應變狀態改變也對電 氣性質及本發明之LED器件性能具有有利影響。 圖式之簡單說明 第1圖為晶格及晶格關聯轴之不意透視圖。 第2A及2B圖為示意圖顯示習知氮化物LED之製造。 第3圖為表也標示為”表I”,列舉氮化物及基材材料之 參數值。 第4A及4B圖為示意圖顯示根據本發明之第一基本具 體例之氮化物LED之製造。 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) I 坤衣 訂 線 (請先閱讀背面之注意事項再V"本頁) 經濟部中央標隼局員工消費合作社印裝 A7 B7五、發明説明(13 ) 第5A、5B、6A及6B圖為示意圖顯示根據本發明之第 一類氮化物LED之製造,該等具體例有多層緩衝層。 第 7A、7B、8A、8B、9A、9B、10A及 10B 圖為示意 圖顯示根據本發明之第二類具體例之氮化物LED之製造, 該等具體例有一蓋層。 第11圖為線圖稱作’’SIMS深度側錄”顯示第9圖之器件 特徵。 第12圖為表也標示為”表Π”,列舉第9圖器件之測量 值。 第13A、13B、14A、14B、15A及15B圖為示意圖顯示 根據本發明之第三類具體例之氮化物LED之製造,該等具 體例具有重複(或接近重複)之次級結構於缓衝結構内部。 第16圖為表,標示為”表ΙΙΓ列舉根據本發明之若干器 件之性能資料。 第17圖為表,也標示為”表IV”,顯示進一步性能資料 〇 較佳具體例之詳細說明 根據本發明,低溫凝核層係由數層具有不同組成之分 立層組成。特別多層構造中其中至少一層,較佳為直接沉 積於基材上該層係由含銦氮化物組成作為用於AlInGaN磊 晶生長之緩衝層。 通常本發明可以兩種方式具體表現。常見一層含铟氮 化物化合物緩衝層直接設置於基材上。相反地,習知緩衝 層化合物僅含得自III欄之鋁或鎵。具體表現本發明之兩 I---------批衣----^---^11------# (請先閱讀背面之注意事項再、寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -16- 經濟部中央標準局員工消費合作社印製 . A7 B7 五、發明説明(14 ) 種方式之差異為缓衝層一方面為InN(僅包括得自III欄之銦 ),及它方面包括含銦及另一種III櫊元素較佳為嫁之化合 物。該化合物例如可配方為GajjIrikN,此處0<x< 1。 InN於約1100°C左右熔化接近GaN磊晶生長溫度。但 因銦與氮原子彼此鍵結相對脆弱,故InN晶格可能於此溫 度或甚至略低溫度分解。例如考慮一種情況,此處於InN 缓衝層沉積後,進行隨後GaN磊晶生長步驟用於形成主動 結構層。因GaN蟲晶生長步驟之溫度相當高,故下方InN 層熔化或”鬆弛”。此種下方InN緩衝層鬆弛可藉由提供基 材與薄膜間之服貼程度降低裂開傾向。 因本發明使用之InN及其他銦化合物之熔點相當低, 故發現恰於含銦缓衝層上方需要提供蓋層較佳為GaN層。 當含铜層於高溫蟲晶生長步驟期間鬆·弛時,InN層由材料 蓋層約束,該材料於該溫範圍保持固體。為求簡明起見, 本說明書將就InGaN/GaN缓衝層的說明,需瞭解所述結構 實際上例如為InGaN缓衝層於GaN蓋層下方。缓衝層及蓋 層二者皆屬於基材與主動結構間之總缓衝結構之一部分。 具體例 有無數可能的本發明之具體例。其中多個具體例可分 類成多類具體例。將說明本發明之第一基本具體例,然後 說明其他類別具體例為基本具體例之變化或衍伸。 第一具體例:單一缓衝層(第4圖) 第4圖以最簡單具體例說明本發明有單一缓衝層16, 同第2圖,但根據本發明缓衝層4係由含銦之氮化物化合物 (請先閱讀背面之注意事項本頁) 裝· 訂 線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -17- A7 B7 五、發明説明(15 ) 組成。 式 通常根據本發明使用之含銦III-V氮化物具有如下形 I---;------批衣-- (請先閱讀背面之注意事項再本頁)-14- Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (12) The specific properties of the various elements in column III will be enumerated below for a discussion of various specific examples of the invention. Experiments have verified that these specific ratios can produce a buffer structure with good results. However, the present invention broadly includes other compositions and thicknesses. In addition, high-quality InGaN layers can be grown at temperatures much lower than the temperatures used by GaN, A1N, and AlGaN (below 800 ° C vs. 1000 ° C), so the buffer layer containing InN and InGaN is excellent. High structural quality, which is impossible to achieve by previous industry manufacturing technology. Further according to the present invention, the buffer structure includes a cover layer on top. The capping layer may be GaN, A1N or a suitable AlInGaN interlayer. Generally speaking, a III-V nitride buffer layer containing a specific amount of indium can be covered by a III-V nitride capping layer containing a smaller amount of indium. Here, each component is an appropriate choice for the temperature of the subsequent epitaxial growth step. An additional advantage provided by the capping layer is that during the manufacturing process, after the buffer structure is deposited, followed by a high-temperature active structure deposition step, the cap can maintain the positioning of the remaining buffer structures and protect the buffer structure from the harmful effects of high temperatures. It is also believed that the change in strain state caused by the use of a multi-step nuclei layer also has a beneficial effect on electrical properties and the performance of the LED device of the present invention. Brief Description of the Drawings Figure 1 is an unintended perspective view of the lattice and its associated axes. Figures 2A and 2B are schematic diagrams showing the manufacturing of a conventional nitride LED. Figure 3 is a table also labeled "Table I", which lists the parameter values of nitrides and substrate materials. Figures 4A and 4B are schematic views showing the manufacture of a nitride LED according to the first basic specific example of the present invention. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) I. Knitwear Thread (please read the precautions on the back before V " this page) Printed by A7, Consumers Cooperative of Central Bureau of Standards, Ministry of Economic Affairs B7 V. Description of the invention (13) Figures 5A, 5B, 6A, and 6B are schematic diagrams showing the manufacture of the first type of nitride LED according to the present invention. These specific examples have multiple buffer layers. 7A, 7B, 8A, 8B, 9A, 9B, 10A, and 10B are schematic diagrams showing the manufacture of nitride LEDs according to the second specific example of the present invention, which has a cover layer. Figure 11 is a line diagram called "SIMS Depth Profile" showing the device characteristics of Figure 9. Figure 12 is a table also marked as "Table Π", enumerating the measured values of the device of Figure 9. 13A, 13B, 14A, 14B, 15A, and 15B are schematic diagrams showing the manufacture of nitride LEDs according to the third specific example of the present invention, which has a repeating (or nearly repeating) secondary structure inside the buffer structure. 16 The figure is a table, labeled "Table III" lists performance data of several devices according to the present invention. Figure 17 is a table, also labeled "Table IV", showing further performance information. 〇 Detailed description of the preferred specific examples According to the present invention, the low-temperature core layer is composed of several discrete layers with different compositions. In particular, at least one of the multilayer structures is preferably directly deposited on the substrate. This layer is composed of an indium-containing nitride as a buffer layer for AlInGaN epitaxial growth. Generally, the present invention can be embodied in two ways. A buffer layer containing an indium nitride compound is usually disposed directly on the substrate. In contrast, conventional buffer layer compounds contain only aluminum or gallium from column III. Specific performance of the two aspects of the present invention I --------- batch clothes ^^-^ 11 ------ # (Please read the precautions on the back before writing this page) Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -16- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7 V. Description of the invention (14) The difference between the methods is that the buffer layer is on the one hand InN (including only indium from column III), and other aspects thereof include compounds containing indium and another III element, which are preferably married. This compound can be formulated, for example, as GajjIrikN, where 0 < x < 1. InN melts at about 1100 ° C, which is close to the GaN epitaxial growth temperature. However, because the bonding of indium and nitrogen atoms is relatively fragile, the InN lattice may decompose at this temperature or even slightly lower. For example, consider a case where after the InN buffer layer is deposited, a subsequent GaN epitaxial growth step is performed to form an active structure layer. Because the temperature of the GaN vermicular growth step is quite high, the underlying InN layer melts or "relaxes". This relaxation of the underlying InN buffer layer can reduce the tendency to crack by providing a conformation between the substrate and the film. Because the melting points of InN and other indium compounds used in the present invention are relatively low, it is found that it is necessary to provide a capping layer, preferably a GaN layer, just above the indium-containing buffer layer. When the copper-containing layer relaxes and relaxes during the high-temperature worm crystal growth step, the InN layer is constrained by the capping layer of the material, which remains solid in this temperature range. For the sake of brevity, this specification will describe the InGaN / GaN buffer layer. It should be understood that the structure is actually an InGaN buffer layer under the GaN cap layer. Both the buffer layer and the cap layer are part of the total buffer structure between the substrate and the active structure. Specific examples There are countless possible specific examples of the invention. Multiple specific cases can be classified into multiple types of specific cases. The first basic specific example of the present invention will be described, and then other types of specific examples will be described as variations or extensions of the basic specific examples. First specific example: single buffer layer (Figure 4) Figure 4 illustrates the simplest and specific example of the present invention with a single buffer layer 16, the same as Figure 2, but according to the present invention, the buffer layer 4 is made of indium-containing Nitride compounds (please read the notes on the back page first) Binding and binding The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -17- A7 B7 5. Composition of the invention (15). Formula The indium-containing III-V nitride usually used in accordance with the present invention has the following shape I ---; ----- batch coating-(Please read the precautions on the back before this page)

AlxInyGai-x-yN,其中0<ySl及OSxSl。 亦即該化合物除銦之外含有紹及/或鎵。 除了此種基本緩衝結構外,無數本發明具體例具有緩 衝結構包括多層’其中部分層或全部各層作為緩衝層。若 干具體例可分成多類’以下舉例討論該等具體例類;。右 第一類具體例:多層 第5圖顯示-種緩衝結構,其中第一缓衝層係直接 設置於基材上,及第二缓衝層2〇係設置於第一緩衝層^上 。至於第5圖所示化學式,兩層皆為含鋼氣化物化合物, 但ΠΙ攔元素之仙比值與兩層不同。第—層18為_未含 仏仙。但第二層2Q之111欄部分非為純銦,但可為純銘 或純鎵。總而言之,第二層2〇含有比第—層18更少的姻。 第6圖顯示類似第,之緩衝結構,但第三緩衝層切系 設置於第二緩衝層20上。遵照第6圖列舉之化學式,第一 經濟部中央標準局員工消費合作社印製 緩衝層18含若干銦,第二緩衝層2〇含有比第—層2〇更少的 銦,而第三緩衝層22又更少。 第5及6圖之具體例相信屬於本發明之第—類具體例。 第-類具體例有多層含銦緩衝層。雖然顯示兩層及三層之 緩衝結構但也可使用額外緩衝層。 此類具體例之共通點為各層調配成其係於隨後之製造 步驟如蟲晶生長步驟溫度藉鬆弛而作為緩衝層。下述其他 Μ氏張尺度適财_家縣(CNS)AW ( 210^1^7 -18- 經濟部中央標準局員工消費合作社印製 A7 —-------—_ B7_ 五、發明説明" —~ 類具體例於缓衝結構内有其他類型之緩衝層。 第二類具體例:蓋層:第7、8、9及10圖 第7、8、9及1〇圖示例說明本發明之第二類具體例。 此等具體例中,緩衝結構包括蓋層設置於缓衝層上方。 第7及8圖中缓衝結構係以大類化學組成表示。第9及} 〇 圖分別對應於第7及8圖之結構,但第9及10圖提供製造與 使用之器件具體例。 〜 較佳提供一蓋層,此處整體製作過程包括高溫步驟如, 製ia緩衝、^構後之蟲晶生長步驟。已經沉積的含銦缓衝層 於同/狐下鬆弛。蓋層較佳約東含銦材料定位(概略參考第7 及8圖)。如此蓋層係由更可忍受稍後製造步驟之高溫的 ΠΙ-V氣化物材料製成。氮化鎵(第$及聞)為較佳蓋層材 ;斗4依據日日生長步驟溫度而定,蓋層可含銦或其他出 類元素。 現在參照第7圖,其中顯示蓋層類別之第一具體例。 s钔缓衝層24由篕層26覆蓋,蓋層配方可列舉為如上使用 之III V氮化物通式。含銦緩衝層具有上列任一種化學 配方。—般而f,蓋層26含有較少量姻,經選擇而減少於 稍後製造步驟溫度時鬆弛的傾向。 但第9圖之特例中,相對小量銦含量僅占20%銦,差 胃為鎵提供於緩衝層24。該厚度被成功地使用,但精確厚 度對本發明而s無特殊限制,故可使用其他厚度。下列有 關厚度ΐ料對藉此方式製造之結構性能進行說明。此種配 方適σ用於一種态件,其主動結構將於夠高溫製造因此缓 度適用中國國- (請先閱讀背面之注意事項寫本頁) fe® -裝. 訂 -19- 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(Π ) 衝層24即使含中等量之銦仍然保持鬆弛。 第8圖顯示另一蓋層具體例,其中有二缓衝層28及30 設置於蓋層32下方。再度缓衝層28及30及蓋層32係以化學 組成之通式標示。第一缓衝層28(直接位於基材上方)之銦 含量高可獲得良好鬆弛。第二缓衝層30含有銦含量較少之 III欄元素混合物。 再度,第10圖顯示更特定結構。提供純InN層28用於 獲得最大鬆弛及應力解除,提供含較少量銦之中間層30俾 獲得高溫時之較佳穩定性,提供GaN蓋層32用於高溫時約 束下方二層28及30。GaN蓋層可忍受此種高溫製造步驟。 所示特例中,中層3 0為銦鎵氮化物,此處銦含量再度至多 僅20%而提供於主動結構製造時之高溫下,鬆弛與結構穩 定性間之良好平衡。 第11圖以’’SIMS深度侧錄”形式呈現第9圖具體例之實 驗資料。頭字語SIMS代表二次離子質譜術。SIMS圖繪圖 二次離子數目呈器件表面下方深度之函數。 SIMS深度侧錄(profile)為線圖顯示第9圖說明之得自 於凝核層上生長的單層η-型(矽攙雜)GaN層之SIMS侧錄的 N及In轨線。InGaN缓衝層與藍寶石基材之交界面深度約 為0.8微米。 對兩種元素氮及銦提供離子數目。氮曲線於線圖之大 部分領域為常數。此點合理,原因為大半領域皆對應氮化 物層。薄膜含有約50%氮,基材大致不含氮。因此於約0.8 微米深度氮數目劇降,該處為基材-薄膜交界面。 (請先閲讀背面之注意事項AlxInyGai-x-yN, among which 0 < ySl and OSxSl. That is, the compound contains, in addition to indium, gallium and / or gallium. In addition to such a basic buffer structure, countless specific examples of the present invention have a buffer structure including a plurality of layers, some or all of which serve as buffer layers. Several specific examples can be divided into multiple categories' The following examples discuss these specific examples;. Right The first specific example: multilayer Figure 5 shows a buffer structure, in which the first buffer layer is directly disposed on the substrate, and the second buffer layer 20 is disposed on the first buffer layer ^. As for the chemical formula shown in Figure 5, both layers are steel-containing gaseous compounds, but the element ratio of the element II is different from that of the two layers. The first-layer 18 is _ not containing 仏 仙. However, the second layer 2Q column 111 is not pure indium, but can be pure inscription or pure gallium. All in all, the second layer 20 contains fewer marriages than the first layer 18. FIG. 6 shows a buffer structure similar to the first one, but the third buffer layer is cut on the second buffer layer 20. In accordance with the chemical formula listed in Figure 6, the buffer layer 18 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs contains some indium, the second buffer layer 20 contains less indium than the first layer 20 and the third buffer layer 22 and less. The specific examples of FIGS. 5 and 6 are believed to belong to the first type of specific examples of the present invention. A first type of example is a multilayer indium-containing buffer layer. Although two- and three-layer buffer structures are shown, additional buffer layers may be used. The common point of such specific examples is that the layers are formulated so that they are used as buffer layers by relaxing the temperature in subsequent manufacturing steps such as the worm crystal growth step. The following other M's Zhang scales are suitable for wealth_ 家 县 (CNS) AW (210 ^ 1 ^ 7 -18- Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 —-------—_ B7_ V. Invention Explanation " — ~ Specific examples include other types of buffer layers in the buffer structure. Specific examples of the second type: cover layer: Figures 7, 8, 9 and 10 Figure 7, 8, 9, and 10 examples The second specific example of the present invention will be described. In these specific examples, the buffer structure includes a cap layer disposed above the buffer layer. The buffer structures in Figs. 7 and 8 are represented by a large class of chemical composition. Figs. 9 and} 〇 Corresponding to the structures in Figures 7 and 8, respectively, but Figures 9 and 10 provide specific examples of devices that are manufactured and used. ~ It is better to provide a cover layer, where the overall manufacturing process includes high-temperature steps such as ia buffering, structure The next step is the growth of insect crystals. The indium-containing buffer layer that has been deposited is relaxed under the same fox. The cover layer is preferably positioned about the indium-containing material (refer to Figures 7 and 8). So the cover layer is more bearable It is made of high-temperature II-V gaseous material in the later manufacturing steps. Gallium nitride (No. 1 and No. 1) is the preferred capping material; bucket 4 is based on daily growth steps. Depending on the temperature, the capping layer may contain indium or other out-of-class elements. Referring now to Figure 7, the first specific example of the type of capping layer is shown. The buffer layer 24 is covered by a rhenium layer 26, and the formulation of the capping layer can be listed as The general formula of the III V nitride used above. The indium-containing buffer layer has any of the chemical formulae listed above. Generally, f, the cap layer 26 contains a smaller amount of material, which is selected to reduce the tendency to relax at a later manufacturing step temperature. However, in the specific example of Fig. 9, a relatively small amount of indium accounts for only 20% of indium, and the difference is that gallium is provided for the buffer layer 24. This thickness is successfully used, but the precise thickness is not particularly limited to the present invention, so it can be Use other thicknesses. The following thickness materials are used to describe the structural properties of this method. This formula is suitable for a state of the article, and its active structure will be manufactured at a high temperature. Therefore, it is suitable for China-(Please read first Note on the back page) fe® -Package. Order-19- Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (Π) The punching layer 24 remains loose even with a moderate amount of indium. Figure 8 shows another capping tool By way of example, two buffer layers 28 and 30 are disposed below the cover layer 32. Again, the buffer layers 28 and 30 and the cover layer 32 are indicated by the general formula of the chemical composition. The first buffer layer 28 (directly above the substrate) High indium content can achieve good relaxation. The second buffer layer 30 contains a mixture of III column elements with less indium content. Again, Figure 10 shows a more specific structure. A pure InN layer 28 is provided for maximum relaxation and stress relief Provides an intermediate layer 30 containing a small amount of indium for better stability at high temperatures, and provides a GaN cap layer 32 to constrain the lower two layers 28 and 30 at high temperatures. The GaN cap layer can tolerate such high temperature manufacturing steps. In the specific case shown, the middle layer 30 is indium gallium nitride, where the indium content is again at most only 20% and provides a good balance between relaxation and structural stability at high temperatures during active structure manufacturing. Figure 11 presents the experimental data of the specific example in Figure 9 in the form of "SIMS depth profile". The initial word SIMS stands for secondary ion mass spectrometry. The number of secondary ions in the SIMS plot is a function of the depth below the device surface. SIMS depth side The profile is a line graph showing the N and In trajectories from the SIMS profile of a single-layer n-type (silicon-doped) GaN layer grown on the nuclei layer as illustrated in Figure 9. InGaN buffer layer and sapphire The depth of the interface of the substrate is about 0.8 microns. The number of ions is provided for the two elements nitrogen and indium. The nitrogen curve is constant in most areas of the line graph. This is reasonable because most of the areas correspond to the nitride layer. The film contains Approximately 50% nitrogen, the substrate is substantially free of nitrogen. Therefore, the number of nitrogen drops sharply at a depth of about 0.8 microns, which is the substrate-film interface. (Please read the precautions on the back first

BB 本頁) .裝· 訂 線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -20- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明(18 ) 線圖係根據對數比例繪圖,故於銦曲線由0.0微米至 約0.7微米深度之峰值僅為雜訊約為0.8微米之銦峰值波幅 之約千分之一。於0.8微米之銦峰對應於緩衝層,指示銦 併入該結構内且保有於其中。 因銦僅於InGaN/GaN缓衝結構之InGaN部分生長期間 於周圍環境生長薄膜,故銦信號指示多層缓衝層存在有 InGaN部分及其所在位置。銦存在於薄膜-基材交界面之 額外確證可由銦信號峰值係位於氮信號下降之相同深度之 事實獲得確證。 於基材-薄膜交界面之銦峰值也指示蓋層(本例為GaN) 可保持InGaN缓衝層定位。 第16圖為凡得波霍爾(Van der Pauw Hall)測量值之表( 標示為’’表II”),亦即器件層之導電特徵相對於半導體器件 操作之測量值。獲得此等結果之器件各自具有類似厚度及 攙雜程度之主動層GaN : Si(亦即攙雜Si之GaN層)於凝核 層上。獲得兩組數值,一組為習知GaN凝核層之數值如第 2圖,另一組為根據本發明之器件如第9圖所示具有 InGaN/GaN層之數值。 值得注意的差異為電子運動性,較佳儘可能高來實現 各層之最高導電係數及最低輸入驅動電流,電子運動性對 本發明之第9圖之InGaN/GaN器件而言比習知生長於GaN 缓衝層上之樣本(第2圖)高約5%。 總電阻率較佳儘可能小對本發明之器件比習知器件更 小。此種優異差異相信來自於應變狀態之有利變化,或來 (請先閱讀背面之注意事項本頁) .裝. 訂 線- --r 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -21 - A7 ____B7 五、發明説明(19) 自於GaN: Si頂層之異位及/或點瑕疵密度下降,且為根據 本發明使用InGaN/GaN複合凝核層所得效果。 第三類具體例:缓衝次級結構:第13、14及15圖 第二類具體例被廣義特徵化為具有一系列緩衝次級結 構。各個次級結構彼此相同或類似。前述具體例之緩衝結 構可用作本類具體例重複之次級結構之例。 第13圖顯示一種緩衝結構包括二次級結構34及36,各 次級結構包括氮化銦緩衝層(38及4〇)及氮化鎵蓋層(42及 44)。換言之若第9圖之蓋層缓衝結構重複兩次,所得結果 為第13圖之結構》 此類具體例中將就緩衝次級結構描述本發明及申請專 利。例如第13圖中’顯示緩衝次級結構34及36為兩種雙層 次級結構。 又於一種次級結構内將各層描述為次級結構層及申請 專利。再度參照第13圖,二層氮化銦緩衝層3 8及4〇被稱作 次級結構緩衝層,及兩層氮化鎵蓋層42及44被稱作次級結 構蓋層。 其次參照第14圖,顯示包括三種次級結構46、48及5〇 之緩衝結構。各該三種次級結構為第9圖該型蓋層次級結 構,包括銦鎵氮化物緩衝層(52、54及56)及氮化鎵蓋層(58 、60及62)。缓衝層顯示為完全相同(亦即厚度及各層之組 成X值一致完全相同),但組成可隨各緩衝層改變。 最後第15圖顯示具有無限次級結構之緩衝結構。顯示 底次級結構64及頂次級結構66。底與頂次級結構64及66間 本·''氏用 ίϊϋ標準(CNS )八4娜·( 210X297公釐 ΐ "~~ - (請先閲讀背面之注意事項 本頁) 裝. 、5Τ 線 經濟部中央標率局員工消費合作社印製 -22- 五、發明説明(20 經 濟 標 準 局 員 合 作 社 印 製 之間隙68表示任何歡數目之料次級結構。 社媒第H、輯構包括兩層次級結構緩紗。次級 結構緩衝層之化學組成俜 茂衝層-人級 列舉。 成係^述含細-V氮化物之通式 各次級結構之次級結構底層(?〇及叫包一 構底層其直接础鄰於基材)含有第 ^級、·。 量係與下標參心值有關。該量可高達^ 之職,亦即該材料為氮化鋼。各 欄』成 結構層(74及76)含有較少量錮。 之第-次級 及y::T化學式對各次級結構底層使用相同-及力參數,但此專配方可隨不同次級結構 構頂層亦為真。 m 其他具體例 由本發明之此等具體例之討論可明瞭多種其他配置 屬可能。例如可使用數種三層式次級結構,各自皆根據 8圖之三層式緩衝結構。又可使用類似第8圖之次級結構 但各種次級結構之緩衝層之化學式可隨化學配方改變 厚度也可改變。 一般而言,具有特定化學組成之—層部分依據其化學 組成而定可作為缓衝層或蓋層。若材料於稍後製造溫度之 南溫下大致維持實心且剛性,則該層可作為蓋層。當然係 假定此層下方為於如此高溫可鬆弛或熔化之材料層特 定層的鬆弛傾向愈高,則其作為緩衝層愈佳。最後高溫之 溫度高度可決;t具有狀組成之-層是否可作為緩 項 it 亦 第 及 本紙張尺度適用中國國家標準(CNS)八4胁(210χ297公幻 -23 - 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明(21 ) 蓋層。 大半例中,缓衝層之生長之開始溫度遠低於對氮化物 膜使用之將缓衝層直接於藍寶石基材上生長之溫度。典型 藍寶石上沉積之缓衝層係於400-900°C沉積,而其餘結構 係於700-1200°C沉積。又複合凝核層加蓋俾便保護對其於 生長過程遞增至更高溫。凝核層總厚度可為業界人士視為 適當之任何值。但較佳厚度為約250-300埃。 製造技術之一般說明 緩衝層及蓋層係於200至1000°C,較佳於400-600°C範 圍之溫度生長。分立各層無需於相同溫度生長。又其他條 件也可改變。例如可改變周圍條件如生長氣氛之麼力。 周圍生長氣氛通常包括周圍氣體,其不具反應性或不 參與層形成過程。此等氣體包括氬氣,氦氣,氫氣,氮氣 ,氫與氮之混合氣體等。周圍氣體及其他可以業界人士已 知方式以多種比例、組合等使用。 最後若待沉積之III欄(及V欄)元素提供於周圍氣氛, 則其比例及數量也可改變,包括攔V對欄III之比。 實驗資料 也對前文顯示及討論之若干緩衝結構之特例生長L E D 器件。由各結構所得LED性能資料示於表111(第16圖)。 光輸出值係以使用先前技術之光電器件如第2圖器件 相對於標準化回合之百分增益提供。於相同時框生長之標 準化回合具有5-7%外部量子效率,及發出485-505 nm波 長範圍之光。因希望產生可輸送最高可能光輸出之LED器 (請先閱讀背面之注意事項 本頁) .裝. 訂 本纸張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) -24- A7 ___B7__ 五、發明説明(22) 件,故使用此處所述本發明之優點明顯。 注意不同具體例可產生約15 nm範圍改變之光波長(比 較可見光譜毗鄰兩色間之波長差約為50 nm)。LED業界人 士瞭解之製造技術可應用於本發明將光波長調整至正確預 定值。 先前研究顯示器件結構存在之應變量可改變結構之主 動區或發光區組成。因主動層組成決定發光波長,故此處 觀察得波長遷移指示結構之應變狀態變化。 各例中’器件之光輸出及效率皆可媲美於相同期間於 GaN凝核層上生長的LED器件之光輸出及光效率或甚至更 高。第9圖所示特例中,調整於凝核層之InGaN部分之InN 莫耳分量也可影響器件性能.β 表IV資料(第π圖)顯示本發明之]lED器件之光輸出比 先前技術器件(〇.〇〇 InN莫耳分量)增高。又產生之光波長 X緩衝層之100埃InGaN部分之.組成變化影響(第9圖)。標 示為”0·00’’該欄指示第2圖之先前技術器件的性能。如同 第16圖所示-寅料,第丨7圖之資料也顯示根據本發明可達成 性能改良及應變狀態變化。 當此層InGaN層厚度改變時可見類似之光輸出及波長 之遷移。如前例測量電力輸送性質,此等結果與藉由使用 本發明之凝核層所帶來之應變狀態或顯微結構的改良有直 接關聯。 -25 - A7 A7 38-40...氮化銦缓衝層 42-4…氮化鎵蓋層 46-50…次級結構 52-6...銦鎵氮化物缓衝層 58-62…氮化鎵蓋層 64.. .底次級結構 66.. .頂次級結構 6 8...間隙 70-6...次級結構層 B7 五、發明説明(23 ) 元件標號對照 2.. .基材 32...蓋層 4.. .凝核結構,缓衝結構 34-6...次級結構 6.. .主動結構 8.. .主動區 10.. .P-型層 12.. .η-型層 14-6...接點 18-22...缓衝層 24.. .缓衝層 26.. .蓋層 28-30...缓衝層 (請先閣讀背面之注意事項再本頁)(BB page). Binding and binding. The paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm). -20- Printed by A7 B7, Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Illustration of the invention (18). The plot is based on a logarithmic scale, so the peak in the depth of the indium curve from 0.0 microns to about 0.7 microns is only about one-thousandth of the peak amplitude of the indium with a noise of about 0.8 microns. The indium peak at 0.8 microns corresponds to the buffer layer, indicating that indium is incorporated into the structure and retained therein. Because indium only grows thin films in the surrounding environment during the growth of the InGaN portion of the InGaN / GaN buffer structure, the indium signal indicates the presence of the InGaN portion and its location in the multilayer buffer layer. Additional confirmation that indium is present at the film-substrate interface can be confirmed by the fact that the peak of the indium signal is located at the same depth as the nitrogen signal. The peak of indium at the substrate-film interface also indicates that the cap layer (GaN in this example) can maintain the positioning of the InGaN buffer layer. Figure 16 is a table of Van der Pauw Hall measurement values (labeled as "Table II"), which is the measured value of the conductive characteristics of the device layer relative to the operation of the semiconductor device. The devices each have an active layer GaN: Si (that is, a doped Si-doped GaN layer) on the nuclei layer of similar thickness and doping degree. Two sets of values are obtained. The other group is the value of the device according to the present invention with an InGaN / GaN layer as shown in Figure 9. The notable difference is the electron mobility, preferably as high as possible to achieve the highest conductivity and lowest input drive current of each layer, Electron mobility is about 5% higher for the InGaN / GaN device of Figure 9 of the present invention than the sample (Figure 2) grown conventionally on a GaN buffer layer. The total resistivity is preferably as small as possible for the device of the present invention Smaller than conventional devices. This excellent difference is believed to be due to favorable changes in the strain state, or come (please read the precautions on the back page first). Binding. --- r This paper size applies Chinese national standards ( CNS) A4 size (210X297 mm)- 21-A7 ____B7 V. Description of the invention (19) Since the ectopic and / or point defect density of the GaN: Si top layer is reduced, and it is the effect obtained by using the InGaN / GaN composite nuclei layer according to the present invention. The third specific example: Cushioning secondary structure: The second type of concrete examples in Figures 13, 14, and 15 are broadly characterized as having a series of buffering secondary structures. Each secondary structure is the same or similar to each other. The buffering structure of the foregoing specific example can be used as An example of a repetitive secondary structure is shown in Figure 13. Figure 13 shows a buffer structure including secondary secondary structures 34 and 36, each of which includes an indium nitride buffer layer (38 and 40) and a gallium nitride cap layer ( 42 and 44). In other words, if the capping buffer structure of FIG. 9 is repeated twice, the result is the structure of FIG. 13 ”Such specific examples will describe the invention and apply for a patent on the buffer secondary structure. In the figure, 'the buffer secondary structures 34 and 36 are shown as two double-layer secondary structures. Each layer is described as a secondary structure layer in a secondary structure and a patent is applied. Referring again to Figure 13, the two-layer indium nitride Buffer layers 38 and 40 are called secondary structure buffer layers And two layers of gallium nitride capping layers 42 and 44 are called secondary structure capping layers. Referring next to FIG. 14, a buffer structure including three secondary structures 46, 48, and 50 is shown. Each of the three secondary structures is the first Figure 9: This type of cover hierarchy includes indium gallium nitride buffer layers (52, 54, and 56) and gallium nitride cover layers (58, 60, and 62). The buffer layers are shown to be exactly the same (i.e. thickness and layers The composition X values are exactly the same), but the composition can be changed with each buffer layer. Finally, Figure 15 shows a buffer structure with an infinite secondary structure. The bottom secondary structure 64 and the top secondary structure 66 are shown. Bottom and top sub-structures 64 and 66. The standard "CNS" 8 4 Na (210X297 mm) " ~~-(Please read the precautions on the back page first). 5T Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs-22- V. Description of the Invention (20 The gap 68 printed by the members of the Economic Standards Bureau of the Cooperatives indicates a secondary structure of any number of materials. Secondary structure slow yarn. The chemical composition of the secondary structure buffer layer-Maoming Chong layer-human-level enumeration. Systematic ^ describes the secondary structure bottom layer (? 〇 and called package) of each secondary structure of the general formula containing fine -V nitride. The bottom layer of a structure is directly adjacent to the base material.) It contains the grade ^. The quantity is related to the subscript center value. The quantity can be as high as ^, that is, the material is nitrided steel. The columns are structured. The layers (74 and 76) contain a smaller amount of 锢. The -secondary and y :: T chemical formulas use the same-and force parameters for the bottom layer of each secondary structure, but this special formula can also be the top layer for different secondary structures. True. M Other Specific Examples From the discussion of these specific examples of the present invention, it will be clear that a variety of other configurations are possible. For example, you can use several three-layer secondary structures, each of which is based on the three-layer buffer structure of Figure 8. You can also use the secondary structure similar to Figure 8 but the chemical formula of the buffer layer of various secondary structures can be formulated with the chemical The thickness can also be changed. Generally speaking, a layer with a specific chemical composition can be used as a buffer layer or a cover layer depending on its chemical composition. If the material is generally solid and rigid at the south temperature of the later manufacturing temperature, This layer can be used as a capping layer. Of course, it is assumed that the specific layer below the layer has a higher relaxation tendency of a material layer that can relax or melt at such a high temperature, and it is better as a buffer layer. The final high temperature temperature can be determined; t has Is it possible to use the -layer as a mitigation item? It is also applicable to the Chinese paper standard (CNS) 8 and 4 (210x297 public fantasy -23-printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Consumer Consumption Cooperative, A7, B7). (21) Cap layer. In most cases, the temperature at which the buffer layer starts to grow is much lower than the temperature at which the buffer layer is grown directly on the sapphire substrate for nitride films. Typical blue The buffer layer deposited on the stone is deposited at 400-900 ° C, and the rest of the structure is deposited at 700-1200 ° C. The composite nuclei layer is capped to protect it from increasing to higher temperatures during the growth process. The nuclei layer The total thickness can be any value deemed appropriate by the industry. However, the preferred thickness is about 250-300 angstroms. General description of manufacturing technology The buffer layer and cover layer are at 200 to 1000 ° C, preferably 400-600 ° C Growth at a range of temperatures. Discrete layers do not need to grow at the same temperature. Other conditions can also be changed. For example, the surrounding conditions can be changed, such as the strength of the growth atmosphere. The surrounding growth atmosphere usually includes the surrounding gas, which is not reactive or participates in the layer formation process . These gases include argon, helium, hydrogen, nitrogen, a mixed gas of hydrogen and nitrogen, and the like. The surrounding gas and others can be used in various proportions, combinations, etc. in a manner known to those skilled in the art. Finally, if the elements of column III (and column V) to be deposited are provided in the surrounding atmosphere, their proportions and quantities can also be changed, including the ratio of column V to column III. The experimental data also grows LED devices for special cases of the buffer structures shown and discussed above. The LED performance data obtained from each structure are shown in Table 111 (Figure 16). The light output value is provided as a percentage gain of a normalized round using a photovoltaic device of the prior art such as the device of FIG. 2. Standardized rounds grown at the same time frame have an external quantum efficiency of 5-7% and emit light in the 485-505 nm wavelength range. I want to produce an LED device that can deliver the highest possible light output (please read the caution page on the back first). Packing. The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm) -24- A7 ___B7__ 5. Description of the invention (22), so the advantages of using the invention described herein are obvious. Note that different specific examples can produce light wavelengths that vary in the range of about 15 nm (compared to the wavelength difference between the adjacent two colors in the visible spectrum of about 50 nm). The manufacturing technology understood by the LED industry can be applied to the present invention to adjust the light wavelength to the correct predetermined value. Previous studies have shown that the presence of strains in the device structure can change the composition of the active or light-emitting area of the structure. Since the composition of the active layer determines the emission wavelength, the change in the strain state of the wavelength migration indicator structure is observed here. The light output and efficiency of the 'devices in each case are comparable to or even higher than the light output and light efficiency of LED devices grown on the GaN nuclei layer during the same period. In the special case shown in Figure 9, the InN Moire component adjusted in the InGaN portion of the nuclei layer can also affect device performance. Β Table IV data (Figure π) shows that the light output of the LED device of the present invention is higher than that of the prior art device (Molar content of 〇〇〇〇N) increased. The wavelength of the light generated by the 100 Angstrom InGaN portion of the X-buffer layer is affected by composition changes (Figure 9). The column labeled "0 · 00" indicates the performance of the prior art device in Fig. 2. As shown in Fig. 16-the material, the data in Fig. 7 also shows that performance improvements and strain state changes can be achieved according to the present invention. When the thickness of this InGaN layer is changed, similar light output and wavelength migration can be seen. As the previous example measures the power transmission properties, these results are related to the state of strain or microstructure brought about by using the core layer of the present invention. The improvement is directly related. -25-A7 A7 38-40 ... Indium nitride buffer layer 42-4 ... Gallium nitride cap layer 46-50 ... Substructure 52-6 ... Indium gallium nitride buffer Layers 58-62 ... gallium nitride capping layer 64 ... bottom secondary structure 66 ... top secondary structure 6 8 ... gap 70-6 ... secondary structure layer B. V. Description of the invention (23) Component number comparison 2. .. substrate 32 ... cover layer 4 .. nuclei structure, buffer structure 34-6 ... secondary structure 6. active structure 8. active area 10 .. .P-type layer 12. .η-type layer 14-6 ... contact 18-22 ... buffer layer 24..buffer layer 26..cap 28-30 ... slow Punch (please read the precautions on the back first and then this page)

訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS )八4規格(210X2.97公釐) -26-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs This paper size is applicable to China National Standards (CNS) 8-4 specifications (210X2.97 mm) -26-

Claims (1)

納2201s A8 B8 C8 D8 經濟部中央檩準局員工消費合作社印製 、申請專利範園 u —種半導體器件,其包含: 一基材(2); 一緩衝結構(4)設置於基材(2)上,緩衝結構包括第 一緩衝層(16)直接設置於基材(2)上,第一缓衝層(16) 係由第一種含銦氮化物化合物製成;及 一主動結構(6)設置於缓衝結構(4)上。 2.如申請專利範圍第1項之半導體器件,其中該第—緩衝 層(16)係由選自如下集合之第一種含銦氮化物化合物 製成: AlJnyGa^yN,其中〇<y$i及 3·如申請專利範圍第1項之半導體器件,其中該緩衝結構 進一步包括一第二缓衝層(20)設置於第一緩衝層(18)上 ,第二緩衝層(20)係由第二含銦氮化物化合物製成。 4.如申請專利範圍第〗項之半導體器件,其中該缓衝結構 進一步包括一蓋層(26),該第二層(26)係由第二種含銦 氮化物化合物設置於第—緩衝層(24)上方製成。 5·如申請專利範圍第4項之半導體器件,其中該蓋層(26) 係由氮化鎵製成。 6. 如申請專利範圍第W之半導體器件,其中該緩衝結構 進—步包括一種第一緩衝層狀次級結構(34)。 7. 如申晴專利範圍第6項之半導體器件,其中·· 第一緩衝層狀次級結構(34)包括由含銦氮化物化 合物製成之次級結構緩衝層(38);及 第一緩衝層係含括於第一缓衝層狀次級結構之次 f紙張尺度適用令國國家標準(CNS )八4祕( I -^1 1 - ..^1 1-1 I —1 - —In I # (請先閲讀背面之注意事項再填寫本頁) 訂 -27Nano 2201s A8 B8 C8 D8 Printed and patented by the Consumers' Cooperative of the Central Government Standards Bureau of the Ministry of Economic Affairs. A semiconductor device comprising: a substrate (2); a buffer structure (4) provided on the substrate (2 ), The buffer structure includes a first buffer layer (16) directly disposed on the substrate (2), the first buffer layer (16) is made of the first indium nitride-containing compound; and an active structure (6 ) Is provided on the buffer structure (4). 2. The semiconductor device as claimed in claim 1, wherein the first buffer layer (16) is made of the first indium nitride compound selected from the group consisting of: AlJnyGa ^ yN, where 0 < y $ i and 3. The semiconductor device according to item 1 of the patent application scope, wherein the buffer structure further includes a second buffer layer (20) disposed on the first buffer layer (18), and the second buffer layer (20) is composed of Made of a second indium nitride-containing compound. 4. The semiconductor device according to the scope of the patent application, wherein the buffer structure further includes a cap layer (26), and the second layer (26) is provided by the second indium nitride-containing compound on the first buffer layer (24) Made from above. 5. The semiconductor device according to item 4 of the application, wherein the capping layer (26) is made of gallium nitride. 6. The semiconductor device according to claim W, wherein the buffer structure further includes a first buffer layered secondary structure (34). 7. A semiconductor device as claimed in item 6 of Shen Qing's patent, wherein the first buffer layered secondary structure (34) includes a secondary structure buffer layer (38) made of an indium nitride-containing compound; and the first The buffer layer is included in the first buffer layered secondary structure of the second f paper scale applicable national national standard (CNS) Eighty-fourth secret (I-^ 1 1-.. ^ 1 1-1 I —1-— In I # (Please read the notes on the back before filling out this page) Order-27 申請專利範圍 級結構緩衝層内部。 8·如申請專利範圍第6 s ^ 體裔件,其中該第一緩衝 層狀次級結構(34)包括: 、及、,。構緩衝層(38)係由含銦氮化物化合物製 成;及 上方 及”。構蓋層(42)係設置於次級結構缓衝層⑽ 9. 如申請專利範圍第8項之半導— 只千导體器件,其中該次級結構盖層(42)係由氮化鎵製成。10. 如申請專利範圍第 肖工午導體件,其中該第一緩衝 層狀次級結構(64)包括: 一第-次級結構緩衝層(7G)係由第—含銦氮化物 化合物製成;及 第二次級結構緩衝層(74)係由第二含銦氮化物化 合物設置於第-次級結構緩衝層(7〇)上方製成。11. 如申請專利範圍第6項之半導體器件,其中該緩衝結構 請 先 閎 讀 背 之 注 意 事 項 再 i 訂 經濟部中央標準局員工消費合作社印製 進-步包括第二缓衝層狀次級結構(36)設置於第 衝層狀次級結構(34)上方。 缓 12_如申請專利範圍第u項之半導體器件,其中該第一及 第二緩衝層狀次級結構各自包括: 一次級結構緩衝層(38、4〇)係由含銦氮化物化合 物製成;及 一-人級結構蓋層(42、44)係設置於含銦氮化物層 上方。 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇χ297公羡) -28- AS B8 C8 '^'~ -—___D8 申請專利範園 ' 一 ' 】3.如申請專利範圍第叫之半導體器件,其中於第一及 第一缓衝層狀次級結構(34、36)之個別次級結構蓋層 (42、44)係由氮化鎵製成。 如申請專利範圍第11項之半導體器件,其中: 該第一缓衝層狀次級結構(64)包括由第一含銦氮 化物化合物製成之第一次級結構缓衝層(7〇);及 第二緩衝層狀次級結構(66)包括由第二含姻氮化 物化合物製成之第二次級結構緩衝層(72)。 15.如申請專利範圍第丨丨項之半導體器件,其中該第一及 第二緩衝層狀次級結構(64、66)各自分別包括: 一第一次級結構缓衝層(74、76)係由第一第一含 銦氮化物化合物製成;及 一第二次級結構緩衝層係由笛 可赝你由第一含銦氮化物化合 物設置於第一次級結構緩衝層上方製成。 (請先閲讀背面之注意事項再本頁) m 填寫本 訂 經濟部中央標準局員工消費合作社印製Patent Application Scope Inside the level structure buffer layer. 8. According to the sixth patent application of the patent application scope, wherein the first buffer layered secondary structure (34) includes:, and ,. The structure buffer layer (38) is made of an indium-containing nitride compound; and above and ". The structure cap layer (42) is provided on the secondary structure buffer layer. Only a thousand-conductor device, in which the secondary structure cap layer (42) is made of gallium nitride. 10. As described in the patent application No. Xiao Gongwu conductor, the first buffer layered secondary structure (64) It includes: a first-secondary structure buffer layer (7G) is made of the first-indium-containing nitride compound; and a second secondary-structure buffer layer (74) is made of the second-indium-nitride-containing compound at the first time Grade structure buffer layer (70) is made on top. 11. For the semiconductor device with the scope of patent application No. 6, among which the buffer structure please read the precautions before reading i printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs The further step includes the second buffer layered secondary structure (36) disposed above the first punched layered secondary structure (34). The two buffer layered secondary structures each include: a primary structure buffer layer (3 8.40) is made of indium-containing nitride compound; and one-human-level structure cover layer (42, 44) is arranged above the indium-containing nitride layer. This paper size applies to Chinese National Standard (CNS) A4 specifications (21〇χ297 public envy) -28- AS B8 C8 '^' ~ -____ D8 Patent Application Park 'One'] 3. As the semiconductor device in the scope of the patent application, which is in the first and the first buffer layer The individual secondary structure cap layers (42, 44) of the shape-like secondary structure (34, 36) are made of gallium nitride. For example, the semiconductor device of the scope of application for item 11 of the patent, wherein: the first buffer layer is shaped like The secondary structure (64) includes a first secondary structure buffer layer (70) made of a first indium nitride-containing compound; and the second buffer layered secondary structure (66) includes a second buffer-containing nitride A second secondary structure buffer layer (72) made of a compound. 15. The semiconductor device according to item 丨 丨 in the patent application scope, wherein the first and second buffer layered secondary structures (64, 66) each include : A first secondary structure buffer layer (74, 76) is made of the first first indium nitride-containing compound; and The second secondary structure buffer layer is made by Dike You. The first indium nitride-containing compound is placed above the first secondary structure buffer layer. (Please read the precautions on the back before this page) m Fill in this order Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 29-29-
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