TW202523142A - Chip packages, operating components and computing devices - Google Patents

Abstract

The embodiment of the present application provides a chip package, a working assembly and a computing device, including: a substrate; a plurality of bare crystal modules, arranged on one side of the substrate, at least some of the plurality of bare crystal modules are interconnected; the plurality of bare crystal modules include at least one memory bare crystal module, and the memory bare crystal module includes a plurality of stacked memory bare crystals and logic processing bare crystals. The technical solution of the embodiment of the present application can achieve ultra-large computing power and ultra-high storage bandwidth by providing a chiplet-based 2.5D/3D packaging solution.

Description

Chip packages, operating components and computing devices

The present application relates to the field of chip packaging technology, and more particularly to a chip package, a working assembly and a computing device.

On the one hand, with the improvement of semiconductor manufacturing technology, transistor density is approaching its limit, which brings about problems such as heat generation, serious power consumption, and nonlinear increase in manufacturing costs. The node improvement of semiconductor manufacturing technology has slowed down and entered the "post-Moore era", and advanced packaging has become an important way to continue Moore's Law.

On the other hand, as the application scenarios of high-performance computing continue to expand, higher requirements are placed on the performance of computing chips. Among related technologies, the memory wall is also a big challenge to traditional computing performance. In-memory computing is a solution proposed to solve the memory wall problem. By reducing the path length between the processor and the memory and increasing the path bandwidth, computing performance is improved. The improvement of chip technology and performance has promoted the demand for advanced packaging and chip modules (chiplets).

The present application embodiment provides a chip package, a working assembly and a computing device to solve or alleviate one or more technical problems in the prior art.

As one aspect of an embodiment of the present application, the embodiment of the present application provides a chip package, comprising: a substrate; a plurality of bare crystal modules, arranged on one side of the substrate, at least some of the plurality of bare crystal modules being interconnected; the plurality of bare crystal modules including at least one memory bare crystal module, the memory bare crystal module including stacked memory bare crystals and logic processing bare crystals.

In one implementation, the logic processing die includes a memory control unit and/or a processor unit.

In one implementation, there are multiple memory dies.

In one implementation, the number of logically processed dies is one or more.

In one implementation, the top die of the memory die module is the memory die, and the bottom die of the memory die module is the logic processing die; or, the top die of the memory die module is the logic processing die, and the bottom die of the memory die module is the memory die.

In one implementation, non-top dies of the memory die module are provided with through silicon vias (TSVs).

In one embodiment, the dies of the memory die module are connected by hybrid bonding or by micro bumps.

In one implementation, the connection between bare die modules includes: connecting through the substrate.

In one implementation, a substrate circuit is embedded in the substrate, and the connection method between the bare die modules includes: connecting to each other through the substrate circuit.

In one embodiment, a bridge die and a redistribution line (RDL) interposer are provided in the substrate, the RDL interposer is arranged on a side of the bridge die facing the die module, and the connection between the die modules includes: connecting to each other through the RDL interposer.

In one implementation, the bridge die is configured as a silicon dielectric.

In one implementation, the bridge die includes a silicon dielectric and a TSV in the silicon dielectric.

In one implementation, the connection between the bare die modules includes: connecting through an interposer, wherein the interposer is disposed between the substrate and the bare die module.

In one implementation, the interposer includes an RDL interposer, and the RDL interposer includes an RDL medium and an RDL wiring layer in the RDL medium.

In one embodiment, the interposer includes a bridge die-in-interposer, and the bridge die-in-interposer includes a filling medium and a bridge die surrounded by the filling medium.

In one implementation, the bridge die interposer further includes an RDL interposer, and the RDL interposer is disposed on a side of the bridge die facing the die module.

In one embodiment, the bridge die is configured as a silicon dielectric; or, the bridge die includes a silicon dielectric and a TSV in the silicon dielectric.

In one embodiment, the bridge die interposer further includes a hole (TIV) in the filling medium for connecting the die module and the substrate.

In one embodiment, the interposer includes a silicon interposer including a silicon dielectric and a TSV disposed in the silicon dielectric.

In one embodiment, the interposer includes a silicon interposer and an RDL interposer located between the silicon interposer and the bare die module, wherein the silicon interposer includes a silicon dielectric and a TSV disposed in the silicon dielectric.

In one embodiment, the interposer further includes an RDL interposer located between the silicon interposer and the substrate.

In one implementation, a plurality of memory die modules are arranged in rows and columns on one side of the substrate.

In one implementation, there are adjacent memory die modules connected to each other among a plurality of memory die modules, wherein the adjacent memory die modules are memory die modules adjacent in a first direction, and/or the adjacent memory die modules are memory die modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

In one implementation, the plurality of bare die modules further include an input/output IO bare die, and the IO bare die is interconnected with at least a portion of the memory bare die modules.

In one implementation, the memory die modules and the IO die are arranged in an array in rows and columns.

In one implementation, the IO die is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction.

In one implementation, there are adjacent memory crystal modules connected to each other among the multiple memory crystal modules, wherein the adjacent memory crystal modules are memory crystal modules adjacent in a first direction, and/or the adjacent memory crystal modules are memory crystal modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

In one implementation, at least one IO die is distributed around each of the memory die modules.

In one implementation, four IO die are distributed around each memory die module, and adjacent IO die are connected to each other in a first direction, where the first direction is a row direction or a column direction.

In one implementation, the plurality of bare die modules further include an IO bare die module, the IO bare die module includes stacked IO bare die and memory bare die, and the IO bare die module is interconnected with at least part of the memory bare die modules.

In one implementation, the top die of the IO die module is the memory die, and the bottom die of the IO die module is the IO die; or, the top die of the IO die module is the IO die, and the bottom die of the IO die module is the memory die.

In one implementation, the memory die modules and the IO die modules are arranged in rows and columns on one side of the substrate.

In one implementation, the IO die module is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction.

In one implementation, there are adjacent memory crystal modules connected to each other among the multiple memory crystal modules, wherein the adjacent memory crystal modules are memory crystal modules adjacent in a first direction, and/or the adjacent memory crystal modules are memory crystal modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located.

In one implementation, at least one IO die module is distributed around each of the memory die modules.

In one implementation, four IO die modules are distributed around each memory die module, and adjacent IO die modules in a first direction are connected to each other, where the first direction is a row direction or a column direction.

In one implementation, adjacent IO die modules are connected to each other.

As one aspect of an embodiment of the present application, the embodiment of the present application provides a working assembly, including a chip package in any embodiment of the present application, and a PCB board, wherein the chip package is arranged on one side of the PCB board.

In one implementation, there are multiple chip packages.

In one embodiment, at least parts of the plurality of chip packages are connected to each other.

In one implementation, a memory device is disposed on one side of the PCB board, and the bare die module in the chip package is interconnected with the memory device via the PCB board.

In one implementation, there are multiple memory devices.

In one implementation, the memory device and the chip package unit are arranged on the same side of the PCB board.

As one aspect of an embodiment of the present application, the embodiment of the present application provides a computing device, including a working component and a power supply module in any implementation method of the embodiment of the present application.

In one implementation, there are multiple working components.

In one embodiment, at least some of the plurality of working components are interconnected.

The technical solution of the embodiment of this application can achieve ultra-large computing power and ultra-high storage bandwidth by providing a chiplet-based 2.5D/3D packaging solution.

The above summary is for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, implementations and features described above, further aspects, implementations and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description.

In the following, only certain exemplary embodiments are briefly described. As can be recognized by those skilled in the art, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative rather than restrictive in nature.

Application Scenarios

As technology develops, chips become more integrated and their performance continues to improve. However, as technology further develops, it becomes increasingly challenging to integrate more functions and components on a single chip, which also increases the cost and complexity of manufacturing.

To overcome these challenges, the concept of chiplet began to emerge in the field of semiconductor manufacturing technology. A chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplets split the entire system into multiple smaller and more focused parts. These chiplets can be designed, manufactured and tested independently, and then combined in a package to form a complete functional system or processing system to achieve higher flexibility, performance optimization and cost reduction design and manufacturing methods. Chiplet is an innovative solution to the complexity and cost challenges faced by the continuous improvement of chip technology and performance.

Under the technical concept of chiplet, 2.5D and 3D packaging solutions are born, such as Chip-on-Wafer-on-Substrate (CoWoS). In an exemplary CoWoS solution, logic die and high-bandwidth memory (HBM) stack are integrated together, usually by arranging multiple HBM stacks around the logic die to provide excellent computing and memory performance. Among them, the Logic die is the core computing unit of the CoWoS packaged chip, which contains a large number of graphics processing units (GPUs) for high-performance computing tasks; the HBM stack adopts 3D stacking technology to stack multiple memory chip components together and communicate through silicon vias (TSV) to provide high-bandwidth and low-latency memory access.

The CoWoS solution allows multiple chips with different functions to be integrated into a single package, providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and bandwidth, the chip packaging area of the CoWoS solution will also be larger, and the power consumption and cost will be higher.

1A and 1B show the architecture of the chip package provided by the embodiment of the present application. As shown in FIG1A and 1B , the chip package includes a substrate 20 and a plurality of bare die modules 10 , and the plurality of bare die modules 10 are arranged on one side of the substrate 20 .

The substrate 20 is used as a packaging substrate, and its material includes an organic substrate, a ceramic substrate, a sapphire substrate, etc. Different applications and requirements may select different types of materials, and the present application embodiment does not limit this.

The connection method between the bare die module 10 and the substrate 20 is not limited in the present application embodiment. For example, the connection method can be through a controlled collapse chip connection bump (Controlled Collapse Chip Connection, referred to as C4 bump or C4 bump) or a connection method using an interposer.

Among them, C4 bumps are made by bumping process, the core process flow is metal deposition, and the most common metal deposition steps include the deposition of under bump metallization (UBM) and the deposition of the bump itself. The deposition of under bump metallization (UBM) is usually achieved by sputtering, electroless plating, plating, etc.; the deposition of the bump itself is usually achieved by electroplating, ball planting, and printing.

Interposers can help components on the upper or lower layers to interconnect electrically and exchange information (such as connecting two bare chips). There are many types of interposers, which can be selected based on actual needs. The following will introduce them through specific examples.

Furthermore, the plurality of bare crystal modules 10 include at least one memory bare crystal module 100. That is, all of the plurality of bare crystal modules 10 may be configured as memory bare crystal modules 100, or some of them may be configured as memory bare crystal modules 100, that is, other types of bare crystal modules may exist in the plurality of bare crystal modules 10. The embodiment of the present application does not limit the number of bare crystal modules 10 and memory bare crystal modules 100.

The memory chip module 100 includes a plurality of stacked memory die 102 and logic processing die 101. In the embodiment of the present application, the number, stacking method, and arrangement position of the memory die 102 and the logic processing die 101 are not limited, and may be 1, 2, 4, 8, 12, 16, 20, 24, etc.

In one example, in the memory die module 100 shown in FIG. 1A , there are multiple memory die 102 , the top die of the memory die module 100 is the logic processing die 101 , and the bottom die of the memory die module 100 is the memory die 102 .

In another example, in the memory die module 100 shown in FIG. 1B , there are multiple memory die 102 , the top die of the memory die module 100 is the memory die 102 , and the bottom die of the memory die module 100 is the logic processing die 101 .

That is to say, the stacking position of the logic processing die 101 can be adjusted according to actual needs, for example, it can also be stacked between the memory die 102.

The memory die 102 may be a chip die of any type of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory, or electrically erasable programmable read-only memory (EEPROM). Exemplarily, the memory die 102 may be a customized chip die or a standardized chip die, which is not limited in the present application embodiment.

The logic processing die 101 may be a chip die responsible for logic processing functions. Exemplarily, the logic processing die 101 may include a memory control unit, may include a processor unit, or may include a memory control unit and a processor unit. The processor unit may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a knowledge processing unit (KPU), a tensor processing unit (TPU), an intelligence processing unit (IPU), a reconfigurable dataflow unit (Reconfigurable Dataflow Unit), a neural network processor (NPU) or any other type of processor (xPU), which is responsible for executing instructions and performing various computing and data processing tasks, including simple arithmetic operations and complex logical operations, thereby realizing functions such as computing, control, and decision-making. The memory control unit is responsible for managing and coordinating part of the memory access, such as converting the memory operations requested by the processor into memory operations and ensuring the correct transmission and storage of data to achieve efficient memory access and data transmission.

It should be noted that in the embodiment of the present application, a chip is a small silicon wafer (or other semiconductor materials) on which multiple electronic components (such as transistors, capacitors, resistors, etc.) and circuit connections are integrated. These components and connections form complex circuits that can perform various functions, thereby realizing tasks such as calculation, storage, control, and signal processing. That is, a chip is a highly integrated electronic device. A die refers to an unpackaged, single chip. In the chip manufacturing process, many identical chips are usually manufactured on a silicon wafer (or other materials). Each chip is called a die, which contains a specific circuit design and function. After manufacturing, the die will be separated and can be further packaged into finished chips or used for other applications.

Furthermore, the method of interconnection (referred to as interconnection) between the memory die 102 and the logic processing die 101 can be configured according to actual needs, and the embodiment of the present application is not limited to this.

In one implementation, the non-top die of the memory die module 100 (which may be the memory die 102 or the logic processing die 101) is provided with TSVs, i.e., vertical vias are formed inside the die to achieve interconnection and communication between chips at different levels. Each TSV is a tiny metal via that passes through the thickness of the die and connects circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and higher performance and more compact packaging solutions.

As an example, the dies of the memory die module 100 (which may be the memory die 102 or the logic processing die 101) are connected by hybrid bonding. Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the two dies, so that the chip dies can be precisely aligned and connected at the micron scale on the wafer. Hybrid bonding generally enables the transmission of electrical signals and data without the use of solder or conductive materials, thereby reducing signal transmission losses in some applications. Because the connection is very close, high-density chip stacking can be achieved through hybrid bonding, thereby realizing more functions in a smaller package size.

As another example, the die of the memory die module 100 (which may be the memory die 102 or the logic processing die 101) are connected via micro bumps. Specifically, a µbump is a tiny protruding structure, usually made of metal material, which forms interconnections and communications between the die. Moreover, this structure is usually manufactured by a microelectronics process, and its size, position, and arrangement can be precisely controlled, thereby achieving high-density connections.

According to the chip package provided in the embodiment of the present application, the bare die module is a packaging component based on the chiplet concept, and a 2.5D/3D packaging solution is provided by packaging multiple bare die modules on one side of the substrate. The memory bare die module can realize the infinite stacking and customized stacking of memory bare die and logic processing bare die, thereby realizing the expansion of storage bandwidth and the improvement of computing power performance. Moreover, compared with the CoWoS solution, the stacking method adopted by the memory bare die module can achieve a shorter interconnection distance and a higher interconnection density, which greatly improves the interconnection efficiency and chip performance.

For example, the chip package provided in the embodiment of the present application can be used for high-performance computing chips, sensor chips, micro-electro-mechanical systems (MEMS), optical communication chips, etc. It should be noted that the above application scenarios or application examples provided in the embodiment of the present application are for the purpose of facilitating understanding, and the embodiment of the present application does not specifically limit the application of the chip package.

The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. The several specific embodiments listed can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

Part I

The following introduces different interconnection methods between bare die modules 10 through Example 1 and Example 2. It should be noted that these interconnection methods can be applied to any type of bare die modules, and a single interconnection method can be used in a chip package, or multiple interconnection methods can be used in a chip package at the same time, and this application embodiment does not limit this.

Embodiment 1

In one interconnection method, the bare die modules 10 may be connected via the substrate 20. FIG. 2A, FIG. 2B and FIG. 2C show the interconnection methods between the bare die modules 10 and between the bare die module 10 and the substrate 20 based on the substrate.

In one example, as shown in FIG. 2A , the bare die module 10 is connected to the substrate 20 via the C4 bump 104, and the bare die modules 10 are connected to each other via the substrate circuit 103 in the substrate 20. In this interconnection method, the substrate circuit 103 is directly embedded in the substrate 20, that is, multiple layers of substrate circuits 103 can be added to realize the interconnection between different components, including communication and power supply. This method has a simple structure and low cost.

The C4 bumps 104 are disposed in the connection area between the substrate 20 and the die module 10, thereby realizing reliable interconnection between the substrate 20 and the die module 10. The C4 bumps can be arranged at a smaller pitch, thereby realizing high-density interconnection between the die modules 10 and between the substrate 20 and the die module 10.

In another example, the bare die modules 10 are interconnected inside the substrate 20. Specifically, a bridge die 201 is disposed in the substrate 20, and an RDL interposer 110 is disposed above the bridge die 201 (on the side facing the bare die module 10), and the RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107, so that the bare die modules 10 are interconnected inside the substrate 20.

There are two implementations in this example: one implementation is shown in FIG. 2B , where the bridge die 201 is configured as a silicon dielectric 205. Each die module 10 can be interconnected through a via 108 in the substrate 20 and an RDL interposer 110 on the bridge die 201, thereby realizing interconnection between the die modules 10. The remaining signals (including signals on the bridge die 201 or other signals on the die module 10) can be connected to the solder balls 109 at the bottom of the substrate 20 through the substrate circuit 103 and the via 108 in the substrate 20.

Another implementation is shown in FIG. 2C , where the bridge die 201 is configured to include a silicon dielectric 205 and TSVs 204 in the silicon dielectric 205. The upper surface of the RDL interposer 110 (the side facing the die module 10) is connected to the C4 bumps 104 via pads, that is, one end of the C4 bumps 104 is connected to the die module 10, and the other end is connected to the upper surface of the RDL interposer 110, thereby realizing interconnection between the die modules 10. At the same time, the side of the bridge die 201 facing away from the die module 10 can be connected to the substrate circuit 103 via the TSVs 204.

Among them, the interconnection method based on bridged bare die can realize high-density interconnection between bare die modules, provide higher performance, functional integration, flexibility and energy efficiency, and make complex 3D packaging systems more feasible and efficient.

Embodiment 2

In this embodiment, the die modules 10 may be connected via an interposer disposed between the substrate 20 and the die modules 10. The interposer may be used to interconnect the die modules 10 on the substrate 20, or may be used to interconnect the substrate 20 and the die modules 10.

The interposer may include a redistribution layer (RDL) interposer, a bridge die interposer or a silicon interposer. It should be noted that each interposer corresponds to an interconnection method, so different interposers are selected, and different interconnection methods are used.

In one interconnection mode, as shown in FIG3A , the interposer may be an RDL interposer 110 , that is, the bare die modules 10 may be connected via the RDL interposer 110 . Specifically, the RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106 .

The RDL medium 106 is usually made of organic materials; the common material of RDL 107 is electroplated copper (Plated Cu) supplemented by a base titanium or copper sputtering layer; the surface of the copper layer is then covered with a corresponding protective layer ink as needed.

Exemplarily, RDL 107 is used to connect the micro bump 105 on the die module 10 and the C4 bump 104 on the other side of the RDL interposer 110, thereby realizing the interconnection between the die module 10 and the substrate 20 and between the die modules 10, and realizing high-density and high-speed signal transmission.

The interconnection method of RDL interposer is suitable for complex interconnection between bare die modules and substrates and between bare die modules. Specifically, compared with substrate interconnection which is limited by the number of substrate layers, the use of RDL interposer allows more layers of interconnection, and the location of RDL interposer is more flexible, so more complex and higher density interconnection can be achieved; and the interconnection method using RDL interposer usually has shorter and more dense interconnection paths, so it may have better performance and lower signal delay.

In one interconnection manner, as shown in FIG. 3B and FIG. 3C , the interposer may be a bridge die interposer 210 , including a filling dielectric 202 and a bridge die 201 surrounded and filled by the filling dielectric 202 .

Exemplarily, the material of the filling medium 202 may be a molding material, an underfill material or other materials used for protecting the filling, including organic materials or inorganic materials, as long as the filling medium 202 can protect the bridge die 201 .

In one example, as shown in FIG. 3B , the bridge die 201 may include a silicon dielectric 205 and a TSV 204 disposed in the silicon dielectric 205 . For example, one surface (such as the upper surface) of the bridge die 201 is disposed between two die modules 10 , and the other surface (such as the lower surface) is connected to the C4 bump 104 through the TSV 204 in the silicon dielectric 205 , and then connected to the substrate 20 through the C4 bump 104 .

Exemplarily, as shown in FIG. 3B , the bridge die interposer 210 may further include an RDL interposer 110 disposed on the bridge die 201 , wherein the RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107 for realizing an interconnection relationship between the connected die modules 10 .

As an optional example, the bridge die 201 is provided with a C4 bump 104 on the side facing the substrate 20, the bridge die 201 is connected to the C4 bump 104 through TSV 204, and then interconnected with the substrate 20 through the C4 bump 104; the die module 10 is provided with a micro bump 105 on the side facing the bridge die interposer 210, and the die module 10 is interconnected on the RDL interposer 110 through the micro bump 105.

In another example, as shown in FIG3C , the bridge die 201 is configured as a silicon dielectric 205. It should be noted that the RDL interposer 110 may be provided on one surface (such as the upper surface) of the bridge die 201 as required, and may be provided between two die modules 10, so that the interconnection relationship between the die modules 10 is realized through the RDL interposer 110 on the upper surface of the bridge die 201, and the other surface (such as the lower surface) of the bridge die 201 may not be connected to the substrate 20.

Further, as an example, as shown in FIGS. 3B and 3C , the bridge die interposer 202 may further include a (Through Interposer Via) TIV 203, which is disposed in the filling medium 202 and connected between the micro bumps 105 and the C4 bumps 104 to realize the interconnection between the die module 10 and the substrate 20. Thus, the interconnection between the die modules 10 can be realized through the bridge die interposer 202, and the remaining signals can be connected to the substrate 20 through the TIV 203.

For example, in an implementation in which the interposer is a bridge die interposer 210, i.e., an implementation as shown in FIGS. 3B and 3C , since the sparseness of the arrangement of the micro bumps 105 may be different from the sparseness of the arrangement of the TIV 203, in order to facilitate interconnection, an interconnection interposer, such as an RDL interposer 110 (not shown in the figure), may be provided between the bridge die interposer 210 and the micro bumps 105.

The interconnection method based on the bridged die interposer can achieve high-density interconnection between die modules and between die modules and substrates, providing higher performance, functional integration, flexibility and energy efficiency, making complex 3D packaging systems more feasible and efficient.

In one implementation, as shown in FIG. 3D , the interposer may be a silicon interposer 310 , which includes a silicon dielectric 205 and a TSV 204 disposed in the silicon dielectric 205 .

Exemplarily, a micro-bump 105 is provided on the side of the bare die module 10 facing the substrate, and an RDL interposer 110 is provided between the micro-bump 105 and the silicon dielectric 205. The RDL interposer 110 includes an RDL dielectric 106 and an RDL wiring layer 107. The micro-bump 105 is interconnected with the TSV 204 through the RDL 110; one end of the TSV 204 is connected to the C4 bump 104 on the substrate 20, and the other end is interconnected with the RDL 110, so that different bare die modules 10 can be interconnected on the RDL interposer 110, and the remaining signals pass through the silicon dielectric 205 and the TSV 204 after passing through the RDL interposer 110, and are connected to the C4 bump 104, and finally connected to the substrate 20.

Here, the side of the silicon interposer 310 facing the substrate 20 may also have an RDL interposer 110, and the RDL interposer 110 includes an RDL dielectric 106 and an RDL wiring layer 107. One end of the RDL interposer 110 is connected to the TSV 204, and the other end is connected to the C4 bump 104, and is connected to the substrate 20 through the C4 bump 104, as shown in FIG. 3E.

The silicon interposer 205 can manufacture complex circuit structures in a very small size and realize high-density interconnection. In addition, due to the good electrical conductivity of silicon and the fast signal transmission rate, the delay of signal transmission is reduced. Furthermore, silicon has stable physical and electrical properties, which can enable the silicon interposer to maintain stable interconnection performance under different working environments.

Part 2

The following describes the interconnection topology of multiple bare die modules 10 on the substrate 20 through the third to fifth embodiments. It should be noted that one interconnection topology can be used alone in a chip package, or multiple interconnection topologies can be used simultaneously in a chip package, and the present application embodiment does not limit this.

As shown in FIG4 , a plurality of bare die modules 10 are arranged in rows and columns on one side of the substrate 20, i.e., the topology is N x M, where N is the number of columns and M is the number of rows, for example: 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc. array forms, n, N and M are all positive integers. In the embodiment of the present application, the first direction is the column direction X or the row direction Y, and the second direction Z is at an angle with the first direction in the plane where the substrate 20 is located, such as an angle of 135 degrees.

Among the plurality of bare die modules, there are adjacent bare die modules that are connected to each other. For example, the bare die modules that need to establish an interconnection relationship are configured as adjacent positions.

Embodiment 3

This embodiment takes the memory die module 100 as an example, and multiple memory die modules 100 are arranged in rows and columns on one side of the substrate 20, for example: 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc. array forms. Among the multiple memory die modules, there are adjacent memory die modules connected to each other, such as memory die modules that need to establish an interconnected relationship are configured as adjacent positions.

In one interconnection topology, as shown in FIG. 5A , the memory die modules connected to each other are memory die modules 100 adjacent to each other in a first direction, where the first direction is a column direction X or a row direction Y.

In one interconnect topology, as shown in FIG5B , the interconnected memory die modules further include memory die modules 100 adjacent to each other in the second direction, and the second direction Z is at an angle to the first direction in the plane where the substrate 20 is located, that is, an interconnection relationship can be formed in the diagonal direction. In this way, interconnections can be added in multiple directions, storage bandwidth can be expanded, and developers can realize high-performance and diversified chip functions.

The technical solution of the embodiment of the present application can expand the interconnection relationship of the memory bare crystal module 100 according to actual needs, thereby achieving the expansion of storage bandwidth and the improvement of computing power performance.

Embodiment 4

In this embodiment, the plurality of bare die modules 10 include an input output (IO) bare die 200 and a memory bare die module 100, as shown in FIG. 6 .

For example, the IO die 200 can be used to process the communication with the memory die module 100 and the outside of the chip package system, including data logging and output, communication protocol processing, etc., and can include interfaces and functions required for interaction with the network, storage, external devices, etc. For example, in a chip package of a computing accelerator card, the memory die module 100 is responsible for computing and storage, while the IO die 200 is responsible for processing input and output operations and communicating with other devices.

Among them, each IO die 200 and each memory die module 100 are arranged in an array in rows and columns on one side of the substrate 20, and the IO die 200 is interconnected with at least part of the memory die modules 100, that is, the IO die 200 forms an interconnection relationship with at least part of the memory die modules 100.

In one embodiment, in the array formed by each memory die module 100 and each IO die 200, the IO die 200 is located at the edge of the array in a first direction, and the first direction is the column direction X or the row direction Y. That is, a plurality of memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, for example: 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc., and the IO die 200 is arranged around the memory die module array. As shown in FIG. 7A , FIG. 7B , FIG. 7C , and FIG. 7D , the memory die module arrays are exemplified in the form of 1x1, 1x2, 2x2, and 3x3 arrays, respectively.

As shown in FIG. 7A , for a 1x1 memory die module array, each memory die module 100 is interconnected with four IO die 200; as shown in FIG. 7B , for a 1x2 memory die module array, each memory die module 100 is interconnected with three IO die 200; as shown in FIG. 7C , for a 2x2 memory die module array, each memory die module 100 is interconnected with two IO die 200. As shown in FIG7D , for a 3×3 memory die module array, each corner memory die module 100 is interconnected with two IO die 200, and the remaining memory die modules 100 on the edge row or edge column except the corners are interconnected with one IO die 200, and the internal memory die modules 100 (except the edge row and edge column) do not need to be interconnected with the IO die 200. The number of IO die 200 is not limited, for example, it can also be 3, 5, etc.

In one embodiment, a plurality of memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, such as 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc. arrays, and the IO die 200 is arranged at the periphery of the memory die module array. As shown in FIG. 7A, FIG. 7B, FIG. 7C and FIG. 7D, the memory die module array is exemplified by arrays of 1x1, 1x2, 2x2, and 3x3, respectively.

It should be noted that the interconnection relationship of the memory die module array can adopt any interconnection topology in the third embodiment. For example, the interconnection relationship of the memory die modules in the diagonal direction can be added to the array form shown in Figures 7C and 7D, as shown in Figures 8A and 8B.

In one implementation, at least one IO die 200 is distributed around each memory die module 100, as shown in FIG. 9 , wherein the number of IO die 200 can be adjusted according to bandwidth requirements, thereby achieving expansion of storage bandwidth and improvement of data transmission performance.

In one implementation, as shown in FIG. 10 , four IO die 200 are distributed around each memory die module 100, wherein adjacent IO die 200 in a first direction are interconnected to establish an interconnection relationship to maximize interconnection bandwidth.

The technical solution of the embodiment of the present application can expand the interconnection relationship between the memory die module 100 and the IO die 200 according to actual needs, which can not only shorten the transmission distance between the memory die module 100 and the IO die 200, but also increase the interconnection density, thereby achieving the expansion of storage bandwidth and the improvement of data transmission performance.

Embodiment 5

In this embodiment, the multiple bare crystal modules 10 include an IO bare crystal module 300 and a memory bare crystal module 100. The IO bare crystal module 300 is interconnected with at least part of the memory bare crystal module 100. The IO bare crystal module 300 includes stacked IO bare crystals 200 and memory bare crystals 102, as shown in Figure 11.

The number, stacking method, and arrangement position of the memory die 102 and the IO die 200 are not limited in the embodiments of the present application. For example, in the IO die module 300 shown in FIG11 , there are multiple memory die 102, the top die of the IO die module 300 is the memory die 102, and the bottom die of the IO die module 300 is the IO die 200. Another example: in the IO die module 300, there are multiple memory die 102, the top die of the IO die module 300 is the IO die 200, and the bottom die of the IO die module 300 is the memory die 102. Therefore, the stacking position of the IO die 200 can be adjusted according to actual needs, for example, it can also be stacked between the memory die 102.

In one implementation, the non-top die of the IO die module 300 (which may be the memory die 102 or the IO die 200) is provided with TSVs, i.e., vertical vias are formed inside the die to achieve interconnection and communication between chips at different levels. Each TSV is a tiny metal via that passes through the thickness of the die and connects circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and higher performance and more compact packaging solutions.

As an example, the dies of the IO die module 300 (which can be the memory die 102 or the IO die 200) are connected by hybrid bonding. Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the two dies, so that the chip dies can be accurately aligned and connected at the micron scale on the wafer. Hybrid bonding can usually achieve the transmission of electrical signals and data without the use of solder or conductive materials, so in some applications, the loss of signal transmission can be reduced. Because the connection is very close, high-density chip stacking can be achieved through hybrid bonding, thereby realizing more functions in a smaller package size.

As another example, the dies of the IO die module 300 (which may be the memory die 102 or the IO die 200) are connected via micro bumps, thereby forming interconnections and communications between the dies, and their size, position, and arrangement can be precisely controlled to achieve high-density connections.

Exemplarily, the IO die 200 can be used to handle communications with the IO die module 300 and with the outside of the IO die module 300 (such as other die modules), including data logging and output, communication protocol processing, etc., and may include interfaces and functions required for interaction with the network, storage, other die modules, etc.

The IO die modules 300 and the memory die modules 100 are arranged in rows and columns on one side of the substrate 20, and the IO die modules 300 are at least interconnected with some of the memory die modules 100, that is, the IO die modules 300 are at least interconnected with some of the memory die modules 100. Furthermore, adjacent IO die modules 300 are interconnected.

In one embodiment, in the array formed by each memory die module 100 and each IO die module 300, the IO die module 300 is located at the edge of the array in a first direction, and the first direction is the column direction X or the row direction Y. That is, a plurality of memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, for example: 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc., and the IO die module 300 is arranged around the memory die module array. As shown in FIG. 12A , FIG. 12B , FIG. 12C , and FIG. 12D , the memory die module arrays are exemplified in the form of 1x1, 1x2, 2x2, and 3x3 arrays, respectively.

As shown in FIG12A, for a 1x1 memory die module array, each memory die module 100 is interconnected with four IO die modules 300; as shown in FIG12B, for a 1x2 memory die module array, each memory die module 100 is interconnected with three IO die modules 300; as shown in FIG12C, for a 2x2 memory die module array, each memory die module 100 is interconnected with two IO die modules 300. 12D , for a 3x3 memory die module array, each corner memory die module 100 is interconnected with two IO die modules 300, and the remaining memory die modules 100 on edge rows or edge columns except the corners are interconnected with one IO die module 300, and the internal memory die modules 100 (except the edge rows and edge columns) do not need to be interconnected with the IO die module 300.

In one embodiment, a plurality of memory die modules 100 are arranged in rows and columns on one side of the substrate 20 to form a memory die module array, such as 2x2, 3x3, 4x4...nxn, etc.; or 1x2, 2x4, 3x6, 4x8...nx2n, etc.; or 1x3, 1x4, 2x5, 3x4, 3x5...nxm, etc. arrays, and the IO die module 300 is arranged at the periphery of the memory die module array. As shown in FIG. 12A, FIG. 12B, FIG. 12C, and FIG. 12D, the memory die module array is exemplified by arrays of 1x1, 1x2, 2x2, and 3x3, respectively.

It should be noted that the interconnection relationship of the memory die module array can adopt any interconnection topology in the third embodiment. For example, the interconnection relationship of the memory die modules in the diagonal direction can be added to the array form shown in Figures 12C and 12D, as shown in Figures 13A and 13B.

In one implementation, at least one IO die module 300 is distributed around each memory die module 100, as shown in FIG. 14 , wherein the number of IO die modules 300 can be adjusted according to bandwidth requirements, thereby achieving expansion of storage bandwidth and improvement of data transmission performance.

In one implementation, as shown in FIG. 15 , four IO die modules 300 are distributed around each memory die module 100, wherein adjacent IO die modules 300 in a first direction are interconnected to establish an interconnection relationship to maximize interconnection bandwidth.

The technical solution of the embodiment of the present application can expand the interconnection relationship between the memory die module 100 and the IO die module 300 according to actual needs, which can not only shorten the transmission distance between the memory die module 100 and the IO die module 300, but also increase the interconnection density, thereby achieving the expansion of storage bandwidth and the improvement of data transmission performance.

Part 3

The following introduces a working assembly including one or more chip packages through Embodiment 6 and Embodiment 7.

Embodiment 6

As shown in FIG. 16 , the embodiment of the present application provides a working assembly, including a printed circuit board (PCB) 30 and a chip package 40 , wherein at least one chip package 40 is arranged on one side of the PCB 30 .

The chip package 40 can be any of the chip packages described in the above application scenarios or embodiments, that is, the chip package 40 includes a substrate 20 and multiple bare die modules 10. It should be noted that the working assembly can include one chip package or multiple chip packages, and the embodiment of the present application does not specifically limit the type, quantity, and interconnection topology of the chip package 40.

Exemplarily, the chip package 40 is connected to the PCB board 30 through the solder balls 109, so that the bare die modules 10 inside different chip packages 40 are interconnected on the PCB board 30.

There may be multiple chip packages 40, and there are interconnected chip packages among the multiple chip packages 40. For example, an interconnection relationship may be established between adjacent chip packages through the PCB board 30, thereby realizing PCB board-level interconnection between the chip packages 40.

In one embodiment, the chip packages 40 are connected to each other on the PCB 30 via connection lines 50. Exemplarily, the connection lines 50 may be any type of interconnection intellectual property (IP) components or modules such as Peripheral Component Interconnect Express (PCIE), Serializer/Deserializer (Serdes), Universal Chiplet Interconnect Express (UCIe), Compute Express Link (CXL), Remote Direct Memory Access (RDMA), Ethernet, etc.

According to the working assembly provided in the embodiment of the present application, the disadvantages of small storage bandwidth and small computing power of the traditional packaging solution can be avoided, and advanced packaging technology is provided to increase the storage bandwidth, thereby improving the chip computing power.

Embodiment 7

As shown in FIG17 , the present application embodiment provides a working assembly, including a PCB board 30, a chip package 60 and a memory device 70. Exemplarily, the memory device 70 and the chip package 60 are arranged on the same side of the PCB board 30.

The chip package 60 includes a substrate 20, a plurality of bare die modules 100 and a plurality of IO bare die 200, and the chip package 60 is interconnected with at least one memory device 70 via a PCB board 30. The embodiment of the present application does not specifically limit the number of chip packages 60 and the interconnection topology.

The chip package 60 can be a chip package of any embodiment in the fourth embodiment, that is, the chip package 60 includes a substrate 20, an IO bare crystal 200 and a memory bare crystal module 100, and the chip package 60 is interconnected with at least one memory device 70 through a PCB board 30.

Exemplarily, the substrate 20 in the chip package 60 is connected to the PCB board 30 through the solder balls 109, thereby connecting the signals on the IO die 200 and the memory die module 100 to the PCB board 30.

There may be multiple chip packages 60, and there are interconnected chip packages among the multiple chip packages 60, such as adjacent chip packages can establish an interconnection relationship on the PCB board 30. In one embodiment, the chip packages 60 are interconnected on the PCB through connecting wires 50, so that the PCB board-level interconnection between the chip packages 60 can be realized.

According to the working components provided in the embodiment of the present application, the expansion of storage capacity and interconnection bandwidth can be further achieved.

The other components of the chip package of the above-mentioned embodiment can adopt various technical solutions known to those skilled in the art now and in the future, and will not be described in detail here.

Part 4

The present application embodiment also provides a computing device, including any one of the working components of the above embodiments and a power supply module, wherein the power supply module is used to provide power to the working component, and the number of the working components can be one or more, which is not limited in the present application embodiment. Exemplarily, at least some of the multiple working components are interconnected, which can be electrically connected or physically connected, which is not limited in the present application embodiment.

For example, the computing device provided by the embodiments of the present application can be used in devices and systems that require a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in fields such as artificial intelligence, deep learning, and big data analysis.

For example, the computing device provided by the embodiment of the present application can be used in various devices that need to monitor and measure physical or chemical changes, such as smart phones, automobiles, industrial automation equipment, medical equipment, and other fields that require high-performance sensor chips to implement.

Illustratively, the computing device provided by the embodiment of the present application can be used in a micro-electromechanical system, such as a gyroscope and accelerometer in a smart phone, an airbag triggering system in a car, a micro lens array in a projector, etc.

Exemplarily, the computing device provided by the embodiment of the present application can be used in optical fiber communication systems, such as optical fiber network equipment, optical interconnection of data centers, long-distance optical fiber transmission systems, and other fields that require high-speed data transmission.

When the computing device is used in different systems or fields, other components of the computing device may be different. Other components of the computing device of the above-mentioned embodiment can be adopted in various technical solutions known to people with ordinary knowledge in this field now and in the future, and will not be described in detail here.

In the technical solution of the embodiment of the present application, the chip package can provide 3D and 2.5D packaging structures, and combined with multi-level interconnection relationships, it can realize wireless expansion and high-density interconnection topology of the bare chip module as a packaging unit.

The first level interconnection can be understood as the infinite stacking of memory die and logic processing die in the memory die module. It can be understood that the vertical stacking of memory die and logic processing die forms a 3D packaging structure, which can achieve a shorter interconnection distance and a higher interconnection density, greatly improving the interconnection efficiency and chip performance, and achieving the expansion of storage bandwidth and the improvement of computing performance. For details, please refer to FIG. 1A, FIG. 1B of the embodiment of this application and the related introduction of the memory die module 100.

The second level interconnection can be understood as the interconnection between bare die modules, which is between the traditional 2D packaging and the complete 3D packaging, and is a 2.5D packaging structure, such as the interconnection between the memory bare die module and the IO bare die, which shortens the transmission distance and increases the interconnection density. For details, please refer to the relevant introduction of the first to fifth embodiments of the present application.

The third level interconnection can be understood as PCB board-level interconnection, such as the connection between IO bare chips through the PCB board, the connection between IO bare chips and memory devices through the PCB board, and the connection between chip packages through the PCB board, thereby further expanding the storage bandwidth and storage capacity to achieve greater performance improvement. For details, please refer to the relevant introduction of the sixth and seventh embodiments of this application.

In the description of this specification, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

In this application, unless otherwise clearly specified and limited, the terms "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be fixed connection, detachable connection, or integration; it can be mechanical connection, electrical connection, or communication; it can be direct connection, or indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components. For those with ordinary knowledge in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

The above disclosure provides many different implementations or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and configurations of specific examples are described above. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and/or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various implementations and/or configurations discussed.

The above is only the specific implementation of this application, but the protection scope of this application is not limited thereto. Any technician familiar with this technical field can easily think of various changes or substitutions within the technical scope disclosed in this application, which should be covered by the protection scope of this application. Therefore, the protection scope of this application should be based on the protection scope of the claim.

10: bare die module 20: substrate 100: memory bare die module 101: logic processing bare die 102: memory bare die 103: substrate circuit 104: C4 bump 105: micro bump 108: hole 110: RDL interposer 106: RDL dielectric 107: RDL wiring layer 210: bridge bare die interposer 201: bridge bare die 202: filling dielectric 203: TIV 310: silicon interposer 204: TSV 205: silicon dielectric 200: IO bare die 300: IO bare die module 30: PCB board 50: connection line 109: Solder ball 40, 60: Chip package 70: Memory device

In the drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

1A and 1B show a structural diagram of a chip package according to an embodiment of the present application;

2A, 2B and 2C show the structure of a chip package according to an embodiment of the application;

3A, 3B, 3C, 3D and 3E show the structure of a chip package according to an embodiment of the present application;

FIG4 shows a topological diagram of a chip package according to an embodiment;

5A and 5B show interconnection topology diagrams of a chip package according to an embodiment;

FIG6 shows a structural diagram of a chip package according to an embodiment of the present application;

7A, 7B, 7C and 7D illustrate interconnection topology diagrams of a chip package according to an embodiment;

8A and 8B show interconnection topology diagrams of a chip package according to an embodiment;

FIG9 shows a structural diagram of a chip package according to an embodiment of the present application;

FIG10 shows an interconnection topology diagram of a chip package according to an embodiment;

FIG. 11 shows a structural diagram of a chip package according to an embodiment of the present application;

12A, 12B, 12C and 12D illustrate interconnection topology diagrams of a chip package according to an embodiment;

13A and 13B show interconnection topology diagrams of a chip package according to an embodiment;

FIG. 14 shows a structural diagram of a chip package according to an embodiment of the present application;

FIG15 shows an interconnection topology diagram of a chip package according to an embodiment;

FIG16 shows a structural diagram of a working assembly according to an embodiment of the present application;

Figure 17 shows a structural diagram of the working components according to the embodiment of the present application.

10: Bare crystal module

20:Substrate

100: Memory bare die module

101: Logical processing of bare wafers

102: Memory bare die

Claims (46)

A chip package comprises: a substrate; and a plurality of bare die modules arranged on one side of the substrate, wherein at least some of the plurality of bare die modules are interconnected; the plurality of bare die modules include at least one memory bare die module, wherein the memory bare die module includes stacked memory bare die and logic processing bare die. A chip package according to claim 1, wherein the logic processing die includes a memory control unit and/or a processor unit. A chip package according to claim 1, wherein the number of the memory bare chips is multiple. A chip package according to claim 1, wherein the number of logic-processed bare chips is one or more. The chip package according to claim 1, wherein the top layer die of the memory die module is the memory die, and the bottom layer die of the memory die module is the logic processing die; or, the top layer die of the memory die module is the logic processing die, and the bottom layer die of the memory die module is the memory die. The chip package according to claim 1, wherein the non-top die of the memory die module is provided with a through silicon via (TSV). The chip package according to claim 1, wherein the bare die of the memory bare die module are connected by hybrid bonding or by micro bumps. According to the chip package described in claim 1, the connection method between bare chip modules includes: connecting through the substrate. According to the chip package described in claim 8, a substrate circuit is embedded in the substrate, and the connection method between the bare chip modules includes: connecting to each other through the substrate circuit. The chip package according to claim 8, wherein a bridge die and a redistribution line (RDL) interposer are provided in the substrate, the RDL interposer is arranged on a side of the bridge die facing the die module, and the connection method between the die modules includes: connecting to each other through the RDL interposer. A chip package according to claim 10, wherein the bridge die is configured as a silicon dielectric. The chip package according to claim 10, wherein the bridge die includes a silicon dielectric and a TSV in the silicon dielectric. According to the chip package described in claim 1, the connection method between the bare die modules includes: connecting through an intermediate layer, and the intermediate layer is arranged between the substrate and the bare die module. The chip package according to claim 13, wherein the interposer comprises an RDL interposer, and the RDL interposer comprises an RDL medium and an RDL wiring layer in the RDL medium. The chip package according to claim 13, wherein the interposer comprises a bridge die-in-interposer, wherein the bridge die-in-interposer comprises a filling medium and a bridge die surrounded by the filling medium. The chip package according to claim 15, wherein the bridge die interposer further comprises an RDL interposer, and the RDL interposer is arranged on a side of the bridge die facing the die module. The chip package according to claim 15, wherein the bridge die is configured as a silicon dielectric; or the bridge die includes a silicon dielectric and a TSV in the silicon dielectric. The chip package according to claim 15, wherein the bridge die interposer further includes a hole (TIV) located in the filling medium for connecting the bare die module and the substrate. The chip package according to claim 15, wherein the interposer comprises a silicon interposer, and the silicon interposer comprises a silicon dielectric and a TSV disposed in the silicon dielectric. The chip package according to claim 13, wherein the interposer includes a silicon interposer and an RDL interposer located between the silicon interposer and the bare die module, the silicon interposer includes a silicon dielectric and a TSV disposed in the silicon dielectric. The chip package according to claim 20, wherein the interposer further includes an RDL interposer located between the silicon interposer and the substrate. According to the chip package described in claim 1, multiple memory die modules are arranged in rows and columns on one side of the substrate. A chip package according to claim 22, wherein there are adjacent memory die modules connected to each other among the plurality of memory die modules, wherein the adjacent memory die modules are memory die modules adjacent in a first direction, and/or the adjacent memory die modules are memory die modules adjacent in a second direction, wherein the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located. The chip package according to claim 1, wherein the plurality of bare die modules further include an input/output IO bare die, and the IO bare die is interconnected with at least part of the memory bare die modules. A chip package according to claim 24, wherein each of the memory die modules and each of the IO die are arranged in an array distributed in rows and columns. A chip package according to claim 25, wherein the IO bare die is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction. A chip package according to claim 25, wherein there are adjacent memory bare crystal modules connected to each other among the multiple memory bare crystal modules, wherein the adjacent memory bare crystal modules are memory bare crystal modules adjacent in a first direction, and/or the adjacent memory bare crystal modules are memory bare crystal modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located. A chip package according to claim 25, wherein at least one IO die is distributed around each of the memory die modules. A chip package according to claim 25, wherein four IO die are distributed around each memory die module, and adjacent IO die are connected to each other in a first direction, wherein the first direction is a row direction or a column direction. The chip package according to claim 1, wherein the multiple bare crystal modules also include an IO bare crystal module, the IO bare crystal module includes stacked IO bare crystals and memory bare crystals, and the IO bare crystal module is interconnected with at least part of the memory bare crystal modules. The chip package according to claim 30, wherein the top layer die of the IO die module is the memory die, and the bottom layer die of the IO die module is the IO die; or, the top layer die of the IO die module is the IO die, and the bottom layer die of the IO die module is the memory die. A chip package according to claim 30, wherein each of the memory die modules and each of the IO die modules are arranged in an array in rows and columns on one side of the substrate. A chip package according to claim 32, wherein the IO bare die module is located at an edge of the array in a first direction, and the first direction is a row direction or a column direction. A chip package according to claim 32, wherein there are adjacent memory bare crystal modules connected to each other among the multiple memory bare crystal modules, wherein the adjacent memory bare crystal modules are memory bare crystal modules adjacent in a first direction, and/or the adjacent memory bare crystal modules are memory bare crystal modules adjacent in a second direction, the first direction is a row direction or a column direction, and the second direction forms an angle with the first direction in the plane where the substrate is located. A chip package according to claim 32, wherein at least one IO die module is distributed around each of the memory die modules. A chip package according to claim 32, wherein four IO die modules are distributed around each memory die module, and adjacent IO die modules in a first direction are connected to each other, and the first direction is a row direction or a column direction. A chip package according to claim 30, wherein adjacent IO bare die modules are connected to each other. A working assembly, comprising: The chip package as described in any one of claim items 1 to 37; and a PCB board, wherein the chip package is arranged on one side of the PCB board. A working assembly according to claim 38, wherein the number of the chip packages is multiple. A working assembly according to claim 39, wherein at least portions of the plurality of chip packages are interconnected. According to the working assembly described in claim 38, a memory device is arranged on one side of the PCB board, and the bare chip module in the chip package is interconnected with the memory device through the PCB board. A working component according to claim 41, wherein the number of the memory devices is multiple. A working assembly according to claim 41, wherein the memory device and the chip package are arranged on the same side of the PCB board. A computing device comprising: The working component described in any one of claim 38 to 43; and a power supply module. A computing device according to claim 44, wherein the number of the working components is multiple. A computing device according to claim 44, wherein at least some of the multiple working components are interconnected.