TW202326735A - Memory device and operation method thereof - Google Patents

Abstract

A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.

Description

Memory device and method of operation thereof

The present invention relates to a memory device with In-Memory-Computing (IMC) and an operating method thereof.

Artificial intelligence (AI) has become a highly effective solution in many fields. The key operation of AI is to perform multiply-and-accumulation (MAC) on a large amount of input data (such as input feature maps) and weight values.

However, with the current AI architecture, it is easy to encounter IO bottleneck and inefficient MAC operation flow.

To achieve high accuracy, MAC operations can be performed with multi-bit inputs and multi-bit weight values. However, the I/O bottleneck becomes more severe and will be less efficient.

In-Memory-Computing (IMC) can be used to accelerate MAC operations, because IMC can reduce the complex arithmetic logic unit (ALU) required under the central processing architecture, and provide MAC in memory High parallelism of operations.

When performing IMC, if the background setting time of the multiplication operation can be accelerated, it will be beneficial to the performance of the IMC.

According to an example of the present case, a method of operating a memory device is proposed, the memory device includes a plurality of memory units, the method of operating the memory device includes: in a first stage, selecting a whole signal line to connect the whole The signal line is pulled up from a first reference voltage to a second reference voltage, and a first string selection line is selected to pull up the first string selection line from the first reference voltage to a third reference voltage. The second string selects the line to maintain the first reference voltage, selects a first word line to pull the first word line from the first reference voltage to a fourth reference voltage, and does not select a second word line to pull up the second word line from the first reference voltage to a fifth reference voltage; sensing in a second phase; maintaining the overall signal line at the The second reference voltage, if the first string selection line is not selected, the first string selection line is pulled down from the third reference voltage to the first reference voltage, and the second string selection line is selected so that the second string selection line Pulling up from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining the unselected second word line at the fifth reference voltage ; and sensing in a fourth stage.

According to another example of the present case, a method for operating a memory device is proposed, the memory device includes a plurality of memory units, the method for operating the memory device includes: in a first stage, selecting an overall signal line to connect the The overall signal line is pulled up from a first reference voltage to a second reference voltage, and a first string selection line is selected to pull up the first string selection line from the first reference voltage to a third reference voltage, and not selected a second string select line to maintain at the first reference voltage, select a first word line to pull the first word line from the first reference voltage to a fourth reference voltage, and deselect a first word line Two word lines to pull up the second word line from the first reference voltage to a fifth reference voltage; sensing in a second phase; maintaining the overall signal line at a third phase The second reference voltage maintains the selected first string selection line at the third reference voltage, maintains the unselected second string selection line at the first reference voltage, does not select the first word line with the The first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected to be pulled down from the fifth reference voltage to the fourth reference voltage. voltage; and sensing in a fourth stage.

According to another example of this case, a memory device is proposed, including: several memory cells; a plurality of overall signal lines; a plurality of bit lines; a plurality of string selection lines; a plurality of word lines, coupled to the memories memory cells, the memory cells are further coupled to the bit lines; a plurality of first switches, coupled to the string selection lines and the bit lines; and a plurality of second switches, coupled to the bit lines These overall signal lines and these bit lines; wherein, in a first stage, select a first overall signal line of these overall signal lines to pull up the first overall signal line from a first reference voltage to A second reference voltage, select the first string selection line of the string selection lines to pull up the first string selection line from the first reference voltage to a third reference voltage, do not select one of the string selection lines a second string selection line to maintain the first reference voltage, select a first word line of the word lines to pull the first word line from the first reference voltage to a fourth reference voltage , and deselecting a second word line of the word lines to pull the second word line from the first reference voltage to a fifth reference voltage; sensing in a second phase; in a In the third stage, the first overall signal line is maintained at the second reference voltage, the first string selection line is not selected and the first string selection line is pulled down from the third reference voltage to the first reference voltage, selecting the second string selection line to pull the second string selection line from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining The unselected second word line is sensed at the fifth reference voltage; and in a fourth phase.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

The technical terms in this specification refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations or definitions of these terms shall prevail. Each embodiment of the disclosure has one or more technical features. On the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 shows a schematic circuit diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 is, for example but not limited to, a three-dimensional (3D) memory device. As shown in FIG. 1, the memory device 100 includes a plurality of memory blocks (memory block) B0~BQ (Q is a positive integer), a page buffer circuit 120, a common source line (common source line) CSL, a plurality of A global source line (global source lines, also called a global signal line) GSL0~GSLQ, a plurality of string select lines (string select line) SSL0~SSLN (N is a positive integer), a plurality of word lines WL0~WLM (M is a positive integer), a plurality of bit lines BL0~BLP (P is a positive integer).

Each of the memory blocks B0 ˜ BQ includes a plurality of switches SW1 , a plurality of switches SW2 and a plurality of memory strings SS. Each memory string SS includes a plurality of memory cells MC. The memory cells MC are located at intersections of the word lines WL0 ˜WLM and the bit lines BL0 ˜BLP. In the same memory block, the memory cells MC coupled to the same bit line form a memory string SS.

The switches SW1 are located at intersections of the string selection lines SSL0 -SSLN and the bit lines BL0 -BLP. When an associated memory string SS is selected, the associated switch SW1 will be turned on.

The switches SW2 are located at intersections of the global source lines GSL0 -GSLQ and the bit lines BL0 -BLP. When a related memory block is selected, the related switch SW2 will be turned on.

The plurality of unit cell currents Id flowing through the memory strings SS will flow to related circuits (such as but not limited to, accumulator circuits) at the back end through the common source line CSL to perform related operations (such as but not limited to, accumulation circuits) Limited by multiplication and accumulation operation (Multiply Accumulate, MAC), data reading, data writing, etc.).

The page buffer circuit 120 includes a plurality of page buffers 121_0˜121_P. Each page buffer 121_0˜121_P is coupled to each bit line BL0˜BLP.

FIG. 2 shows a schematic diagram and a waveform diagram of a memory operation method according to an embodiment of the present invention. In FIG. 2, for the convenience of explanation, the memory cells MC coupled to the same word line (such as WL0) are drawn to clearly show the operation when the string selection line is switched. In addition, when string selection lines are switched, although the second figure switches sequentially (SSL0→SSL1...), it should be understood that this case is not limited to this, and the switching sequence of string selection lines can have other sequences, which is also within the spirit of the case.

In the following, the memory block B0 (global source line GSL0 ), the string selection lines SSL0 , SSL1 , and the word lines WL0 , WL1 are taken as examples for illustration, but it should be understood that this case is not limited thereto. For the convenience of explanation, the data of other memory blocks are originally accessed, but after address decoding, for example, it is found that the next data is stored at the intersection of string selection line SSL0 and word line WL0 in memory block B0 (ie, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).

Then in stage P21, select the overall source line GSL0 to be pulled up from the first reference voltage to the second reference voltage; select the string selection line SSL0 to be pulled up from the first reference voltage to the third reference voltage; do not select (unselect) other strings Select lines SSL1~SSLN to maintain at the first reference voltage; select word line WL0 to be pulled up from the first reference voltage to the fourth reference voltage; do not select other word lines WL1~WLM to be pulled up from the first reference voltage to the fourth reference voltage Five reference voltages (higher than the fourth reference voltage). Thereby, the memory cells MC in the area 150 can be selected (as shown in FIG. 1 and FIG. 2 ).

After that, sensing is performed in phase P22.

Afterwards, after address decoding, for example, it is found that the next piece of data is stored in the memory cell MC at the intersection of the string selection line SSL1 and the word line WL0 in the memory block B0 (that is, the string selection line SSL1 is The selected string selection line, and the word line WL0 is the selected word line). That is, the selected string selection line changes (from string selection line SSL0 to string selection line SSL1 ), but the selected word line does not change (still word line WL0 ).

Then in the phase P23, the selected overall source line GSL0 is maintained at the second reference voltage; the unselected string selection line SSL0 is pulled down from the third reference voltage to the first reference voltage; the other unselected string selection lines SSL2~ SSLN is maintained at the first reference voltage; the selected string selection line SSL1 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; the unselected word lines WL1~WLM are maintained at the fifth reference voltage. Thereby, the memory cells MC in the area 151 (as shown in FIG. 1 and FIG. 2 ) can be selected.

Afterwards, sensing is performed in phase P24.

Similarly, after the address is decoded, in order to access the next piece of data, the selected string selection line should be changed (for example, from the string selection line SSL1 to the string selection line SSL2), but the selected word line remains unchanged. Then in the next stage, the selected global source line GSL0 is maintained at the second reference voltage; the unselected string selection line SSL1 is pulled down from the third reference voltage to the first reference voltage; the other unselected string selection lines SSL0 and SSL3~SSLN are maintained at the first reference voltage; the selected string selection line SSL2 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; other unselected characters are The lines WL1˜WLM are maintained at the fifth reference voltage.

Similarly, after the address is decoded, in order to access the next piece of data, if switching to a different memory block, the operation similar to stage P21 needs to be performed again.

As shown in FIG. 2 , the memory device 100 further includes an accumulation circuit 130 coupled to the page buffer circuit 120 .

The data read from the selected memory cells MC are first input into the page buffer circuit 120, and then sent to the accumulation circuit 130 (the present application is not limited thereto) for MAC operation to obtain the output data.

That is, in the operation method of FIG. 2, after the initialization phase (P21), when reading the data in the same memory block, when it is necessary to switch the string selection line, the level of the overall source line Maintaining the level of the selected word line and the unselected word line, and switching the level of the next selected string selection line and the currently selected string selection line (such as stage P23). This method can shorten the background setup time of the memory device operation (stages P21-P24 can be regarded as the multiplication bit line setup time and word line setup time in the MAC operation).

In addition, in the embodiment of FIG. 2 of the present application, by switching the memory block and the string selection line, compared with the conventional technology, the word line setting time can be reduced, thereby speeding up the operation.

What's more, in the embodiment of Fig. 2 of this case, if the memory device has multiple memory planes (memory plane) and each memory plane has its own accumulation circuit, then the accumulation and output of the MAC operation can be implemented in a pipelined manner conduct.

FIG. 3 shows a schematic diagram and a waveform diagram of a memory operation method according to another embodiment of the present invention. In FIG. 3 , for the convenience of explanation, the memory cells MC coupled to the same string select line (eg SSL0 ) are drawn to clearly show the operation when the word line is switched. In addition, when word line switching is performed, although FIG. 3 switches in order (WL0→WL1...), it should be understood that this case is not limited to this, and the switching order of word lines can have other orders, which is also within the spirit of the case.

In the following, the memory block B0 (global source line GSL0 ), the string selection lines SSL0 , SSL1 , and the word lines WL0 , WL1 are taken as examples for illustration, but it should be understood that this case is not limited thereto. For the convenience of explanation, the data of other memory blocks are originally accessed, but after address decoding, for example, it is found that the next data is stored at the intersection of string selection line SSL0 and word line WL0 in memory block B0 (ie, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).

Then in the stage P31, the overall source line GSL0 is selected to be pulled up from the first reference voltage to the second reference voltage; the string selection line SSL0 is selected to be pulled up from the first reference voltage to the third reference voltage; other strings are not selected. Select the lines SSL1~SSLN to maintain at the first reference voltage; select the word line WL0 to be pulled up from the first reference voltage to the fourth reference voltage; do not select the other word lines WL1~WLM to be pulled up from the first reference voltage to the fourth reference voltage Five reference voltages (higher than the fourth reference voltage). Thereby, the memory cells MC in the area 150 (as shown in FIG. 1 and FIG. 3 ) can be selected.

Afterwards, sensing is performed in phase P32.

Afterwards, after address decoding, for example, it is found that the next data is stored in the memory unit MC at the intersection of the string selection line SSL0 and the word line WL1 in the memory block B0 (that is, the string selection line SSL0 is still is the selected string selection line, and the word line WL1 is the selected word line). That is, the selected string selection line does not change (still string selection line SSL0), but the selected word line changes (from word line WL0 to WL1).

Then in phase P33, the selected global source line GSL0 is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the unselected string selection lines SSL1~SSLN are maintained at the first reference voltage ; The word line WL0 is not selected and pulled up to the fifth reference voltage by the fourth reference voltage; the other unselected word lines WL2~WLM are maintained at the fourth reference voltage; and, the word line WL1 is selected by the fifth reference voltage The reference voltage is pulled down to the fourth reference voltage. Thereby, the memory cells MC in the area 160 can be selected (as shown in FIG. 1 and FIG. 3 ).

Afterwards, sensing is performed in phase P34.

Similarly, after address decoding, in order to access the next data, the selected word line should be changed (for example, from word line WL1 to word line WL2), but the selected string selection line remains unchanged. Then in the next stage, the selected global source line GSL0 is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the unselected string selection lines SSL1~SSLN are maintained at the first reference voltage voltage; the unselected word line WL1 is pulled up from the fourth reference voltage to the fifth reference voltage; other unselected word lines WL0 and WL3~WLM are maintained at the fifth reference voltage; and, the word line WL2 is selected pulled down from the fifth reference voltage to the fourth reference voltage.

The data read from the selected memory cells MC are first input into the page buffer circuit 120, and then sent to the accumulation circuit 130 (the present application is not limited thereto) for MAC operation to obtain the output data.

That is, in the operation method of FIG. 3, after the initialization phase (P31), when reading data in the same memory block, when it is necessary to switch word lines, the level of the overall source line Maintain, maintain the levels of the selected string selection line and the unselected string selection line, and switch the levels of the next selected word line and the currently selected word line (such as stage P33). This method can shorten the background setup time of the memory device operation (stages P31-P34 can be regarded as the multiplication bit line setup time and word line setup time in the MAC operation).

In addition, in the embodiment of FIG. 3 of this application, by switching the memory block, the string selection line and the word line, compared with the conventional technology, the word line setting time can be reduced, thereby speeding up the operation.

What's more, in the embodiment of FIG. 3 of the present application, if the memory device has multiple memory planes and each memory plane has its own accumulation circuit, the accumulation and output of the MAC operation can be performed in a pipelined manner.

In addition, in other possible embodiments of the present application, the operation methods in FIG. 2 and FIG. 3 can be combined arbitrarily, which are all within the spirit of the present application. FIG. 4 and FIG. 5 show the operation method of the memory device according to another embodiment of the present invention.

In FIG. 4, stages P41-P44 are the same or similar to stages P21-P24 in FIG. 2, and stages P45-P46 are the same or similar to stages P33-P34 in FIG. 3, so details thereof are omitted here.

That is, in the 4th figure, carry out the switching of string selection line earlier (selected string selection line is switched to string selection line SSL1 by string selection line SSL0, as stage P43), carry out the switching of character line afterwards (selected word line) The word line is switched from the word line WL0 to the word line WL1, as in stage P45).

In FIG. 5, stages P51-P54 are the same or similar to stages P31-P34 in FIG. 3, and stages P55-P56 are the same or similar to stages P23-P24 in FIG. 2, so details thereof are omitted here.

That is to say, in Fig. 5, first carry out the switching of word line (selected word line is switched from word line WL0 to word line WL1, as stage P53), carry out the switching of string selection line afterwards (selected string The selection line is switched from the string selection line SSL0 to the string selection line SSL1, as in stage P55).

FIG. 6 shows the operation method of the memory device according to another embodiment of the present application. The operation method of the memory device includes: (610) in a first stage, selecting an overall signal line to pull up the entire signal line from a first reference voltage to a second reference voltage, selecting a first string selection line to pull up the first string selection line from the first reference voltage to a third reference voltage, deselect a second string selection line to maintain at the first reference voltage, select a first word line to pull The first word line is pulled up to a fourth reference voltage by the first reference voltage, and a second word line is not selected to be pulled up to a fifth word line by the first reference voltage Reference voltage; (620) sensing in a second stage; (630) maintaining the overall signal line at the second reference voltage in a third stage, not selecting the first string selection line and the first The string selection line is pulled down from the third reference voltage to the first reference voltage, and the second string selection line is selected to pull the second string selection line up from the first reference voltage to the third reference voltage to maintain being selected. Selecting the first wordline at the fourth reference voltage, and maintaining the unselected second wordline at the fifth reference voltage; and (640) sensing in a fourth phase.

FIG. 7 shows an operation method of a memory device according to another embodiment of the present invention. The operation method of the memory device includes: (710) in a first stage, selecting an overall signal line to pull up the entire signal line from a first reference voltage to a second reference voltage, selecting a first string select line to pull up the first string selection line from the first reference voltage to a third reference voltage, unselect a second string selection line to maintain at the first reference voltage, select a first word line to Pulling up the first word line from the first reference voltage to a fourth reference voltage, and unselecting a second word line to pull up the second word line from the first reference voltage to a fourth reference voltage Five reference voltages; (720) sensing in a second stage; (730) in a third stage, maintaining the overall signal line at the second reference voltage, maintaining the selected first string of selection lines at The third reference voltage maintains the unselected second string selection line at the first reference voltage, the first word line is not selected and the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and selecting the second word line to pull down the second word line from the fifth reference voltage to the fourth reference voltage; and (740) sensing in a fourth phase.

As can be seen from the above, in the above-mentioned embodiment of this case, a faster operation speed (such as but not limited to, a faster MAC operation speed, a faster data read/write speed, etc.) can be provided, because before sensing The background setup time can be reduced (eg, the bitline setup time and the wordline setup time in the multiplication MAC operation can be reduced).

The above-mentioned embodiments of this case can be applied to three-dimensional NAND type flash memory, or memory devices sensitive to retention and thermal changes, such as but not limited to, three-dimensional NOR type flash memory, phase change (PCM) type flash memory memory, magnetic random access memory (magnetic RAM) or resistive RAM, etc.

The above embodiments of this case can be applied to different artificial intelligence (AI) models that need to perform multiple MAC operations, such as but not limited to, fully connected layer (fully connection layer), convolution layer (convolution layer), multilayer perceptron (Multilayer) perceptron), support vector machine (support vector machine), etc.

The foregoing embodiments of the present application can be applied to accelerate MAC operations, read operations, write operations, and the like.

The above-mentioned embodiments of this case can be applied to computing usage, and can also be applied to data search, analysis, clustering analysis, and the like.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100: Memory device B0~BQ: Memory block 120: page buffer circuit CSL: common source line GSL0~GSLQ: Global source line SSL0~SSLN: String selection line WL0~WLM: word line BL0~BLP: bit line SW1, SW2: switch SS: memory string 121_0~121_P: page buffer Id: current 150, 151, 160: area 130: accumulation circuit P21~P24, P31~P34, P41~P46, P51~P56: stages 610-640, 710-740: Steps

FIG. 1 shows a schematic circuit diagram of a memory device according to an embodiment of the present invention. FIG. 2 shows a schematic diagram and a waveform diagram of a memory operation method according to an embodiment of the present invention. FIG. 3 shows a schematic diagram and a waveform diagram of a memory operation method according to another embodiment of the present invention. FIG. 4 and FIG. 5 show the operation method of the memory device according to another embodiment of the present invention. FIG. 6 shows the operation method of the memory device according to another embodiment of the present application. FIG. 7 shows an operation method of a memory device according to another embodiment of the present invention.

610-640: Steps

Claims (10)

A method of operating a memory device, the memory device includes a plurality of memory units, the method of operating the memory device includes: In a first phase, select an overall signal line to pull up the overall signal line from a first reference voltage to a second reference voltage, select a first string selection line to pull the first string selection line from the The first reference voltage is pulled up to a third reference voltage, a second string selection line is not selected to maintain the first reference voltage, and a first word line is selected to be switched from the first reference line to the first reference voltage. pulling the voltage up to a fourth reference voltage, and deselecting a second word line to pull up the second word line from the first reference voltage to a fifth reference voltage; sensing in a second stage; In a third stage, maintaining the overall signal line at the second reference voltage, unselecting the first string selection line and pulling down the first string selection line from the third reference voltage to the first reference voltage, selecting the second string selection line to pull the second string selection line from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining the unselected second word line at the fifth reference voltage; and Sensing is performed in a fourth stage. The method for operating a memory device as claimed in claim 1, wherein the memory device further includes a page buffer circuit and an accumulation circuit, The data read out by at least one selected memory unit of the memory units is input into the page buffer circuit and sent to the accumulating circuit for multiply-accumulate operation to obtain output data. The operation method of the memory device as claimed in claim 1, wherein the memory device includes a plurality of memory planes and each of the memory planes includes an accumulation circuit, and the accumulation and output of a multiply-accumulate operation are performed in a pipeline. The operation method of the memory device as described in claim 1, further comprising: In a fifth stage, maintain the overall signal line at the second reference voltage, maintain the selected second string of selection lines at the third reference voltage, and maintain the unselected first string of selection lines at the second reference voltage. A reference voltage, the first word line is not selected so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected to pull the second word line line is pulled down from the fifth reference voltage to the fourth reference voltage; and Sensing is performed in a sixth stage. A method of operating a memory device, the memory device includes a plurality of memory units, the method of operating the memory device includes: In a first phase, select an overall signal line to pull up the overall signal line from a first reference voltage to a second reference voltage, select a first string selection line to pull the first string selection line from the The first reference voltage is pulled up to a third reference voltage, a second string selection line is not selected to maintain the first reference voltage, and a first word line is selected to be switched from the first reference line to the first reference voltage. pulling the voltage up to a fourth reference voltage, and deselecting a second word line to pull up the second word line from the first reference voltage to a fifth reference voltage; sensing in a second stage; In a third stage, maintain the overall signal line at the second reference voltage, maintain the selected first string of selection lines at the third reference voltage, and maintain the unselected second string of selection lines at the second reference voltage. A reference voltage, the first word line is not selected so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected to pull the second word line line is pulled down from the fifth reference voltage to the fourth reference voltage; and Sensing is performed in a fourth stage. The method for operating a memory device as claimed in item 5, wherein the memory device further includes a page buffer circuit and an accumulation circuit, The data read out by at least one selected memory unit of the memory units is input into the page buffer circuit and sent to the accumulating circuit for multiply-accumulate operation to obtain output data. The operation method of the memory device as described in claim 5, wherein the memory device includes a plurality of memory planes and each of the memory planes includes an accumulation circuit, and the accumulation and output of a multiply-accumulate operation are performed in a pipeline. The operation method of the memory device as described in Claim 5, further comprising: In a fifth stage, maintaining the overall signal line at the second reference voltage, unselecting the first string selection line and pulling down the first string selection line from the third reference voltage to the first reference voltage, selecting the second string selection line to pull the second string selection line from the first reference voltage to the third reference voltage, maintaining the selected second word line at the fourth reference voltage, and maintaining the unselected first word line at the fifth reference voltage; and Sensing is performed in a sixth stage. A memory device comprising: a plurality of memory cells; a plurality of integral signal lines; a plurality of bit lines; a plurality of string selection lines; A plurality of word lines are coupled to the memory cells, and the memory cells are further coupled to the bit lines; a plurality of first switches coupled to the string selection lines and the bit lines; and a plurality of second switches coupled to the overall signal lines and the bit lines; in, In a first stage, select one of the overall signal lines to pull up the first overall signal line from a first reference voltage to a second reference voltage, select one of the string selection lines a first string selection line to pull up the first string selection line from the first reference voltage to a third reference voltage, and unselect one of the string selection lines to maintain at the first reference voltage voltage, select the first word line of the word lines to pull up the first word line from the first reference voltage to a fourth reference voltage, and not select the second word line of the word lines word line to pull up the second word line from the first reference voltage to a fifth reference voltage; sensing in a second stage; In a third phase, the first overall signal line is maintained at the second reference voltage, the first string selection line is not selected and the first string selection line is pulled down from the third reference voltage to the first reference voltage voltage, select the second string selection line to pull up the second string selection line from the first reference voltage to the third reference voltage, maintain the selected first word line at the fourth reference voltage, and , maintaining the unselected second word line at the fifth reference voltage; and Sensing is performed in a fourth stage. The memory device as described in Claim 9, wherein, In a fifth stage, maintain the first overall signal line at the second reference voltage, maintain the selected second string selection line at the third reference voltage, and maintain the unselected first string selection line at the The first reference voltage, the first word line is not selected so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected to the second a word line is pulled down from the fifth reference voltage to the fourth reference voltage; and Sensing is performed in a sixth stage.