201216328 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種三族氮化物半導體的製作方法。 【先前技術】 三族氮化物半導體已被廣泛的應用在紫外光和藍綠 光的發光二極體和短波長雷射二極體上，對於高電子流動 元件也是非常重要的材料。二族氣化物半導體通常是一蠢 晶製程形成的薄膜或薄層，其中最常被使用製造方法是氣 相合成法，例如有機金屬化學氣相〉儿積法（metal organic chemical vapor deposition, MOCVD )、_ 素氣相蠢晶法 (hydride vapor-phase epitaxy, HVPE )、分子束蟲晶法 (molecular beam epitaxy，MBE )和金屬有機氯化物 (metal-organic chloride，MOC)等方法。由於缺乏大面積 的三族氮化物半導體作為磊晶基板，所以三族氮化物半導 體層通常以異質遙晶（hetero-epitaxy )生長的方气形成於 不同的蠢晶基板上’例如：藍寶石基板、碳化石夕基板和石夕 基板。因為上述基板和蟲晶層的晶格常數和熱膨^係數不 匹配，使得磊晶層生長時產生許多晶格缺陷（如&以），合 磊晶層作為其他電子元件設置的基板時，這些缺的存: 會影響電子元件的性能’所以如何減少磊晶層的缺陷^度 是非常重要的。由應用的觀點來看，用於生長三族氮化二 半導體層的磊晶基板可能含有一些不好的特質，會嚴重影 響元件的應用或A量製造，例如：低熱傳導係數、不導ζ 201216328 和不易劈裂（cleave )等等。因此在製造過程中，如何將 生長好的三族氮化物半導體或元件從磊晶基板上分離是 报重要的。 在所有三族氮化物半導體材料中，氮化鎵最廣為被應 用於半導體領域。在許多提升氮化鎵層品質的磊晶方法 « 中，遙晶側向成長法（epitaxial lateral overgrowth technique, elog)係最被廣為使用，其係將具有特定晶體方向的條 狀二氧化矽沉積在氮化鎵磊晶表面，然後才進行磊晶製 • 程’以將氮化鎵生長於其上。其中，氮化鎵在二氧化秒上 方區域的晶蹲缺陷密度明顯較低，然而在窗口區（無二氧 化石夕的區域）和氮化鎵接合（coalescent)邊界處的穿晶缺 陷（threading dislocation)仍然很高。低缺陷密度的氮化 鎵面積係由二氧化矽的面積決定，其中條狀二氧化矽的寬 度不能太大，通常只有幾毫米，否則氮化鎵磊晶再生長時 很難完全覆蓋整個上氧化矽的表面。 • 有很多方法可以將磊晶生長後的氮化鎵及藍寶石磊 晶基板分離，包含機械式研磨法、雷射剝離法（由界面分 離）或化學蝕刻法。然而，機械式研磨過程不但費時且為 • 了達到大面積的均—性更需要小心地處理。而雷射剝離法 則為一連續的過程且每次只能剝離一小面積，不僅費時且 而要π貴的雷射設備。至於化學蝕刻法，則因為藍寶石基 板在化學上為相對惰性材料，故無論是濕式或乾式化學蝕 刻皆為一困難且緩慢的過程。 因此，如何提供一種低缺陷密度的三族氮化物半導體 201216328 製造方法，已成為一重要課題。 【發明内容】 有鑑於上述課題，本發明之目的為提供一種三族氮化 物半導體製造方法，藉由再次磊晶生長三族氮化物半導體 層，以得到較低缺陷密度的三族氣化物半導體層。 為達上述目的，依據本發明之一種三族氮化物半導體 製造方法，包含下列步驟：形成一第一圖案化遮罩層於一 磊晶基板，第一圖案化遮罩層具有複數第一開口；磊晶生 長三族氮化物半導體層於磊晶基板之上並覆蓋至少部份 第一圖案化遮罩層；以及姓刻三族氮化物半導體層以形成 複數第二開口，該等第二開口係實質上至少部份對位於該 等第一開口；以及再次磊晶生長三族氮化物半導體層。 在本發明之一實施例中，磊晶基板之材質包含藍寶 石、三族氮化物、碳化矽、矽、砷化鎵、或氧化鋅至少其 中之一。 在本發明之一實施例中，第一圖案化遮罩層之材質包 含氮化梦、氧化破、氧化鈦、氧化叙、氧化給、氧化鎮或 氟化鎂。 在本發明之一實施例中，三族氮化物半導體層之材質 包含氮化鎵、氣化铭、氮化銦、氣化銘鎵、氮化鎵銦、氮 化鋁銦、或氮化銦鎵鋁。 在本發明之一實施例中，更包含形成犧牲層於該等第 一開口中。 6 201216328 在本發明之一實施例中，第一圖案化遮罩層具有複數 第一部分及複數第二部分，各第一部分之尺寸係大於各第 二部分之尺寸。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含移除第一圖案化遮罩層。 Λ 在本發明之一實施例中，形成該等第二開口之步驟， * 係以濕蝕刻或乾蝕刻製程進行。 在本發明之一實施例中，蝕刻三族氮化物半導體層步 • 驟係蝕刻至三族氮化物半導體層與磊晶基板不連接。 在本發明之一實施例中，再次磊晶生長之三族氮化物 半導體層係至少填補部分該等第二開口。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含黏合一轉印基板至再次磊晶生長後之三族氮化物 半導體層。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含形成一犧牲層於複數第一開口，其中犧牲層之材質 • 為三族氮化物，且具有比三族氮化物半導體層小的帶隙能 量。犧牲層之材質為三族氮化物，且具有比三族氮化物半 ' 導體層小的帶隙能量。 • 在本發明之一實施例中，三族氮化物半導體製造方法 更包含移除犧牲層。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含形成一第二圖案化遮罩層於三族氮化物半導體層。 在本發明之一實施例中，第二圖案化遮罩層具有複數 201216328 第三部分及複數第四部分，各第三部分之尺寸係大於各第 四部分之尺寸。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含移除第二圖案化遮罩層。 在本發明之一實施例中，再次磊晶生長之三族氮化物 半導體層係包覆至少部分第二圖案化遮罩層。 在本發明之一實施例中，三族氮化物半導體製造方法 更包含設置一第三圖案化遮罩層於磊晶基板，並位於該等 第一開口中。 承上所述，依據本發明提供之一種三族氮化物半導體 製造方法，藉由第一圖案化遮罩層來作為遮罩，進而控制 三族氮化物半導體層生長在磊晶基板的位置，再配合後續 蝕刻及再次磊晶生長三族氮化物半導體層之步驟，以得到 較低缺陷密度的三族氮化物半導體。 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之三 族氮化物半導體製造方法，其中相同的元件將以相同的參 照符號加以說明。 請參閱圖1，其係為本發明第一實施例之三族氮化物 半導體製造方法之流程示意圖，三族氮化物半導體製造方 法包含下列步驟：形成一第一圖案化遮罩層於一磊晶基 板，第一圖案化遮罩層具有複數第一開口（S10);磊晶生 長一三族氮化物半導體層於磊晶基板之上並覆蓋至少部 201216328 分第一圖案化遮罩層（S30)，蝕刻三族氮化物半導體層以 形成複數第二開口，該等第二開口係實質上至少部分對位 於該等第一開口（S50)以及再次磊晶生長三族氮化物半 導體層（S70)。 本發明之三族氮化物半導體製造方法，係以製造氮化 應 鎵半導體為例’但此方法還可應用於製造其他材質的三族 氮化物半導體，舉例而言像是二元化合物的三族氮化物半 導體，例如：氮化鎵、氮化鋁、氮化銦；三元化合物的三 # 族氮化物半導體，例如：氮化鋁鎵、氮化鎵銦、氮化鋁銦； 以及四元化合物的三族氮化物半導體，例如：氮化銦鎵鋁。 請同時參閱圖1及圖2A，以說明本發明第一實施例之 二方矢氮化物半導體製造方法。於步驟S1 〇中，係利用電毁 輔助化學氣相沉積（plasma enhanced chemicai vapor deposition，PECVD)將遮罩層的材料沉積於磊晶基板12， 再利用黃光製程將形成於磊晶基板12上的遮罩層材料圖 案化’而形成第一圖案化遮罩層11。在此實施例中，第一 籲圖案化遮罩層11的材質可包含氧化矽（包含二氧化矽以 及非結晶的氧化石夕）、氮化；5夕、氧化鈦、氧化鈕、氧化於、 ' 氧化鎂、氟化鎂或非結晶材料，於此係以二氧化矽為例。 . 可作為生長二私氮化物半導體之蠢晶基板12材質包含藍 寶石、三族氮化物、碳化矽、矽、砷化鎵或氧化鋅至♦其 中之一，於此磊晶基板12的材質係以藍寶石基板為例了 而第一圖案化遮罩層11，在磊晶基板12的表面121」·則 具有複數個第一開口 13。其中，該等開口 13並不限制其 9 201216328 肜狀，可為任何設計的圖案，而開口也可為穿孔或凹样。 請同時參閱圖1及圖2B，於步驟S3〇中， 曰曰 1 生長製程，以將三族氮化物半導體層⑷設置於蟲晶= 之一上亚覆k至少部分第-圖案化遮罩^ u。藉由適舍 ==化物半導體層14a的蠢晶生長條件，三族氮: 物半導體層14a可以生長於磊晶其缸10nS(iP> , 基板12曝露出的表面121 :專弟—開口 13中’而不會生長在第一圖案化遮罩層 所覆蓋的接合面⑴。也就是說，第―圖案化遮罩層η 可以作為遮罩（mask)進而控制三族氮化物半導體層⑷ 生長在蟲晶基板12的位置。其中，三族氮化物半^體層 14a係利用有機化學氣相沉積（m〇cvd)法，使三族氮^ 物半導體層i4a覆蓋至少部份第一圖案化遮罩層;;並生長 於弟-開口 中。三族氮化物半導體層…由遙晶基板 12曝露出的表面121開始生長’垂直生長填滿第一開口 η後，即側向生長以覆蓋第一圖案化遮罩豸u，進而形 成一均勻的三族氮化物半導體層14a。 在三族氮化物半導體生長過程中，相較於側向生長的 部分而言’垂直生長的部分有較高的缺陷度。為了移除三 族氮化物半導體層14a高缺陷度的部分，於步驟s5〇中係 私用缺陷選擇性㈣（defectselectiveetching)，而將三族 ^化物半導體層14a浸入可選擇性钱刻的濕钱刻液，例如 含水或液相（liquid phase)化學液氫氧化鉀、硫酸、磷酸、 j酸或其組合。當然’也可以利用乾蝕刻製程選擇性蝕刻 付到第二開口 c。其中，有一特例為高溫（>25〇度）且高 10 201216328 艰度之液相（熔融）氫氧化鉀溶液。請參閱圖2C所示， 由於在二;^氮化物半導體層14a與悬晶基板12之接合面 16附近之缺卩曰饴度較咼，而且穿透差排缺陷（也⑻也吨 dislocation defects).常會垂直延伸至三族氮化物半導體層 14a上表面，故進行選擇性蝕刻製程時，三族氮化物半導 體層14a與接面16之間會形成複數個第二開口 c,該等第 — 二開口 C係實質上至少部分對位於該等第一開口 13,也就 是各第一開口 13之區域中，至少有一第二開口 c，而且位 ❿於第一開口 13中較高缺陷密度之三族氮化物半導體層 14a’係大部分被蝕刻掉，而第一圖案化遮罩層Η以上的 部分為低缺陷密度’則只稍微被蝕刻，故造成三族氮化物 半導體層14a幾乎不與磊晶基板12連接。值得一提的是， 第二開口 C可為穿孔或為凹槽。 請參閱圖2D所示，於步驟S70中，係再次利用有機 化學氣相沉積法，於磊晶基板12再次磊晶生成三族氮.化 物半導體層14b，並藉由調整磊晶製程參數促使磊晶側向 鲁生長填滿由缺陷選擇蝕刻造成的第二開口 C及填平蝕刻表 面，而形成晶圓結構1。值得注意的是，若三族氮化物半 • 導體層14a (圖2B)在第一次磊晶時並沒有完全覆蓋第一 • 圖案化遮罩層11而遺留少許空隙，只要空隙不會太大， 皆可藉由此再次磊晶生長製程來填補。另外，再生後的三 族氮化物半導體層14b下表面（朝向磊晶基板12之表面） 未必為一平坦表面，例如再生三族氮化物半導體層14b應 用作為LED基板時，此不平坦表面有助於光萃取。此外， 201216328 再生的三族氮化物半導體層14 b厚度或形狀係取決於最終 的產品應用’在本發明中並無限制。 本實施例中，三族氮化物半導體層之製造方去更可勺 含：黏合一轉印基板至再次蟲晶生長後之三族氮化物半導 體層（S85)以及移除第一圖案化遮罩層（S9〇)。在移除 第一圖案化遮罩層Π前’由於再生的三族氮化物半導: 層14b之厚度較薄，為了後續製程的操作方便， 2E和圖2F所示，於步驟S85及S90中，可在再生的氮化 鎵層上表面141黏合一轉印基板17’再用濕蝕刻製程將第 一圖案化遮罩層11從磊晶基板12移除，此轉移過程使再 生三族氮化物半導體層14b由轰晶基板12轉移到=印基 板17上，以進行後續製程的操作。本實施例中，轉印^ 板17還可為導熱材料，例如矽或金屬，以幫助元件散熱。 在後續的製程中，可進一步將元件的結構生長於再生 的三族氮化物半導體層14b上’例如：發光二極體之發光 層或雷射二極體（laser diode)。請參閱圖3所示，此為上 述再生的三族氮化物半導體層14b應用於led元件，作為 led基板之示意圖，LED基板上已設置有發光層等結構， ΙΓΐΐί係黏合於一印刷電路板p上。經磊晶製程於再生 人化物半導體層14b生長發光層後，IJED晶粒係接 合到即刷雷 上，即可硌板p，當led晶粒黏合到印刷式電路板P 移除轉印基板17，以進行打線製程。其中，一條 上，另外递、、，。到再生的三族氮化物半導體層14b的接點 條導線26則連結到與LED晶粒電極相連的印 12 201216328 刷=路板P。如上所述，再生三族氮化物半導體層14b的 不平坦表面，反而有助於提升LED晶粒的光萃取效率。 义π同時參閱圖4A、圖4B和圖4C，其中圖4C係為本 t明第二實施例之三族氮化物半導體製造方法之流程示 • 意圖。與第一實施例不同的是，三族氮化物半導體製造方 法更可包含形成一犧牲層於該等第一開口（S4〇)以及移 除犧牲層（S8〇)。於步驟S4〇中，係待第一圖案化遮罩層 11升y成於磊晶基板12後，再形成犧牲層15在該等第一開 • 口 13，當然，也可以是先形成犧牲層15再形成第一圖案 化遮罩層11。接著’再進行生長三族氮化物半導體層14c 於第一圖案化遮罩層1!及犧牲層15上。其中，犧牲層15 之材質可為與二族氮化物半導體層不相$的另一種三族 Γ物材料，於此係以氮化銦鎵為例，以配合後續的能帶 =擇性餘刻製程，其中犧牲層15可具有比三族氮化物半 導體層小的帶隙能量或比三族氮化物半導體層較易餘刻 =性:進行能帶選擇性餘刻製程時，係將晶圓結構& >儿=入錢離子水雜巾，例如氫氧化鉀溶液，並接受光 4_、、射$於光線的光子能量高於犧牲層15的帶隙能量 -但低於氮化鎵層14c的帶隙能量，故於照光過程中，光線 只會被犧牲層15吸收，故於步驟S80中，可經由昭㈣ 犧牲層15’但三族氮化物半導體層W仍被保 +同種類的二族氮化物材料可以是具有不同摻 雜物U〇pant)的三族氮化物 : ^化知（retype doped GaN)’可以錢氣化舒水溶液中， 13 201216328 選擇性地被_移除。相對於切Μ在^基板上之三 =化物何體層㈣，卿有較佳選擇性㈣特性之不 的二族氮化物半導體層，尤其是有較絲刻特性之 導體層做為犧牲層15，有助於增加㈣製程過程之 =握度。在此實施财’作為犧牲層15之氮化銦録可完 、虫」掉，經選擇性餘刻製程後，可得到如圖2D所示 之第一圖案化遮罩層11及三魏化物半導體層14b，l中 T向生長於第—圖案化遮罩層u上之三减化物半導體 層14b有較低的缺陷度。 請參照目5A至圖5F所示，其係本發明第三實施例中 另一種三族氮化物半導體製造方法之結構及流程示意 圖本毛月第一貫把例係揭露另一種選擇性移除位於蟲晶 基板曝露表面上的三族氮化物半導體層。與第一實施例不 同的疋纟發明第二實施例之三族氮化物半導體製造方法 更包含.形成-第二圖案化遮罩層於三族氮化物半導體層 (S45)、移除第二圖案化遮罩層（S55)以及設置一第三 圖案化遮罩層於磊晶基板，並位於該等第一開口中 (S60)。 如圖5A及圖5F所示，於步驟S45巾，係先於蟲晶基 板12上形成第一圖案化遮罩層^並蟲晶生長三族氮化物 半導體層14“麦’才形成第二圖案化遮罩層21。其中，第 二圖案化遮罩層21係與第―圖案化遮罩層π對位設置， 而位於三族氮化物半導體層14d之上表面131。而第二圖 案化遮罩層21係具有複數第二開口 23，該等第二開口 23 14 201216328 也與該等第一開口 13對應設置，而位於該等第一開口 13 之正上方。接著，如圖5B所示，藉由第二圖案化遮罩層 21作為遮罩，三族氮化物半導體層14d於第二開口 23之 曝露部分經步驟S50之選擇性蝕刻至碰到磊晶基板表面 121，且三族氮化物半導體層14d不再與第一圖案化遮罩 • 層11連結，且形成複數開口 13a。於此，蝕刻步驟可例如 ' 為利用感應耦合電漿蝕刻（ICP-RIE)。當然，其他圖案化 的蝕刻方法也可以被利用，例如：使用其他光阻材料當作 φ 感應耦合電漿蝕刻之遮罩。請參照圖5C，於步驟S55中， 係可利用感應耦合電漿進行蝕刻，以移除第二圖案化遮罩 層21。接著，利用另一種有機金屬化學氣相沉積法再次磊 晶生長，以形成圖5E中的三族氮化物半導體層14e。 請參閱圖5D，為了避免再磊晶生長製程中三族氮化物 半導體14e生長於磊晶基板表面121的開口 13a而與磊晶 基板12連結，進而不利於後續的分離步驟，故於步驟S60 中，藉由沉積方式設置一第三圖案化遮罩層11a於磊晶基 • 板12以作為一遮罩，防止圖5E中的三族氮化物半導體層 14e生長於基板表面121。當然，若製程參數控制得宜，使 得三族氮化物半導體14e不會生長於基板表面121，則步 • 驟S60可跳過。如圖5E所示，再次磊晶生長是為了促使 三族氮化物半導體材料側向生長以封閉開口 13a，但不會 在遙晶基板12表面形成三族氮化物半導體，相互接合的 三族氮化物半導體層14e形成一晶圓結構2。由於晶圓結 構2中之第一圖案化遮罩層11不會與磊晶基板12連結， 15 201216328 :後：：t:用广虫刻製程將第-圖案化遮罩層11移 :ΒΟΕ) 字晶圓結構2浸置於氧化物蝕刻缓衝液 ===移除以二氧切為材料的第-圖案化遮罩層 又仵—私氮化物半導體層14e。 前述轉移過程，使再+二 晶基板㈣移到前述的轉^==導體層W Μ 以進行後續製程的操作，亦可 ·口）上 ，請參照圖6Α至圖&其係本發明第四實施例之三族 製作方法的結構與流程示意圖，㈣Β 不^地方二 線之剖面示意圖。與前述第一實施例 Π=’本實施例中，設_基…的 "......層31具有不同尺寸的複數第一部分31a ^复數第二部分3lb’第—部分31a之尺寸較第二== 故側向生長的三族氮化物半導體層2 分3U上接合，而形成一開口或凹槽23;第二部== 尺寸較i &側向生長的三族氮化物半導體層24 ==合。如此-來，藉由具有心 Μ的尺寸或形狀，進而可以得到適當尺寸且不需切=層 族氮化物半導體層24。於圖6(：中，虛線圓圈表示 化物+導體層—24與蟲晶基板22之間的空隙Gp，而開口 凹槽23則表示再攻石曰座具你价妙&、+从 · 24 “錢依心.，、法接合的三族氮化 ^導月豆層24 ’使三族氮化物半導體層24形成複數分 的三族氮化物半導體基板S。故只要適當設計第—圖案化 16 201216328 遮罩層31 ’任何形狀或尺寸的三族氮化物半導體基板s都 可以預先設計。 凊麥照圖7A至圖7F所示，係本發明第五實施例中另 一種三族氮化物半導體層製造方法的結構與流程示意 圖。本貫施例係提供另一種可預先決定三族氮化物半導體 尺寸及形狀的方法，與第一實施例不同的是，於步驟_ 中，第-圖案化遮罩層31係具有不同尺寸的複數第 分31a及複數第二部&训。另夕卜，三族氮化物半導體製 形成-第二圖案化遮罩層於三族氮化物 三族氮化物半導體層34除了在第一部分3u益 合’可側向遙晶於開口 ％並同時接合於第二部分3^ 第一部分3U之尺寸較第二部分训大，故侧向生長的三 減化物半導體層24不會在第— -開口或凹㈣〜-〜較小二Π; 的二族氮化物半導體層34會在第二部分训 -長 ^ ’歸驟W中’形成具有不同尺寸的第 ^ ^ ”於三族氣化物半導體層34。如圖7β所示，J = ^遮罩層％沉積於三族氮化物半導體層34表面 为3U。弟二圖案化遮罩層35具有較大的複數個第： ^及較小的複數個第四部M5b，分別對位^二， 31a和第二部分31b。 了位於弟一部分 請參閱圖7C所示，於步驟㈣中，似 半導體時’第二圖案化遮罩矢虱化物 乍為—遮罩’防止遮 17 201216328 罩層覆蓋處被蝕刻。經蝕刻製程，出現開口 33a在磊晶基 板表面321，且圖案化三族氮化物半導體層：Ma係設置於 第一圖案化遮罩層31和第二圖案化遮罩層35之間。請參 閱圖7D所示，再生的三族氮化物半導體侧向及垂直地包 覆（wrap )部分第二圖案化遮罩層3 5，且形成三族氮化物 半導體層34b於第一圖案化遮罩層31上。由於第二圖案 化遮罩層35之第三部分35a的尺寸係比第四部分35b大， 故三族氮化物半導體層34b係包覆第四部分35b但無法完 全包覆第三部分35a，即三族氮化物半導體層34b僅包覆 # 部分第二圖案化遮罩層35。此外，可於再生三族氮化物半 導體層34b前，利用圖5A至圖5C的步驟（S55)，蝕刻移 除第二圖案化遮罩層35，但本實施例中並未依圖5A至圖 5C之步驟移除第二圖案化遮罩層35。如圖7E所示，為了 分離三族氮化物半導體層34b與磊晶基板32,將三族氮化 物半導體層34b接合至轉印基板37,再利用濕蝕刻製程移 除第一圖案化遮罩層31 ( S90)和第二圖案化遮罩層35中 較大的第三部分35a。如此一來，即可獲得具有部分第二 * 圖案化遮罩層35包覆於其中的三族氮化物半導體層34c。 請參照圖8A至圖81所示，其係本發明第六實施例中 另一種三族氮化物半導體層製造方法的結構與流程示意 圖。與前述第五實施例不同的是，於步驟S10中之磊晶基 板，係具有複數層材料，於此係以氮化鎵基板G及藍寳石 基板421作為一磊晶基板42。另外，三族氮化物半導體製 造方法更可包含：設置一第三圖案化遮罩層於磊晶基板， 18 201216328 並位於該等第一開口中（S60)以及移除第二圖案化遮罩 層（S55)。 請參閱圖8A所示，氮化鎵基板G係設置於藍寶石基 板421表面，第一圖案化遮罩層41係部分沉積於氮化鎵 基板G，並形成複數第一開口 43。其中，氮化鎵基板G可 為遙晶於監寶石基板421上之半導體基板或是獨立的基板 產品。請爹閱圖8B所不’透過蟲晶側向成長法’形成三 族氮化物半導體層44且侧向及垂直地包覆第一圖案化遮 φ 罩層41。請參閱圖8C所示，形成一第二圖案化遮罩層45 於三族氮化物半導體層44a，第二圖案化遮罩層45係對位 於第一圖案化遮罩層41，第二圖案化遮罩層45係用來遮 蔽部分三族氮化物半導體層44a，因此在經過三族氮化物 半導體蝕刻步驟（S50)後，磊晶生長的三族氮化物半導 體層44a不會與原本的氮化鎵基板G連接，甚至部分氮化 鎵基板G會被移除，並於氮化鎵基板G形成開口 43a。如 此一來，三族氮化物半導體層44a則夾置於第一圖案化遮 • 罩層41與第二圖案化遮罩層45之間。 接著，請參閱圖8D所示，於步驟S60中，係形成一 ~ 第三圖案化遮罩層48於磊晶基板並填補開口 43a。接著請 . 參閱圖8E所示，可利用感應耦合電漿進行蝕刻，以移除 第二圖案化遮罩層45。請參閱8F所示，再生三族氮化物 半導體層44b側向及垂直地磊晶形成於第一圖案化遮罩層 41上，其中，第三圖案化遮罩層48可防止再生的三族氮 化物半導體層44b連結到原本的氮化鎵基板G。接著請參 19 201216328 閱圖8G及圖8H所示，將轉印基板47接合至再生的三族 氮化物半導體層44b，再利用濕蝕刻製程將第一圖案化遮 罩層41與第三圖案化遮罩層48移除。其中，接合轉印基 板47之再生三族氮化物半導體層44b比較好進行後續製 程的操作。值得注意的是，步驟S55與步驟S60之前後順 序並非固定，也可先進行S55再進行S60。此外，與三族 氮化物半導體層44b分離之氮化鎵基板G還可以重覆利 用，以降低材料成本。 承上所述，依據本發明提供之一種三族氮化物半導體 · 製造方法，藉由第一圖案化遮罩層作為遮罩，進而控制三 族氮化物半導體層生長在磊晶基板的位置，再配合後續蝕 刻及再次磊晶生長三族氮化物半導體層，以得到較低缺陷 密度的三族氮化物半導體。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1為本發明第一實施例之一種三族氮化物半導體製 造方法的流程圖； 圖2A至圖2F為本發明第一實施例之一種三族氮化物 半導體製造方法的示意圖； 圖3為一再生的三族氮化物半導體層應用於LED基板 的示意圖； 20 201216328 圖4A至圖4C為本發明第二實施例之另一種三族氮化 物半導體製造方法的示意圖與流程圖； 圖5A至圖5F為本發明第三實施例之一種三族氮化物 半導體製造方法的示意圖與流程圖； 圖6A至圖6C為本發明第四實施例之一種三族氮化物 * 半導體製造方法的示意圖與流程圖； ' 圖7A至圖7F為本發明第五實施例之之一種三族氮化 物半導體製造方法的示意圖與流程圖；以及 φ 圖8A至圖81為本發明第六實施例之一種三族氮化物 半導體製造方法的示意圖與流程圖。 【主要元件符號說明】 I、 la、2 :晶圓結構 II、 31、41 :第一圖案化遮罩層 11a、48 :第三圖案化遮罩層 III、 16 :接合面 • 12、22、32、42 :磊晶基板 121、131、141、321 :表面 . 13、33、43 :第一開口 13a、33a、43a :開口 14a ' 14b、14c、14d、14e、24、34、34a、34b、34c、44、 44a、44b :三族氮化物半導體層 15 :犧牲層 17、37、47 :轉印基板 21 201216328 2卜35、45 :第二圖案化遮罩層 23、C :第二開口 2 6 ·導線 31a :第一部份 31b :第二部份. 35a :第三部份 35b :第四部份 421 :藍寶石基板 A-A :剖面線 · G:氮化鎵基板 Gp :空隙 P :電路板 S:三族氮化物半導體基板 S10〜S90 :步驟201216328 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of fabricating a Group III nitride semiconductor. [Prior Art] Group III nitride semiconductors have been widely used in ultraviolet light and blue-green light-emitting diodes and short-wavelength laser diodes, and are also very important materials for high electron flow elements. The Group II vaporized semiconductor is usually a thin film or thin layer formed by a stupid process, and the most commonly used manufacturing method is gas phase synthesis, such as metal organic chemical vapor deposition (MOCVD). _ hydride vapor-phase epitaxy (HVPE), molecular beam epitaxy (MBE) and metal-organic chloride (MOC). Due to the lack of a large-area Group III nitride semiconductor as an epitaxial substrate, the Group III nitride semiconductor layer is usually formed on a different stray substrate by a hetero-epitaxy growth of a square gas, for example: a sapphire substrate, Carbonized stone substrate and Shishi substrate. Because the lattice constant and the thermal expansion coefficient of the above substrate and the insect layer do not match, many crystal lattice defects (such as &) are generated when the epitaxial layer is grown, and the epitaxial layer is used as a substrate for other electronic components. These lack of storage: will affect the performance of electronic components 'however, how to reduce the defects of the epitaxial layer is very important. From the application point of view, the epitaxial substrate used to grow the Group III nitrided semiconductor layer may contain some bad characteristics, which may seriously affect the application of the component or the manufacturing of the A quantity, for example: low thermal conductivity, no conductivity 201216328 And not easy to cleave and so on. Therefore, it is important to separate the grown Group III nitride semiconductor or device from the epitaxial substrate during the manufacturing process. Of all the Group III nitride semiconductor materials, gallium nitride is most widely used in the field of semiconductors. Among the many epitaxial methods for improving the quality of gallium nitride layers, the epitaxial lateral overgrowth technique (elog) is the most widely used method for strip-shaped cerium oxide deposition with specific crystal orientation. On the surface of the gallium nitride epitaxial, the epitaxial process is then performed to grow gallium nitride thereon. Among them, the density of germanium nitride in the region above the second oxidation seconds of GaN is significantly lower, but the threading dislocation at the boundary of the window region (the region without the dioxide dioxide) and the gallescent junction (the threading dislocation) ) is still very high. The low defect density GaN area is determined by the area of cerium oxide, and the width of the strip cerium oxide is not too large, usually only a few millimeters, otherwise it is difficult to completely cover the entire upper oxidization when GaN epitaxial regrowth is long. The surface of the dragonfly. • There are many ways to separate the epitaxially grown gallium nitride and sapphire epitaxial substrates, including mechanical grinding, laser stripping (by interface separation) or chemical etching. However, the mechanical grinding process is not only time-consuming but also requires a careful handling of large areas of uniformity. The laser stripping method is a continuous process and can only strip a small area at a time, which is not only time-consuming but also expensive laser equipment. As for the chemical etching method, since the sapphire substrate is chemically relatively inert, both wet or dry chemical etching is a difficult and slow process. Therefore, how to provide a low defect density group III nitride semiconductor 201216328 manufacturing method has become an important issue. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a method for fabricating a Group III nitride semiconductor by re- epitaxially growing a Group III nitride semiconductor layer to obtain a Group III vaporized semiconductor layer having a lower defect density. . In order to achieve the above object, a method for fabricating a Group III nitride semiconductor according to the present invention comprises the steps of: forming a first patterned mask layer on an epitaxial substrate, the first patterned mask layer having a plurality of first openings; Epitaxially growing a Group III nitride semiconductor layer over the epitaxial substrate and covering at least a portion of the first patterned mask layer; and surname a Group III nitride semiconductor layer to form a plurality of second openings, the second openings Essentially at least partially aligned with the first openings; and epitaxially grown the Group III nitride semiconductor layer. In an embodiment of the invention, the material of the epitaxial substrate comprises at least one of sapphire, group III nitride, tantalum carbide, niobium, gallium arsenide, or zinc oxide. In one embodiment of the invention, the material of the first patterned mask layer comprises nitrided, oxidized, titanium oxide, oxidized, oxidized, oxidized or magnesium fluoride. In an embodiment of the present invention, the material of the group III nitride semiconductor layer comprises gallium nitride, gasification, indium nitride, gasification, gallium indium nitride, aluminum indium nitride, or indium gallium nitride. aluminum. In an embodiment of the invention, the method further includes forming a sacrificial layer in the first openings. 6 201216328 In one embodiment of the invention, the first patterned mask layer has a plurality of first portions and a plurality of second portions, each first portion having a size greater than a size of each of the second portions. In one embodiment of the invention, the method of fabricating a Group III nitride semiconductor further includes removing the first patterned mask layer. In one embodiment of the invention, the step of forming the second openings is performed by a wet or dry etch process. In one embodiment of the invention, the etched Group III nitride semiconductor layer is etched to the group III nitride semiconductor layer without being connected to the epitaxial substrate. In one embodiment of the invention, the re-epitaxially grown Group III nitride semiconductor layer fills at least a portion of the second openings. In one embodiment of the invention, the method of fabricating a Group III nitride semiconductor further comprises bonding a transfer substrate to a Group III nitride semiconductor layer after epitaxial growth. In one embodiment of the present invention, the method of fabricating a Group III nitride semiconductor further includes forming a sacrificial layer in the plurality of first openings, wherein the material of the sacrificial layer is a group III nitride and has a smaller than the group III nitride semiconductor layer Band gap energy. The sacrificial layer is made of a group III nitride and has a smaller band gap energy than the group III nitride half conductor layer. • In an embodiment of the invention, the method of fabricating a Group III nitride semiconductor further comprises removing a sacrificial layer. In one embodiment of the invention, the method of fabricating a Group III nitride semiconductor further includes forming a second patterned mask layer on the Group III nitride semiconductor layer. In one embodiment of the invention, the second patterned mask layer has a plurality of 201216328 third portions and a plurality of fourth portions, each third portion having a size greater than the dimensions of the fourth portion. In an embodiment of the invention, the method of fabricating a Group III nitride semiconductor further comprises removing a second patterned mask layer. In one embodiment of the invention, the re-epitaxially grown Group III nitride semiconductor layer coats at least a portion of the second patterned mask layer. In one embodiment of the present invention, the method of fabricating a Group III nitride semiconductor further includes disposing a third patterned mask layer on the epitaxial substrate and located in the first openings. According to the present invention, a method for fabricating a Group III nitride semiconductor according to the present invention is to use a first patterned mask layer as a mask to control the growth of a Group III nitride semiconductor layer on an epitaxial substrate. The step of subsequent etching and re-epitaxial growth of the Group III nitride semiconductor layer is performed to obtain a Group III nitride semiconductor having a lower defect density. [Embodiment] Hereinafter, a method for manufacturing a Group III nitride semiconductor according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings, wherein like elements will be described with the same reference numerals. 1 is a schematic flow chart of a method for fabricating a Group III nitride semiconductor according to a first embodiment of the present invention. The method for fabricating a Group III nitride semiconductor includes the steps of: forming a first patterned mask layer on an epitaxial layer a substrate, the first patterned mask layer has a plurality of first openings (S10); epitaxially growing a group III nitride semiconductor layer over the epitaxial substrate and covering at least part of the 201216328 minute first patterned mask layer (S30) And etching the group III nitride semiconductor layer to form a plurality of second openings, the second openings being substantially at least partially opposite to the first openings (S50) and the epitaxially grown group III nitride semiconductor layer (S70). The method for fabricating a Group III nitride semiconductor of the present invention is exemplified by the manufacture of a gallium-doped gallium semiconductor. However, the method can also be applied to the fabrication of a Group III nitride semiconductor of other materials, for example, a tri-family of binary compounds. a nitride semiconductor such as gallium nitride, aluminum nitride, or indium nitride; a tri-factor nitride semiconductor such as aluminum gallium nitride, gallium indium nitride, aluminum indium nitride; and a quaternary compound A Group III nitride semiconductor such as indium gallium nitride. Referring to Fig. 1 and Fig. 2A, a method of manufacturing a divalent nitride semiconductor according to a first embodiment of the present invention will be described. In step S1, the material of the mask layer is deposited on the epitaxial substrate 12 by plasma enhanced chemicai vapor deposition (PECVD), and then formed on the epitaxial substrate 12 by a yellow light process. The mask layer material is patterned to form a first patterned mask layer 11. In this embodiment, the material of the first patterning mask layer 11 may include cerium oxide (including cerium oxide and non-crystalline oxidized oxidized stone), nitriding, cerium oxide, titanium oxide, oxidation button, oxidation, 'Magnesium oxide, magnesium fluoride or amorphous material, for example, cerium oxide. The material of the stray substrate 12 which can be used as the growth of the second nitride semiconductor includes one of sapphire, group III nitride, tantalum carbide, tantalum, gallium arsenide or zinc oxide, and the material of the epitaxial substrate 12 is The sapphire substrate is exemplified, and the first patterned mask layer 11 has a plurality of first openings 13 on the surface 121" of the epitaxial substrate 12. Wherein, the openings 13 are not limited to the shape of the 201216328, and may be any designed pattern, and the openings may also be perforations or concaves. Referring to FIG. 1 and FIG. 2B simultaneously, in step S3, the 曰曰1 growth process is performed to set the group III nitride semiconductor layer (4) on the worm crystal = one of the sub-clades k at least partially the first-patterned mask ^ u. The group III semiconductor semiconductor layer 14a can be grown in the epitaxial cylinder 10nS (iP>, the exposed surface 121 of the substrate 12: the younger brother-opening 13 by the doping growth condition of the compound semiconductor layer 14a ' does not grow on the joint surface (1) covered by the first patterned mask layer. That is, the first - patterned mask layer η can serve as a mask to control the growth of the group III nitride semiconductor layer (4). The position of the crystal substrate 12, wherein the group III nitride half layer 14a is covered by the organic chemical vapor deposition (m〇cvd) method, so that the group III nitrogen semiconductor layer i4a covers at least a portion of the first patterned mask And growing in the opening-opening. The group III nitride semiconductor layer...the surface 121 exposed by the remote crystal substrate 12 starts to grow. 'Vertical growth fills the first opening η, that is, laterally grown to cover the first pattern. The mask 豸u is further formed to form a uniform group III nitride semiconductor layer 14a. During the growth of the group III nitride semiconductor, the portion vertically grown has a higher degree of defect than the laterally grown portion. In order to remove the group III nitride semiconductor layer 1 4a high-defective portion, in step s5, is a private selective defect selective (four) (defectiveiveetching), and the tri-battery semiconductor layer 14a is immersed in a selective etching of wet money, such as aqueous or liquid phase ( Liquid phase) chemical liquid potassium hydroxide, sulfuric acid, phosphoric acid, j acid or a combination thereof. Of course, it can also be selectively etched by a dry etching process to the second opening c. Among them, there is a special case of high temperature (>25〇) And high 10 201216328 difficult liquid phase (melting) potassium hydroxide solution. Please refer to FIG. 2C, due to the defect in the vicinity of the bonding surface 16 of the nitride semiconductor layer 14a and the suspension substrate 12 It is relatively sturdy, and the penetration defect (also (8) dislocation defects) often extends vertically to the upper surface of the group III nitride semiconductor layer 14a, so when the selective etching process is performed, the group III nitride semiconductor layer 14a and the junction A plurality of second openings c are formed between the two, and the second openings C are substantially at least partially located in the first openings 13 , that is, in the regions of the first openings 13 , at least one second opening c ,and The majority of the group III nitride semiconductor layer 14a' having a higher defect density in the first opening 13 is mostly etched away, and the portion above the first patterned mask layer having a low defect density is only slightly etched. Therefore, the group III nitride semiconductor layer 14a is hardly connected to the epitaxial substrate 12. It is worth mentioning that the second opening C may be a through hole or a groove. Referring to FIG. 2D, in step S70, the system is again The epitaxial substrate 12 is again epitaxially grown by the organic chemical vapor deposition method to form a group III nitride semiconductor layer 14b, and the epitaxial lateral growth is filled to fill the defect caused by the defect selective etching by adjusting the epitaxial process parameters. The wafer structure 1 is formed by two openings C and filling the etched surface. It is worth noting that if the Group III nitride half conductor layer 14a (Fig. 2B) does not completely cover the first • patterned mask layer 11 during the first epitaxy, leaving a small gap, as long as the gap is not too large , can be filled by this re-epitaxial growth process. In addition, the lower surface of the regenerated group III nitride semiconductor layer 14b (toward the surface of the epitaxial substrate 12) is not necessarily a flat surface. For example, when the regenerative group III nitride semiconductor layer 14b is applied as an LED substrate, the uneven surface is helpful. Extracted by light. Further, the thickness or shape of the regenerated Group III nitride semiconductor layer 14b of 201216328 depends on the final product application', which is not limited in the present invention. In this embodiment, the manufacturing process of the group III nitride semiconductor layer further includes: bonding a transfer substrate to the third-group nitride semiconductor layer after the re-crystal growth (S85), and removing the first patterned mask. Layer (S9〇). Before the removal of the first patterned mask layer ' due to the regenerated III-nitride semiconductor semi-conducting: the thickness of the layer 14b is thin, for the convenience of subsequent processes, 2E and 2F, in steps S85 and S90 The first patterned mask layer 11 can be removed from the epitaxial substrate 12 by a wet etching process on the surface 141 of the regenerated gallium nitride layer, and the transfer process is performed to regenerate the group III nitride. The semiconductor layer 14b is transferred from the crystal platen substrate 12 to the =print substrate 17 for subsequent processing. In this embodiment, the transfer plate 17 may also be a heat conductive material such as tantalum or metal to help the component dissipate heat. In a subsequent process, the structure of the element can be further grown on the regenerated Group III nitride semiconductor layer 14b, e.g., a light-emitting layer of a light-emitting diode or a laser diode. Referring to FIG. 3, the above-mentioned regenerated III-nitride semiconductor layer 14b is applied to a LED device as a schematic diagram of a LED substrate. The LED substrate is provided with a light-emitting layer and the like, and is adhered to a printed circuit board. on. After the epitaxial process is performed on the regenerated humanized semiconductor layer 14b to grow the luminescent layer, the IJED die is bonded to the brush ray, that is, the slab p, when the led die is bonded to the printed circuit board P, the transfer substrate 17 is removed. To carry out the wire-making process. Among them, one on the other, the other, ,,. The contact strip conductor 26 to the regenerated Group III nitride semiconductor layer 14b is bonded to the stamp 12 201216328 brush = road board P connected to the LED die electrode. As described above, the uneven surface of the group III nitride semiconductor layer 14b is regenerated, which in turn contributes to the improvement of the light extraction efficiency of the LED crystal grains. Referring to FIG. 4A, FIG. 4B and FIG. 4C, FIG. 4C is a schematic diagram showing the flow of the method for manufacturing a Group III nitride semiconductor according to the second embodiment of the present invention. Different from the first embodiment, the group III nitride semiconductor manufacturing method may further include forming a sacrificial layer on the first openings (S4〇) and removing the sacrificial layer (S8〇). In step S4, after the first patterned mask layer 11 is raised into the epitaxial substrate 12, the sacrificial layer 15 is formed on the first opening 13, and of course, the sacrificial layer may be formed first. 15 further forms the first patterned mask layer 11. Then, the growth of the group III nitride semiconductor layer 14c is performed on the first patterned mask layer 1 and the sacrificial layer 15. The material of the sacrificial layer 15 may be another tri-group material of the same type as the group II nitride semiconductor layer, and the indium gallium nitride is taken as an example to match the subsequent energy band=selective residual The process, wherein the sacrificial layer 15 may have a smaller band gap energy than the group III nitride semiconductor layer or is more reproducible than the group III nitride semiconductor layer = property: when the band selective selective process is performed, the wafer structure is &> children = money ion water towel, such as potassium hydroxide solution, and receive light 4_,, the photon energy of the light is higher than the band gap energy of the sacrificial layer 15 - but lower than the gallium nitride layer 14c The band gap energy, so that during the illumination process, the light is only absorbed by the sacrificial layer 15, so in step S80, the sacrificial layer 15' can be passed through the Sa(4) but the group III nitride semiconductor layer W is still protected by the same kind of The group nitride material may be a group III nitride having a different dopant U 〇 pant): retype doped GaN may be selectively removed by _ _ _ _ _ _ _ _ _ _ _ _ _ Compared with the three-layered body layer (4) on the substrate, the group has a better selective (four) characteristic of the group of nitride semiconductor layers, especially a conductor layer having a relatively silky characteristic as the sacrificial layer 15, Help to increase (4) the process of the = grip. In this implementation, the "indium nitride as the sacrificial layer 15 can be recorded and wormed off", and after the selective etching process, the first patterned mask layer 11 and the triple-weid semiconductor as shown in FIG. 2D can be obtained. The layer 14b, 1 has a lower degree of defect in the T-deposited semiconductor layer 14b grown on the first patterned mask layer u. Please refer to FIG. 5A to FIG. 5F, which is a schematic diagram showing the structure and flow of another method for manufacturing a Group III nitride semiconductor according to a third embodiment of the present invention. The first example of the first month of the present invention reveals another selective removal. The insect crystal substrate exposes the group III nitride semiconductor layer on the surface. A method for fabricating a Group III nitride semiconductor according to a second embodiment of the present invention, which is different from the first embodiment, further includes: forming a second patterned mask layer on the group III nitride semiconductor layer (S45), removing the second pattern The mask layer (S55) and a third patterned mask layer are disposed on the epitaxial substrate and located in the first openings (S60). As shown in FIG. 5A and FIG. 5F, in step S45, a first patterned mask layer is formed on the surface of the crystal substrate 12, and the crystal growth of the group III nitride semiconductor layer 14 is formed to form a second pattern. The mask layer 21 is formed, wherein the second patterned mask layer 21 is disposed in alignment with the first patterned mask layer π, and is located on the upper surface 131 of the group III nitride semiconductor layer 14d. The cover layer 21 has a plurality of second openings 23, and the second openings 23 14 201216328 are also disposed corresponding to the first openings 13 and directly above the first openings 13. Then, as shown in FIG. 5B, By using the second patterned mask layer 21 as a mask, the exposed portion of the group III nitride semiconductor layer 14d at the second opening 23 is selectively etched through the step S50 to the surface of the epitaxial substrate 121, and the group III nitride The semiconductor layer 14d is no longer connected to the first patterned mask layer 11 and forms a plurality of openings 13a. Here, the etching step can be, for example, "inductively coupled plasma etching (ICP-RIE). Of course, other patterned Etching methods can also be utilized, for example: using other photoresists The material is treated as a φ inductively coupled plasma etched mask. Referring to Figure 5C, in step S55, etching can be performed using an inductively coupled plasma to remove the second patterned mask layer 21. Next, another The organometallic chemical vapor deposition method is again epitaxially grown to form the group III nitride semiconductor layer 14e in FIG. 5E. Referring to FIG. 5D, the group III nitride semiconductor 14e is grown on the epitaxial substrate in order to avoid the re-elevation growth process. The opening 13a of the surface 121 is coupled to the epitaxial substrate 12, which is disadvantageous for the subsequent separation step. Therefore, in step S60, a third patterned mask layer 11a is disposed on the epitaxial substrate 12 by deposition. A mask prevents the group III nitride semiconductor layer 14e in FIG. 5E from growing on the substrate surface 121. Of course, if the process parameters are properly controlled so that the group III nitride semiconductor 14e does not grow on the substrate surface 121, step S60 It can be skipped. As shown in FIG. 5E, the epitaxial growth again is to promote the lateral growth of the group III nitride semiconductor material to close the opening 13a, but does not form a group III nitride half on the surface of the remote substrate 12. The conductor, the inter-bonded group III nitride semiconductor layer 14e forms a wafer structure 2. Since the first patterned mask layer 11 in the wafer structure 2 is not connected to the epitaxial substrate 12, 15 201216328: after::t : The first patterned mask layer 11 is moved by a wide-grain engraving process: ΒΟΕ) The word wafer structure 2 is immersed in an oxide etch buffer === removing the first-patterned mask using dioxotomy as a material The layer is further 仵-private nitride semiconductor layer 14e. In the above transfer process, the re+2 crystal substrate (4) is moved to the above-mentioned turn===conductor layer W Μ for subsequent processing, or port), please refer to FIG. 6A to FIG. 3 are schematic diagrams showing the structure and flow of a three-family manufacturing method according to a fourth embodiment of the present invention, and (4) a schematic cross-sectional view of a second line. With the foregoing first embodiment Π=' in the present embodiment, the layer 31 of the _base... has a plurality of first portions 31a of different sizes, the size of the second portion 3lb'-the portion 31a Compared with the second ==, the laterally grown group III nitride semiconductor layer 2 is bonded to 3U to form an opening or recess 23; the second portion == the size of the i & laterally grown group III nitride semiconductor Layer 24 == combined. In this way, by having a size or shape of a heart, it is possible to obtain an appropriate size without cutting the layer nitride semiconductor layer 24. In Fig. 6 (:, the dotted circle indicates the gap Gp between the compound + conductor layer - 24 and the insect crystal substrate 22, and the opening groove 23 indicates that the stone is a good point, and the + from the 24 "Qian Yixin., the method of bonding the three groups of nitrided moon-leaf layer 24' causes the group III nitride semiconductor layer 24 to form a plurality of groups of nitride semiconductor substrates S. Therefore, as long as the appropriate design of the first pattern 16 201216328 Mask layer 31 'The group III nitride semiconductor substrate s of any shape or size can be pre-designed. The buckwheat is another group III nitride semiconductor layer in the fifth embodiment of the present invention as shown in FIGS. 7A to 7F. A schematic diagram of the structure and flow of the manufacturing method. The present embodiment provides another method for predetermining the size and shape of the Group III nitride semiconductor. Unlike the first embodiment, in the step _, the first patterned mask The layer 31 has a plurality of different dimensions 31a and a plurality of second portions & a further, a group III nitride semiconductor formed - a second patterned mask layer in the group III nitride group III nitride semiconductor layer 34 except in the first part 3u The size of the remote crystal in the opening % and simultaneously bonded to the second portion 3^ the first portion 3U is larger than that of the second portion, so that the laterally grown triple-deposited semiconductor layer 24 does not be in the first opening or the concave (four)~- The group II nitride semiconductor layer 34 of the smaller group; in the second part of the training process, the second group of vaporized semiconductor layers 34 having different sizes are formed in the second group. As shown, J = ^ mask layer % is deposited on the surface of the group III nitride semiconductor layer 34 by 3 U. The second patterning mask layer 35 has a larger plurality of: ^ and a smaller plurality of fourth portions M5b , respectively, the alignment ^ 2, 31a and the second portion 31b. For a part of the brother, please refer to Figure 7C, in step (4), when the semiconductor is like a 'second patterned mask sagittal 乍 乍 - mask' to prevent The cover layer is etched. The opening 33a is on the surface of the epitaxial substrate 321 and the patterned group III nitride semiconductor layer is disposed on the first patterned mask layer 31 and the second pattern. Between the mask layers 35. Referring to Figure 7D, the regenerated Group III nitride semiconductor A portion of the second patterned mask layer 35 is laterally and vertically wrapped, and a group III nitride semiconductor layer 34b is formed on the first patterned mask layer 31. Since the second patterned mask layer 35 The third portion 35a is larger in size than the fourth portion 35b, so that the group III nitride semiconductor layer 34b covers the fourth portion 35b but does not completely cover the third portion 35a, that is, the group III nitride semiconductor layer 34b only includes a part of the second patterned mask layer 35. Further, before the regenerative group III nitride semiconductor layer 34b, the second patterned mask layer 35 may be removed by etching using the steps (S55) of FIGS. 5A to 5C. However, in the embodiment, the second patterned mask layer 35 is not removed according to the steps of FIGS. 5A to 5C. As shown in FIG. 7E, in order to separate the group III nitride semiconductor layer 34b and the epitaxial substrate 32, the group III nitride semiconductor layer 34b is bonded to the transfer substrate 37, and the first patterned mask layer is removed by a wet etching process. 31 (S90) and a larger third portion 35a of the second patterned mask layer 35. As a result, the group III nitride semiconductor layer 34c having a portion of the second* patterned mask layer 35 is obtained. Referring to Fig. 8A to Fig. 81, there is shown a schematic diagram showing the structure and flow of a method for fabricating another group III nitride semiconductor layer in the sixth embodiment of the present invention. Different from the fifth embodiment, the epitaxial substrate in the step S10 has a plurality of layers of materials, and the gallium nitride substrate G and the sapphire substrate 421 are used as an epitaxial substrate 42. In addition, the method for fabricating a group III nitride semiconductor may further include: disposing a third patterned mask layer on the epitaxial substrate, 18 201216328 and located in the first openings (S60) and removing the second patterned mask layer (S55). Referring to FIG. 8A, a gallium nitride substrate G is disposed on the surface of the sapphire substrate 421, and the first patterned mask layer 41 is partially deposited on the gallium nitride substrate G, and a plurality of first openings 43 are formed. The gallium nitride substrate G may be a semiconductor substrate that is remotely crystallized on the gemstone substrate 421 or a separate substrate product. Referring to Fig. 8B, the tri-type nitride semiconductor layer 44 is formed by the parasitic lateral growth method, and the first patterned mask layer 41 is coated laterally and vertically. Referring to FIG. 8C, a second patterned mask layer 45 is formed on the group III nitride semiconductor layer 44a, and the second patterned mask layer 45 is located on the first patterned mask layer 41, and the second pattern is formed. The mask layer 45 is used to shield part of the group III nitride semiconductor layer 44a, so that after the group III nitride semiconductor etching step (S50), the epitaxially grown group III nitride semiconductor layer 44a does not nitrite with the original The gallium substrate G is connected, and even a portion of the gallium nitride substrate G is removed, and an opening 43a is formed in the gallium nitride substrate G. As a result, the group III nitride semiconductor layer 44a is interposed between the first patterned mask layer 41 and the second patterned mask layer 45. Next, referring to FIG. 8D, in step S60, a third patterned mask layer 48 is formed on the epitaxial substrate to fill the opening 43a. Next, please refer to FIG. 8E, etching can be performed using inductively coupled plasma to remove the second patterned mask layer 45. Referring to FIG. 8F, the regenerated group III nitride semiconductor layer 44b is laterally and vertically epitaxially formed on the first patterned mask layer 41, wherein the third patterned mask layer 48 prevents the regenerated three-group nitrogen. The compound semiconductor layer 44b is bonded to the original gallium nitride substrate G. Next, referring to FIG. 8G and FIG. 8H, the transfer substrate 47 is bonded to the regenerated group III nitride semiconductor layer 44b, and the first patterned mask layer 41 and the third pattern are patterned by a wet etching process. Mask layer 48 is removed. Among them, the regenerative group III nitride semiconductor layer 44b bonded to the transfer substrate 47 is preferably subjected to a subsequent process. It should be noted that the sequence after step S55 and step S60 is not fixed, and S55 may be performed first and then S60. Further, the gallium nitride substrate G separated from the group III nitride semiconductor layer 44b can be reused to reduce the material cost. According to the invention, a method for fabricating a group III nitride semiconductor according to the present invention, by using a first patterned mask layer as a mask, thereby controlling the growth of the group III nitride semiconductor layer at the position of the epitaxial substrate, The Group III nitride semiconductor layer is grown by subsequent etching and epitaxial growth to obtain a Group III nitride semiconductor having a lower defect density. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart showing a method for fabricating a Group III nitride semiconductor according to a first embodiment of the present invention; FIG. 2A to FIG. 2F are diagrams showing a method for fabricating a Group III nitride semiconductor according to a first embodiment of the present invention; 3 is a schematic diagram of a regenerative group III nitride semiconductor layer applied to an LED substrate; 20 201216328 FIG. 4A to FIG. 4C are schematic diagrams and flowcharts of another method for fabricating a group III nitride semiconductor according to a second embodiment of the present invention; 5A to 5F are schematic diagrams and flowcharts of a method for fabricating a group III nitride semiconductor according to a third embodiment of the present invention; FIGS. 6A to 6C are diagrams showing a method for fabricating a group III nitride* semiconductor according to a fourth embodiment of the present invention; FIG. 7A to FIG. 7F are schematic diagrams and flowcharts of a method for fabricating a group III nitride semiconductor according to a fifth embodiment of the present invention; and FIG. 8A to FIG. 81 are diagrams of a sixth embodiment of the present invention. A schematic diagram and a flow chart of a method for fabricating a Group III nitride semiconductor. [Description of main component symbols] I, la, 2: Wafer structure II, 31, 41: first patterned mask layer 11a, 48: third patterned mask layer III, 16: bonding surface • 12, 22, 32, 42: epitaxial substrate 121, 131, 141, 321 : surface. 13, 33, 43: first opening 13a, 33a, 43a: opening 14a ' 14b, 14c, 14d, 14e, 24, 34, 34a, 34b 34c, 44, 44a, 44b: Group III nitride semiconductor layer 15: sacrificial layer 17, 37, 47: transfer substrate 21 201216328 2b 35, 45: second patterned mask layer 23, C: second opening 2 6 · Conductor 31a: first part 31b: second part. 35a: third part 35b: fourth part 421: sapphire substrate AA: hatching · G: gallium nitride substrate Gp: gap P: circuit Plate S: Group III nitride semiconductor substrate S10 to S90: steps
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