KR970053783A - BGA Semiconductor Package - Google Patents

BGA Semiconductor Package Download PDF

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Publication number
KR970053783A
KR970053783A KR1019950069098A KR19950069098A KR970053783A KR 970053783 A KR970053783 A KR 970053783A KR 1019950069098 A KR1019950069098 A KR 1019950069098A KR 19950069098 A KR19950069098 A KR 19950069098A KR 970053783 A KR970053783 A KR 970053783A
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South Korea
Prior art keywords
semiconductor chip
semiconductor package
bga
film tape
package according
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KR1019950069098A
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Korean (ko)
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KR100331067B1 (en
Inventor
곽노흥
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황인길
아남산업 주식회사
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Publication of KR970053783A publication Critical patent/KR970053783A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/184—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components inserted in holes through the PCBs and wherein terminals of the components are connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 BGA 반도체 패키지에 관한 것으로, 두개 이상의 반도체칩을 다단으로 적충하여 반도체칩의 용량을 증폭시킨 것으로, 상면에 다수의 칩 패드가 형성된 반도체칩과; 상기 반도체칩이 안치되어 부착될 수 있는 호이 형성되고, 내부에 히로패턴이 형성된 다층의 PCB 기판과; 상기 PCB기판의 저면에 형성되며 반도체칩의 회로를 외부로 인출하는 다수의 솔더볼과; 상기 반도체 칩을 보호하기 위하여 감싸진 봉지재로 구성된 BGA반도체 패키지에 있어서, 상기 반도체칩은 제1반도체칩과 제2반도체칩을 필름테이프에 의해 연결시킨 다층의 반도체칩으로 구성된 BGA 반도체 패키지이다.The present invention relates to a BGA semiconductor package comprising a semiconductor chip having a plurality of chip pads formed on an upper surface thereof by amplifying a capacity of a semiconductor chip by stacking two or more semiconductor chips in multiple stages; A multi-layer PCB substrate having an arc to which the semiconductor chip is placed and attached, and having a Hiro pattern formed therein; A plurality of solder balls formed on the bottom surface of the PCB and drawing out circuits of the semiconductor chip to the outside; In the BGA semiconductor package consisting of an encapsulant encapsulated to protect the semiconductor chip, the semiconductor chip is a BGA semiconductor package consisting of a multilayer semiconductor chip connecting the first semiconductor chip and the second semiconductor chip by a film tape.

Description

BGA 반도체 패키지BGA Semiconductor Package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 BGA 반도체 패키지의구성을 도시한 단면도.1 is a cross-sectional view showing the configuration of a BGA semiconductor package according to the present invention.

Claims (11)

상면에 다수의 칩패드가 형성된 반도체칩과; 상기 반도체칩이 안치되어 부착될 수 있는 홈이 형성되고, 내부에 회로패턴이 형성된 다층의 PCB 기판과; 상기 PCB 기판의 저면에 형성되며 반도체칩의 회로를 외부로 인출하는 다수의 솔더볼과; 상기 반도체 칩을 보호하기 위하여 감싸진 봉지재로 구성된 BGA 반도체 패키지에 있어서, 상기 반도체칩은 제1반도체칩과 제2반도체칩을 필름테이프에 의해 연결시킨 다층의 반도체칩으로 구성된 것을 특징으로 BGA 반도체 패키지.A semiconductor chip having a plurality of chip pads formed on an upper surface thereof; A multilayer PCB substrate in which grooves to which the semiconductor chip is placed and attached are formed, and circuit patterns are formed therein; A plurality of solder balls formed on a bottom surface of the PCB board and drawing circuits of the semiconductor chip to the outside; A BGA semiconductor package comprising an encapsulant encapsulated to protect the semiconductor chip, wherein the semiconductor chip comprises a multilayer semiconductor chip in which a first semiconductor chip and a second semiconductor chip are connected by a film tape. package. 제1항에 있어서, 상기 제1반도체칩과 제2반도체칩은 그용량이 동일한 것을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip have the same capacity. 제1항에 있어서, 상기 필름테이프는 양측면에 골드볼이 형성되어 제1반도체칩의 챕패드와 제2반도체칩의 칩패드가 각각 골드볼에 연결됨을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 1, wherein the film tape has gold balls formed at both sides thereof, and the chapter pads of the first semiconductor chip and the chip pads of the second semiconductor chip are connected to the gold balls, respectively. 제1항에 있어서, 상기 필름테이프는 외측으로 외부단자가 인출되어 다층의 PCB 기판에 연결됨을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 1, wherein the film tape is connected to a multilayer PCB substrate with an external terminal drawn outward. 제1항에 있어서, 상기 필름테이프에는 회로패턴이 형성된 것을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package of claim 1, wherein a circuit pattern is formed on the film tape. 제5항에 있어서, 상기 필름테이프는 다층으로 구성되을 특징으로 하는 BGA 반도체 패키지.6. The BGA semiconductor package according to claim 5, wherein the film tape is composed of multiple layers. 제6항에 있어서, 상기 다층의 필름테이프는 테이프 어셈블리 본딩(Tape Assembly Bonding)에 의해 형성됨을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package of claim 6, wherein the multilayer film tape is formed by tape assembly bonding. 제4항에 있어서, 상기 필름테이프에 인출된 외부단자는 캐피러리에 의해 다층의 PCB 기판에 연결됨을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 4, wherein the external terminal drawn on the film tape is connected to the multilayer PCB substrate by a capillary. 제8항에 있어서, 상기 필름테이프의 외부단자와 PCB기판을 연결하는 캐피러리는 그 저면에 홈이 형성된 것을 특징으로 하는 BGA 반도체 패키지.9. The BGA semiconductor package according to claim 8, wherein the capillary connecting the external terminal of the film tape and the PCB substrate has a groove formed on its bottom surface. 제8항에 있어서, 상기 캐피러리로 필름테이프의 외부단자와 PCB 기판을 연결할때 초음파 열접착에 의해 연결하을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 8, wherein the capillary is connected by ultrasonic thermal bonding when the external terminal of the film tape is connected to the PCB substrate. 제1항에 있어서, 상기 다층의 PCB 기판에 형성된 호에 반도체칩이 안치되어 부착되고, 그 내부는 비전도성 에폭시 채워서 봉합시키는 것을 특징으로 하는 BGA 반도체 패키지.The BGA semiconductor package according to claim 1, wherein a semiconductor chip is placed and attached to an arc formed on the multilayer PCB substrate, and an inside thereof is filled with a nonconductive epoxy and sealed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069098A 1995-12-30 1995-12-30 Ball grid array semiconductor package Expired - Fee Related KR100331067B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069098A KR100331067B1 (en) 1995-12-30 1995-12-30 Ball grid array semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069098A KR100331067B1 (en) 1995-12-30 1995-12-30 Ball grid array semiconductor package

Publications (2)

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KR970053783A true KR970053783A (en) 1997-07-31
KR100331067B1 KR100331067B1 (en) 2002-08-08

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000055911A (en) * 1999-02-11 2000-09-15 이중구 Ball grid array package
KR100444175B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 ball grid array of stack chip package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000055911A (en) * 1999-02-11 2000-09-15 이중구 Ball grid array package
KR100444175B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 ball grid array of stack chip package

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Publication number Publication date
KR100331067B1 (en) 2002-08-08

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