KR20260017420A - Data encoding method and chip, data decoding method and chip, display device - Google Patents

Abstract

The present application discloses a kind of data encoding method and chip, a data decoding method and chip, and a display device. Image data used for inputting to a display panel is acquired, the image data includes a plurality of sub-image data, and each sub-image data includes a plurality of data combinations; an address of specific data among each data combination of each sub-image data is acquired, the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; an address and a bit value of a first specific data among the data combinations are written to one preset bit position combination among a plurality of preset bit position combinations of row configuration information of the sub-image data; and an address and a bit value of (N+1)-th specific data among the data combinations are written to a bit position where the N-th specific data among the data combinations is located.

Description

Data encoding method and chip, data decoding method and chip, display device

This application claims priority to a Chinese patent application bearing application number 202410882823.5 filed with the China Patent Office on July 3, 2024, and all of the contents of said Chinese patent application are incorporated herein by reference.

The present application relates to the field of display technology, and more specifically, to a data encoding method and chip, a data decoding method and chip, and a display device.

Display devices typically transmit data at high speed through a point-to-point transmission interface protocol, which may be a new high-speed point-to-point interface transmission protocol (China Standard Point-to-Point Interface, CSPI).

The technical solution of the CSPI protocol is to use 8b/9b encoding to re-encode the data stream so that the consecutive 1s or 0s in the data stream do not exceed 5 bits, i.e., by inserting one bit of 0 for every 5 consecutive 1s, or one bit of 1 for every 5 consecutive 0s, to implement DC balancing.

8b/9b encoding technology can implement DC balancing, but it requires 9 bits of bandwidth to transmit 8 bits of data, which results in an additional overhead of 11.1%. The larger the additional overhead, the more bandwidth is sacrificed, resulting in more power consumption at the transmitter and receiver.

An embodiment of the present application provides a data encoding method, wherein the data encoding method comprises:

A step of obtaining image data for input to a display panel; wherein the image data includes a plurality of sub-image data, each of the sub-image data is used to input to one row pixel unit of the display panel, and each of the sub-image data includes a plurality of data combinations;

A step of obtaining an address of specific data among each of the data combinations of each of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;

A step of recording the address and bit value of the first specific data among the above data combinations into one of the plurality of preset bit position combinations of row configuration information of the sub-image data; and

A step of recording the address and bit value of the N+1th specific data among the above data combinations at the bit position where the Nth specific data among the above data combinations is located; wherein, N is a positive integer.

An embodiment of the present application also provides a kind of data decoding method, said data decoding method comprising:

A step of receiving encoded image data; wherein the image data includes a plurality of sub-image data, each of the sub-image data is for inputting into one row pixel unit of a display panel, and each of the sub-image data includes a plurality of data combinations;

A step of restoring the first replacement data among at least one data combination to specific data according to data recorded in at least one preset bit position combination of row configuration information of the sub-image data, wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; and

A step of restoring the (N+1)th replacement data among the data combinations to the specific data according to the Nth replacement data among the data combinations; wherein the Nth replacement data includes an address of the (N+1)th replacement data and a restored bit value, and N is a positive integer.

An embodiment of the present application also provides a kind of encoding chip, wherein the encoding chip includes computer instructions, wherein the computer instructions are:

A step of obtaining image data for input to a display panel; wherein the image data includes a plurality of sub-image data, each of the sub-image data is used to input to one row pixel unit of the display panel, and each of the sub-image data includes a plurality of data combinations;

A step of obtaining an address of specific data among each of the data combinations of each of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;

A step of recording the address and bit value of the first specific data among the above data combinations into one of the plurality of preset bit position combinations of row configuration information of the sub-image data; and

A step of recording the address and bit value of the N+1th specific data among the above data combinations at the bit position where the Nth specific data among the above data combinations is located; wherein, N is a positive integer.

An embodiment of the present application also provides a kind of decoding chip, wherein the decoding chip includes computer instructions, wherein the computer instructions include:

A step of receiving encoded image data; wherein the image data includes a plurality of sub-image data, each of the sub-image data is for inputting into one row pixel unit of a display panel, and each of the sub-image data includes a plurality of data combinations;

A step of restoring the first replacement data among at least one data combination to specific data according to data recorded in at least one preset bit position combination of row configuration information of the sub-image data, wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; and

A step of restoring the (N+1)th replacement data among the data combinations to the specific data according to the Nth replacement data among the data combinations; wherein the Nth replacement data includes an address of the (N+1)th replacement data and a restored bit value, and N is a positive integer.

An embodiment of the present application also provides a display device, the display device including a display panel, an encoding chip, and a decoding chip, wherein the encoding chip is used to execute a data encoding method provided in an embodiment of the present application and output image data encoded to the decoding chip, the decoding chip is used to execute a data decoding method provided in an embodiment of the present application on the encoded image data and output the decoded image data to the display panel, and the display panel is used to display an image according to the decoded image data output by the decoding chip.

Figure 1 is a flowchart of a data encoding method provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of a pixel unit provided in an embodiment of the present application;
Figure 3 is a schematic diagram of a method for defining a data block address provided in an embodiment of the present application.
FIG. 4 is a schematic diagram of a method for defining an address within a data block provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of a bit structure of a preset bit position combination provided in an embodiment of the present application;
Figure 6 is a schematic diagram of a method for defining row configuration information provided in an embodiment of the present application;
FIG. 7 is a schematic diagram of encoded image data provided in an embodiment of the present application;
FIG. 8 is a schematic diagram of encoded sub-image data provided in an embodiment of the present application;
Figure 9 is a schematic diagram of the command meaning provided in an embodiment of the present application;
Figure 10 is a schematic diagram of a kind of encoded image data;
Figure 11 is a schematic diagram of a data encoding process provided in an embodiment of the present application;
FIG. 12 is a schematic diagram of an address display within a data block provided in an embodiment of the present application;
FIG. 13 is a flowchart of a data decoding method provided in an embodiment of the present application;
Fig. 14 is a schematic diagram of an encoding chip provided in an embodiment of the present application;
Fig. 15 is a schematic diagram of a decoding chip provided in an embodiment of the present application;
Figure 16 is a schematic diagram of a display device provided in an embodiment of the present application.

Below, the technical solutions of the embodiments of this application will be described in conjunction with the drawings of the embodiments of this application. The technical solutions described are intended only to interpret and explain the concepts of this application and should not be considered to limit the scope of protection of this application.

Additionally, in the embodiments of the present application, "plurality" means two or more. In the embodiments of the present application, "first" and "second" are used to distinguish different technical features, and do not indicate order, quantity, or importance.

The various embodiments provided in this application are similar, and features of different embodiments can be combined with each other.

The order in which the following examples are described is not intended to be a limitation on the preferred order of the examples.

Embodiments of the present application provide a data encoding method and chip, a data decoding method and chip, and a display device. The display device may be integrated into a display device, including, but not limited to, a television, a smartphone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and the like.

In the embodiment of the present application, the data encoding method provided by the present application is described from the perspective of a display device, that is, the display device is described as an executing entity.

Referring to FIG. 1, FIG. 1 is a flowchart of a data encoding method provided in an embodiment of the present application. The data encoding method may include at least one of steps 110 to 140 below.

Step 110, image data for input to a display panel is obtained, the image data includes a plurality of sub-image data, each sub-image data is for input to a pixel unit of one row of the display panel, and each sub-image data includes a plurality of data combinations.

A display panel refers to a component used to display an image, and may include a plurality of pixel units, each of which may emit light, display color, or reflect light to generate an image. The type of the display panel may be set according to an actual situation, for example, the display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED), and the embodiments of the present application are not limited thereto. The pixel units included in the display panel may exist in the form of rows and/or columns. For example, the display panel includes a plurality of row pixel units and a plurality of column pixel units, as illustrated in FIG. 2.

In an embodiment of the present application, image data to be input to a display panel includes a plurality of bits, and the bit value of each bit position existing in the image data and the sub-image data is 0 or 1. Since the sub-image data is used to be input to a pixel unit in one row of the display panel, the division of the sub-image data in the image data may match the division of the number of pixel unit rows in the display panel. For example, if the display panel includes L rows of pixel units, the image data may include L pieces of sub-image data, where L is a positive integer.

In each sub-image data of the image data, the embodiment of the present application sets a plurality of data combinations, each data combination being a bit sequence in the sub-image data. Here, each sub-image data may include the same quantity of data combinations, optionally, each sub-image data includes X data combinations, where X is a positive integer, for example, X may be 10, 12 or 15. In addition, each data combination may have the same number of bits, optionally, each data combination has Y bits, where Y is a positive integer, for example, Y may be 450, 468, 486, 504, 520 or 540. In an actual application process, the number of data combinations included in the sub-image data may be first determined, and then the number of bits included in each data combination may be determined based on the number of data combinations; or the number of bits included in each data combination may be first determined, and then the number of data combinations included in the sub-image data may be determined based on the number of bits.

In some cases, the sub-image data may contain one or more empty data combinations, and/or the data combination may contain one or more empty bits. Here, "empty" means that the bit value at the bit position is empty, and thus, it can also be said that the sub-image data may not contain one or more specific data combinations, and/or the data combination may not contain one or more specific bits.

For example, if each sub-image data includes 15 data combinations and each data combination is preset to have 540 bits, then for the 966/960 channel of the CSPI protocol, since 966/960 multiplied by 8 bits is approximately 15 times 540 bits, we can say that each data combination is present, but a specific bit of the last data combination is not present, or a specific empty bit exists in the last data combination; for the 726/720 channel of the CSPI protocol, since 726/720 multiplied by 8 bits is approximately 11 times 540 bits, we can say that the last four data combinations are not present, or four empty data combinations exist, and in addition, a specific bit of the fifth-from-the-end data combination is not present, or a specific empty bit exists in the fifth-from-the-end data combination.

Step 120, obtain the address of specific data from each data combination of each sub-image data, the specific data has M bits, and the bit values of the M bits are all 0 or all 1, and M is an integer greater than or equal to 2.

Specific data refers to data in which all bit values on M consecutive bits are the same, and the value of M can be set according to the actual situation, for example, M can be 4, 5, 6, 7, 8, or 9. For example, when M is 9, the specific data includes 000000000 and 11111111, and when M is 5, the specific data includes 00000 and 11111.

The address of a specific piece of data indicates where that piece of data is specifically located within a data set. For each data set within each sub-image data set, the presence of that piece of data can be checked; when a specific piece of data is checked, its address is generated.

In some embodiments, each data set includes multiple data blocks, and each data block corresponds to multiple data addresses. Here, the address of a specific data includes a data block address and an address within the data block, the data block address is the address of the data block in which the specific data is located within the data set, and the address within the data block is the address within the data block in which the specific data is located.

Here, the data block address and the address within the data block can be expressed as bit values, and the number of bits that the data block address has can be determined based on the number of data blocks in the data combination, and the number of bits that the address within the data block has can be determined based on the number of addresses within the data block. For example, assuming that each data combination includes 6 data blocks and that each data block includes 28 addresses, 6 different values are required to distinguish 6 data blocks, 28 different values are required to distinguish 28 addresses, at least 3 bits are required to indicate 6 different values, and at least 5 bits are required to indicate 28 different values, and therefore, the data block address can include 3 bits, and the address within the data block can include 5 bits, and based on this, FIG. 3 exemplarily shows one possible definition method of the data block address, and FIG. 4 exemplarily shows one possible definition method of the address within the data block. What is important to understand is that in Figure 4, "address within data block" and "corresponding address within data block" are different definitions of the same address, where "address within data block" is defined in binary and represents the address as a bit value, and "corresponding address within data block" is defined in decimal and represents the address as a number.

Of course, the address of a particular piece of data can be expressed in other ways as well, for example, the address of a particular piece of data can be determined based on the position occupied by the first bit, the last bit, or any one bit within a data set.

When the address of specific data is expressed by a data block address and an address within the data block, for any one data combination, it is possible to inquire whether specific data exists within each data block of the data combination; and when specific data is inquired, the data block address and the address within the data block of the specific data are generated. Optionally, it is possible to sequentially or in parallel inquire whether specific data exists within each data block, and after the specific data inquiring process for all data blocks is completed, the data block address and the address within the data block of each inquired specific data are generated; or, while sequentially inquiring whether specific data exists within each data block, the data block address and the address within the data block of the specific data are generated each time a specific piece of data is inquired.

In some embodiments, step 120 includes steps 122 to 128 as follows.

Step 122, determine whether the data on the M bits corresponding to the S-th address of the K-th data block in the data combination is specific data, where K is a positive integer less than or equal to P, the initial value of K is 1, P is a positive integer, S is a positive integer less than or equal to Q, the initial value of S is 1, and Q is a positive integer.

Here, each data combination contains P data blocks, and each data block contains Q addresses, where P and Q are both positive integers, for example, P is 5, 6, 7, or 8, and Q is 10, 28, or 44. For any data combination, starting from the first address of the first data block of the data combination (i.e., starting from a state where K is 1 and S is 1), sequentially determining whether data on the M bits corresponding to each address in each data block is specific data is performed, and the process of looking up specific data corresponding to the last address of the last data block is completed (i.e., until K+1 exceeds P and S+1 exceeds Q).

For the Kth data block of the data combination, when the Sth address within the Kth data block is queried, after reading the data on the M bits corresponding to the Sth address, it is possible to determine whether the data on the M bits corresponding to the Sth address are specific data. Optionally, the M bits corresponding to the address within the data block refer to M bits whose start bits are the corresponding bits in the data block.

Since specific data refers to data in which all bit values on M consecutive bits are the same, when determining whether the data on M bits is specific data, it is sequentially determined whether the bit value of the current bit and the bit value of the next bit among the M bits are the same, and if they are all the same, the data on the M bits is specific data, and if there is something that is not the same, the data on the M bits is not the specific data; or after reading the bit value of the first bit among the M bits, it is sequentially determined whether the bit value of the subsequent bit among the M bits is the same as the bit value of the first bit, and if they are all the same, the data on the M bits is specific data, and if there is something that is not the same, the data on the M bits is not the specific data.

Step 124: When the data on the M bits is specific data, the data block address of the specific data and the address within the data block are generated.

For M bits corresponding to the S-th address within the K-th data block, when the data on these M bits is specific data, a data block address of the specific data and an address within the data block are generated in real time, where the data block address is used to indicate the K-th data block, and the address within the data block is used to indicate the S-th address within the K-th data block.

Step 126, set S to S+1, and execute again from the step of determining whether the data on the M bits corresponding to the S-th address in the K-th data block among the data combinations is specific data.

After the judgment in step 122, regardless of whether the data on the M bits corresponding to the S-th address is specific data, step 126 must be performed to continue to judge whether the data on the M bits corresponding to the next address is specific data, that is, S is set to S+1, and the execution is repeated from the step of judging whether the data on the M bits corresponding to the S-th address in the K-th data block among the data combinations is specific data.

What should be understood is that after the judgment in step 122, when the data on the M bits corresponding to the S-th address is specific data, step 124 is performed first and then step 126 is performed; when the data on the M bits corresponding to the S-th address is not specific data, step 126 is performed directly.

Step 128, when S+1 is greater than Q, set K to K+1, set S to 1, and execute again from the step of determining whether the data on the M bits corresponding to the S-th address in the K-th data block among the data combinations is specific data, and proceed until K+1 is greater than P.

Here, whenever S is set to S+1 in step 126, it is first determined whether S+1 is greater than Q, and if S+1 is less than or equal to Q, since all address lookups within the current data block have not been completed, the specific data lookup process for the next address within the current data block is continued, that is, based on the new value of S, the process returns to step 122 and is executed again; if S+1 is greater than Q, since all address lookups within the current data block have been completed, the process of specific data lookup for the next data block is continued, that is, K is set to K+1, and S is set to 1, and based on the new value of K and the new value of S, the process returns to step 122 and is executed again.

Similarly, whenever K is set to K+1 in step 128, it can first be judged whether K+1 is greater than P, if K+1 is less than or equal to P, it means that the entire lookup of the data blocks included in the current data combination is not yet finished, so the specific data lookup process for the next data block of the current data combination is continued, that is, based on the new value of K and the new value of S, return to step 122 and execute again; if K+1 is greater than P, it means that the entire lookup of the data blocks included in the current data combination is finished, so the specific data lookup process for the next data combination is continued, that is, execute steps 122 to 128 again for the next data combination.

Step 130, the address and bit value of the first specific data in the data combination are written to one of the preset bit position combinations in the row configuration information of the sub-image data.

Each sub-image data corresponds to one line configuration information (Line Config), and the line configuration information is used to indicate the relevant parameters that a pixel unit of one row corresponding to the sub-image data has in the display image. The embodiment of the present application adds a plurality of preset bit position combinations to the line configuration information, and each preset bit position combination corresponds to one data combination in the sub-image data.

Here, each preset bit position combination is used to indicate the address and bit of the first specific data in the data combination corresponding to the preset bit position combination. For any one data combination, if specific data exists in the data combination, the address and bit value of the first specific data in the data combination are written to the preset bit position combination corresponding to the data combination in the row configuration information of the sub-image data. Optionally, based on the above-described steps 122 to 128, when it is first confirmed as a result of the judgment in step 122 that the data on the M bits in the data combination is specific data, step 124 may be executed to generate the address of the first specific data, and the address and bit value of the first specific data in the data combination may be written to the preset bit position combination of the row configuration information, or, after generating the addresses of all specific data in the data combination, the address and bit value of the first specific data in the data combination may be written to the preset bit position combination of the row configuration information.

In some embodiments, each preset bit position combination includes a first bit position combination, a second bit position combination, and a third bit position combination, which are all arranged in order, and when the address of the specific data includes a data block address and an address within the data block, the step 130 described above includes: writing the data block address of the first specific data among the data combinations to the first bit position combination of the preset bit position combination; writing the bit value of the first specific data among the data combinations to the second bit position combination of the preset bit position combination; and writing the address within the data block of the first specific data among the data combinations to the third bit position combination of the preset bit position combination.

Here, each bit position combination has one or more bits, and the number of bits that the bit position combination has can be set according to the actual situation. For example, the number of bits that the first bit position combination has matches the number of bits that the data block address of the specific data has, the number of bits that the third bit position combination has matches the number of bits that the address within the data block of the specific data has, and furthermore, since the bit values of the specific data have only two values, 0 and 1, the number of bits that the second bit position combination has is 1. Assuming that the data block address of the specific data has 3 bits and the address within the data block has 5 bits, the possible bit structures for the preset bit position combinations of the row configuration information are as shown in Fig. 5.

In some embodiments, each sub-image data includes T data combinations that are all arranged in order, and the row configuration information of each sub-image data includes T preset bit position combinations that are all arranged in order, where T is a positive integer. For example, T is 10, 12, or 15. Based on this, the above-described step 130 includes writing an address and a bit value of a first specific data in an R-th data combination to the R-th preset bit position combination of the row configuration information of the sub-image data, where R is a positive integer less than or equal to T. That is, the order in which the plurality of data combinations are arranged in the corresponding sub-image data matches the order in which the plurality of preset bit position combinations are arranged in the corresponding row configuration information.

In some embodiments, the data encoding method further includes writing first preset invalid data to the R-th preset bit position combination of the row configuration information of the sub-image data when specific data does not exist in the R-th data combination.

In some embodiments, the data encoding method further includes filling the R-th preset bit of the row configuration information of the sub-image data with second preset invalid data if the R-th data combination does not exist. For a description of the case where one or more specific data combinations do not exist in the sub-image data, refer to the description of step 110 described above, but will not be described in detail herein.

Here, the first preset invalid data is used to indicate that specific data does not exist in the data combination, and the second preset invalid data is used to indicate that the data combination does not exist. Optionally, if the address of the specific data includes a data block address and an address within the data block, the first preset invalid data and the second preset invalid data include a preset invalid data block address and/or an address within the invalid data block, and for descriptions of the invalid data block address and the address within the invalid data block, refer to FIGS. 3 and 4.

For example, if the preset bit position combination includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order, the address of the invalid data block among the first preset invalid data and the second preset invalid data is filled into the first bit position combination of the preset bit position combination, and the address within the invalid data block among the first preset invalid data and the second preset invalid data is filled into the third bit position combination of the preset bit position combination, and further, since the second bit position combination of the preset bit position combination can be arbitrarily filled with 0 or 1, the preset bit position combination filled with the first preset invalid data and the second preset invalid data can be one of the following arbitrary bit value cases: 000000000, 000011101, 000011110, 000011111, 000100000, 000111101, 000111110, 000111111, 111000000, 111011101, 111011110, 111011111, 111100000, 111111101, 111111110, 11111111.

It should be understood that in the embodiments of the present application, the first preset invalid data and the second preset invalid data may have the same bit value or different bit values. For example, the first preset invalid data and the second preset invalid data may both be 111011111; or the first preset invalid data may be 000111111 and the second preset invalid data may be 111000000.

In some embodiments, the preset bit position combination is a header bit position combination, and the row configuration information further includes a command (CMD) bit position combination and a register (Reserve) bit position combination; when the sub-image data includes X data combinations, the row configuration information includes a 1T CMD bit position combination, an XT header bit position combination, and a 4T register bit position combination.

For example, when X is 15, one possible definition way of row configuration information is as shown in FIG. 6, and data (i.e., encoded image data) transmitted from an encoding chip of a display device to a decoding chip is as shown in FIG. 7, and one row data (i.e., encoded sub-image data) among them is as shown in FIG. 8, and furthermore, the meaning of each command appearing from FIG. 6 to FIG. 8 is as shown in FIG. 9, and furthermore, FIG. 10 exemplarily shows data transmitted from an encoding chip of a display device to a decoding chip in a related art, and based on the data encoding method provided in the embodiment of the present application, the row configuration information is compatible with the data encoding method of the existing CSPI protocol by including a combination of existing CMD bit positions.

Step 140, the address and bit value of the N+1th specific data among the data combinations are written to the bit where the Nth specific data among the data combinations is located, where N is a positive integer.

For any data combination, if two or more specific data exist in the data combination, the address and bit value of the (N+1)th specific data in the data combination are written to the bit where the Nth specific data in the data combination is located, where N is a positive integer. That is, the address and bit value of the second specific data in the data combination are written to the bit where the first specific data in the data combination is located, the address and bit value of the third specific data in the data combination are written to the bit where the second specific data in the data combination is located, and in this manner, the address and bit value of the current specific data in the data combination are written to the bit where the previous specific data in the data combination is located, and the address and bit value of the last specific data in the data combination are written to the bit where the second-to-last specific data in the data combination is located. This continues until.

In some embodiments, the bit structure of the data combination after the specific data is replaced (i.e., the bit structure of the bits in which the address and bit value are written after the address and bit value are written to the bits where the specific data is located) is identical to the bit structure of the preset bit position combination of the row configuration information. By setting the same bit structure, it is ensured that a unified encoding standard is followed during the encoding process, thereby improving encoding efficiency. In this manner, it should be understood that the number of bits that the specific data has is identical to the number of bits that the preset bit position combination has, i.e., a total of M bits.

For example, if the preset bit position combination includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order, the bit structure after the specific data is replaced also includes three bit position combinations arranged in order, and further, when writing the address and bit value to the bit where the specific data is located, the data block address, the bit value, and the address within the data block are written in order to these three bit position combinations. For other introductions and descriptions regarding the bit structure and the number of bits of the preset bit position combination, please refer to the description of step 130 described above, which will not be described in detail herein.

In some embodiments, the data encoding method further includes a step of writing third preset invalid data to a bit where the last specific data in the data combination is located, wherein the third preset invalid data is used to indicate that the encoding process of the data combination has ended. That is, for any data combination, when the specific data search process of the data combination has ended, the last specific data in the data combination can be identified, and the third preset invalid data is written to a bit where the last specific data in the data combination is located, thereby indicating that the encoding process for the data combination has ended. Optionally, when the address of the specific data includes a data block address and an address within the data block, the third preset invalid data includes the preset invalid data block address and/or the address within the invalid data block, and an introduction and description regarding the invalid data block address and the address within the invalid data block refer to FIGS. 3 and 4 .

For example, after the third preset invalid data is written to the bit where the last specific data is located in the data combination, the following arbitrary bit values can be taken: 000000000, 000011101, 000011110, 000011111, 000100000, 000111101, 000111110, 000111111, 111000000, 111011101, 111011110, 111011111, 111100000, 1111111101, 111111110, 11111111.

Hereinafter, a data encoding method provided by an embodiment of the present application is introduced and described through specific examples. Fig. 11 shows one data combination as an example, and the data combination has 540 bits. If the data combination is divided into 6 data blocks, each data block has 90 bits; for each data block, as shown in Fig. 12, starting from the first bit of each data block, if the first bit is indicated as address 1, and then one address is indicated for every two bits, 28 addresses can be indicated for each data block.

In the data encoding process, the display device starts from the first address (address 1) within the first data block (1st Block (90 bits)) and determines whether the data on the 9 bits (1st search 9 bits) starting from the bit where address 1 is located is specific data (whether the bit values are all 0 or all 1); regardless of whether the data is specific data, the display device must continue to determine whether the data on the 9 bits (2nd search 9 bits) starting from the bit where address 2 is located is specific data, and so on until the display device determines whether the data on the 9 bits (28th search 9 bits) starting from the last address within the last data block (6th Block (90 bits)) is specific data.

In the above-described specific data lookup process, when the data on the first 9 bit positions is confirmed as specific data, the data block address, bit value, and address within the data block of the specific data (the first specific data) are filled into the header bit position combination of the row configuration information.

As shown in Fig. 11, when specific data is first checked in the 9 bits (4th search 9 bits) starting from the bit where the fourth address is located within the first data block, the specific data 000000000 is the first specific data; the data block address of the first specific data is 001, which is recorded in the first bit position combination (d0d1d2) of the header bit position combination; the bit value of the first specific data is 0, which is recorded in the second bit position combination (d3) of the header bit position combination; the address of the first specific data within the data block is 00100, which is recorded in the third bit position combination (d4d5d6d7d8) of the header bit position combination; therefore, the bit value of the header bit position combination is 001000100.

In the above-described specific data lookup process, each time the next specific data is looked up, the address and bit value of the next specific data are written to the bit where the current specific data is located, and also, the bit structure after the specific data is replaced is the same as the bit structure of the header bit position combination, so that the address and bit value of each specific data can be displayed through the bit where the previously replaced specific data is located.

As shown in Fig. 11, when the second specific data is checked in the 9 bits (28th search 9 bits) starting from the last address (data address 28) in the last data block (6th Block (90 bit)), the specific data 111111111 is the second specific data; the data block address of the second specific data is 110, the bit value is 1, the address in the data block is 11100, and the address and bit value of the second specific data are written in the bits where the first specific data is located; therefore, the bit value on the bit where the replaced first specific data is located is 110111100.

After the above-described specific data query is completed, the last specific data in the data combination can be confirmed, and the third preset invalid data is written to the bit where the last specific data is located to indicate that the encoding process for the data combination has been completed. Here, the third preset invalid data includes the preset invalid data block address and/or an address within the invalid data block.

As shown in Fig. 11, when the last specific data is checked in the 9 bits (28th search 9 bit) starting from the last address (data address 28) within the last data block (6th Block (90 bit)), the specific data 111111111 is the last specific data (and simultaneously the second specific data among the data combinations); the third preset invalid data is written to the bit where the last specific data is located. Assuming that 000 is one of the possible invalid data block addresses and 11101 is one of the possible invalid data block addresses, the third preset invalid data can be 000111101; therefore, the bit value on the bit where the last specific data that was replaced is 000111101.

In summary, the embodiment of the present application breaks the situation in which multiple logical 1s or multiple logical 0s originally present in the image data appear continuously by replacing data having the same consecutive multiple-bit values among the image data with the address and bit value of other data having the same consecutive multiple-bit values during the encoding process, and realizes DC balance, thereby effectively preventing errors due to DC offset during the decoding process.

In addition, the embodiment of the present application does not add new bits to the original bits of the image data by replacing data with consecutive multi-bit values having the same data, but instead sets up row configuration information separately for each sub-image data of the image data, so that the address and bit value of the data with the same first consecutive multi-bit value among each data combination of the sub-image data of the image data are written to the corresponding preset bit position combination of the row configuration information of the sub-image data, and since the number of bits of the image data is much greater than the number of bits of the row configuration information, compared to the related art that inserts a large number of redundant bits into the image data, the embodiment of the present application only needs to configure an additional small number of bits, thereby reducing the additional overhead of data transmission and preventing excessive power consumption at the transmitter and receiver. For example, in the 8b/9b encoding technology, 9 bits of bandwidth are required for transmitting 8-bit data, and the additional overhead is 11.1%; whereas in the embodiment of the present application, 9 additional bits are required as the preset bit position combination of the row configuration information for transmitting 540-bit data, and the additional overhead is 1.6%.

In addition, through the technical solution of the embodiment of the present application, the address and bit value of the same data of each original consecutive multi-bit value in the image data all have corresponding instructions after encoding, so that in the decoding process, the address and bit value of the same data of each original consecutive multi-bit value in the image data can be obtained based on a combination of preset bit positions of the row configuration information or based on data replaced in the image data, thereby restoring the same data of each consecutive multi-bit value replaced in the image data, thereby ensuring that the encoded image data can be decoded accurately. In this way, the embodiment of the present application implements DC balance and reduces additional overhead, while also ensuring the reliability of the encoding and decoding processes.

Referring to Figure 13, Figure 13 is a flowchart of a data decoding method provided in an embodiment of the present application. The data decoding method may include at least one of steps 210 to 230 below.

Step 210, receiving encoded image data, the image data including a plurality of sub-image data, each sub-image data being for inputting into one row pixel unit of a display panel, and further, each sub-image data including a plurality of data combinations.

Step 220, according to data recorded on at least one preset bit position combination of row configuration information of sub-image data, the first replacement data among at least one data combination is restored to specific data, the specific data has M bits, and further, the bit values on the M bits are all 0 or all 1, and M is an integer greater than or equal to 2.

Step 230, according to the Nth replacement data among the data combinations, the N+1th replacement data among the data combinations is restored to specific data, the Nth replacement data includes the address of the N+1th replacement data and the restored bit value, and N is a positive integer.

Here, replacement data refers to data obtained by replacing specific data within a data combination during encoding. That is, during encoding, the address and bit value of the N+1th specific data within the data combination are recorded in the bit where the Nth specific data is located within the data combination, and then the data on the bit where the original Nth specific data is located is replaced with the Nth replacement data.

What you need to understand is that the address of the Nth replacement data and the address of the Nth specific data are the same, and the bit value after the Nth replacement data is restored and the bit value of the Nth specific data are also the same. Since the address and bit value of the first specific data of each data combination are written to each preset bit position combination of the row configuration information of the sub-image data during encoding, the address and restored bit value of the first replacement data of at least one data combination can be obtained according to the data written to at least one preset bit position combination of the row configuration information of the sub-image data during decoding, thereby restoring the first replacement data to the first specific data. In addition, since the address and bit value of the N+1th specific data of the data combination are written to the bit where the Nth specific data of the data combination is located during encoding, the address and restored bit value of the N+1th replacement data of the data combination can be obtained according to the Nth replacement data of the data combination, thereby restoring the N+1th replacement data to the N+1th specific data.

In some embodiments, the sub-image data includes T data combinations arranged in order, the row configuration information includes T preset bit position combinations arranged in order, and T is a positive integer; the step 220 described above includes a step of restoring the first replacement data among the R-th data combination of the sub-image data to specific data according to the data recorded in the R-th preset bit position combination of the row configuration information of the sub-image data, and R is a positive integer less than or equal to T. That is, according to the data recorded in the R-th preset bit position combination of the row configuration information of the sub-image data, the address and the restored bit value of the first replacement data among the R-th data combination of the sub-image data can be obtained, thereby restoring the first replacement data among the R-th data combination to the first specific data.

In some embodiments, if there is no replacement data in the R-th data combination of the sub-image data, the data written to the R-th preset bit position combination of the row configuration information of the sub-image data is the first preset invalid data.

In some embodiments, if the Rth data combination does not exist in the sub-image data, the data written to the Rth preset bit position combination of the row configuration information of the sub-image data is the second preset invalid data.

In some embodiments, data written to the R-th preset bit position combination of the row configuration information of the sub-image data is first preset invalid data; when the first preset invalid data is read from the R-th preset bit position combination of the row configuration information of the sub-image data, the decoding operation for the R-th data combination of the sub-image data is terminated.

In some embodiments, data written to the R-th preset bit position combination of the row configuration information of the sub-image data is second preset invalid data; when the second preset invalid data is read from the R-th preset bit position combination of the row configuration information of the sub-image data, the decoding operation for the R-th data combination of the sub-image data is terminated.

In some embodiments, the last replacement data of the data combination is the third preset invalid data; when the third preset invalid data is read from the data combination, the decoding operation for the data combination is terminated. That is, when encoding, the third preset invalid data is written to the bit where the last specific data in the data combination is located, so the last replacement data of the encoded data combination is the third preset invalid data; when decoding, when the third preset invalid data is read from the encoded data combination, it is confirmed that the corresponding replacement data is the last replacement data, and the decoding process for the data combination is completed.

In some embodiments, the data set includes a plurality of data blocks, each of which corresponds to a plurality of data addresses; the address of the specific data includes a data block address and an address within the data block, the data block address is an address of a data block in which the specific data is located within the data set, and the address within the data block is an address within the data block in which the specific data is located. It should be understood that the address of the replacement data also includes a data block address and an address within the data block, the data block address is an address of a data block in which the replacement data is located within the data set, and the address within the data block is an address within the data block in which the replacement data is located.

In some embodiments, the bit structure of the replacement data is identical to the bit structure of the preset bit position combinations of the row configuration information.

In some embodiments, the bit structure of each preset bit position combination of the row configuration information includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; wherein, data written to the first bit position combination of the preset bit position combination is a data block address of the first replacement data in the encoded data combination, or the data written to the first bit position combination may be said to be a data block address of the first specific data in the data combination before encoding; data written to the second bit position combination of the preset bit position combination is a restored bit value of the first replacement data in the encoded data combination, or the data written to the second bit position combination may be said to be a bit value of the first specific data in the data combination before encoding; data written to the third bit position combination of the preset bit position combination is an address within a data block of the first replacement data in the encoded data combination, or the data written to the third bit position combination may be said to be an address within a data block of the first specific data in the data combination before encoding.

In some embodiments, the bit position structure of the replacement data includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; wherein data written to the first bit position combination of the Nth replacement data among the encoded data combinations is a data block address of the N+1th replacement data among the encoded data combinations, or data written to the first bit position combination may be said to be a data block address of the N+1th specific data among the data combinations before encoding; data written to the second bit position combination of the Nth replacement data among the encoded data combinations is a restored bit value of the N+1th replacement data among the encoded data combinations, or data written to the second bit position combination may be said to be a bit value of the N+1th specific data among the data combinations before encoding; data written to the third bit position combination of the Nth replacement data among the encoded data combinations is an address within a data block of the N+1th replacement data among the encoded data combinations, or data written to the third bit position combination may be said to be an address within a data block of the N+1th specific data among the data combinations before encoding.

It should be understood that the noun interpretation, specific implementation method, and corresponding beneficial effects of the data decoding method provided in the embodiments of the present application may refer to the introduction and description of the data encoding method provided in the embodiments of the present application, and are not described in detail here.

In order to facilitate better implementation of the data encoding method provided in the embodiment of the present application, the embodiment of the present application also provides an encoding chip based on the above-described data encoding method, wherein the encoding chip includes computer instructions, and the computer instructions can be used to execute the above-described data encoding method, wherein the meanings of the nouns are the same as in the above-described data encoding method, and specific implementation details may refer to the description of the method embodiment.

For example, the encoding chip is as shown in FIG. 14, and the computer commands of the encoding chip can be located in the module shown in FIG. 14, and at this time, the encoding chip can include a data acquisition module (1410), an information acquisition module (1420), and a data recording module (1430).

The data acquisition module (1410) is used to acquire image data for input to a display panel, the image data including a plurality of sub-image data, each sub-image data being for input to one row pixel unit of the display panel, and each sub-image data including a plurality of data combinations.

The information acquisition module (1420) is used to acquire the address of specific data in each data combination of each sub-image data, the specific data has M bit positions, the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2.

The data recording module (1430) is used to record the address and bit value of the first specific data among the data combinations into one of the plurality of preset bit position combinations of the row configuration information of the sub-image data. The data recording module (1430) is also used to record the address and bit value of the (N+1)th specific data among the data combinations into the bit position where the Nth specific data among the data combinations is located, where N is a positive integer.

In some embodiments, the data combination includes a plurality of data blocks, and the address of the particular data includes a data block address and an address within the data block, the data block address is an address of a data block where the particular data is located within the data combination, and the address within the data block is an address within the data block where the particular data is located.

In some embodiments, the information acquisition module (1420) described above is also used to determine whether data at M bit positions corresponding to the S-th address within the K-th data block of the data combination is specific data, wherein K is a positive integer less than or equal to P and the initial value of K is 1, P is a positive integer, S is a positive integer less than or equal to Q and the initial value of S is 1, and Q is a positive integer; when the data at M bit positions is specific data, a data block address of the specific data and an address within the data block are generated; S is set to S+1, and the execution is repeated from the step of determining whether data at M bit positions corresponding to the S-th address within the K-th data block of the data combination is specific data; when S+1 is greater than Q, K is set to K+1 and S is set to 1, and the execution is repeated from the step of determining whether data at M bit positions corresponding to the S-th address within the K-th data block of the data combination is specific data, until K+1 is greater than P.

In some embodiments, each preset bit position combination includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; the above-described data recording module (1430) is also used to record a data block address of a first specific data among the data combinations into the first bit position combination of the preset bit position combination; is used to record a bit value of the first specific data among the data combinations into the second bit position combination of the preset bit position combination; and is used to record an address within a data block of the first specific data among the data combinations into the third bit position combination of the preset bit position combination.

In some embodiments, the sub-image data includes T data combinations arranged in order, the row configuration information includes T preset bit position combinations arranged in order, and T is a positive integer; the data recording module (1430) described above is also used to record an address and a bit value of a first specific data among the R-th data combinations into the R-th preset bit position combination of the row configuration information of the sub-image data, and R is a positive integer less than or equal to T.

In some embodiments, when specific data does not exist in the R-th data combination, the data recording module (1430) described above is also used to record the first preset invalid data in the R-th preset bit position combination of the row configuration information of the sub-image data.

In some embodiments, when the Rth data combination does not exist, the data recording module (1430) described above is also used to record the second preset invalid data into the Rth preset bit position combination of the row configuration information of the sub-image data.

In some embodiments, the data recording module (1430) described above is also used to record third preset invalid data at the bit position where the last specific data in the data combination is located.

When implementing specifically, it should be understood that each module described above may be implemented as an independent entity, or may be arbitrarily combined to form one or more entities.

In order to better implement the data decoding method provided in the embodiment of the present application, the embodiment of the present application also provides a decoding chip based on the above-described data decoding method, wherein the decoding chip includes a computer instruction, and the computer instruction can be used to execute the above-described data decoding method, wherein the meaning of the noun is the same as in the above-described data decoding method, and specific implementation details may refer to the description of the method embodiment.

For example, the decoding chip is as shown in FIG. 15, and the computer instructions within the decoding chip may be located in the module shown in FIG. 15, and at this time, the decoding chip may include a data receiving module (1510) and a data restoration module (1520).

The data receiving module (1510) is used to receive encoded image data, the image data includes a plurality of sub-image data, each sub-image data is used to input one row pixel unit of the display panel, and each sub-image data includes a plurality of data combinations.

The data restoration module (1520) is used to restore the first replacement data among at least one data combination to specific data according to data recorded in at least one preset bit position combination of row configuration information of the sub-image data, the specific data having M bit positions, the bit values on the M bit positions being all 0 or all 1, and M being an integer greater than or equal to 2. The data restoration module (1520) is also used to restore the (N+1)-th replacement data among the data combination to specific data according to the N-th replacement data among the data combinations, the N-th replacement data including an address and a restored bit value of the (N+1)-th replacement data, and N being a positive integer.

When implementing specifically, it should be understood that each module described above may be implemented as an independent entity, or may be arbitrarily combined to form one or more entities.

A person skilled in the art will understand that the computer instructions described above can be stored in a computer-readable storage medium and loaded and executed by a processor.

To this end, an embodiment of the present application provides a computer-readable storage medium having computer instructions stored therein, the computer instructions being loaded by a processor to execute any step of a data encoding method or a step of a data decoding method provided in an embodiment of the present application.

For example, the computer instructions might perform the following steps:

Image data for input to a display panel is acquired, the image data includes a plurality of sub-image data, each sub-image data is used to input to one row pixel unit of the display panel, and each sub-image data includes a plurality of data combinations;

Obtain the address of specific data among each data combination of each sub-image data, the specific data has M bit positions, the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;

The address and bit value of the first specific data among the data combinations are written to one of the preset bit position combinations among the plurality of preset bit position combinations of the row configuration information of the sub-image data;

The address and bit value of the N+1th specific data in the data combination are recorded at the bit position where the Nth specific data in the data combination is located, and N is a positive integer.

As another example, the computer instructions might execute the following steps:

Receiving encoded image data, wherein the image data includes a plurality of sub-image data, each of the sub-image data is for inputting into one row pixel unit of a display panel, and each of the sub-image data includes a plurality of data combinations;

According to data recorded in at least one preset bit position combination of row configuration information of the above sub-image data, the first replacement data among at least one of the above data combinations is restored as specific data, the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;

According to the Nth replacement data among the above data combinations, the N+1th replacement data among the above data combinations is restored to the specific data, the Nth replacement data includes the address of the N+1th replacement data and the restored bit value, and N is a positive integer.

Here, the computer-readable storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, etc.

The computer instructions stored in the computer-readable storage medium can execute any step of a data encoding method or any step of a data decoding method provided in the embodiments of the present application, so that any beneficial effect that can be realized by any data encoding method or any beneficial effect that can be realized by a data decoding method provided in the embodiments of the present application can be realized, and for details, refer to the preceding embodiments, and are not described in detail herein.

The embodiment of the present application also provides a display device as shown in FIG. 16, which is a structural schematic diagram of a display device related to the embodiment of the present application, and is specifically described as follows:

The display device includes a display panel, an encoding chip, and a decoding chip, wherein the encoding chip is used to execute the steps of the above-described data encoding method embodiment and output image data encoded by the decoding chip, the decoding chip is used to execute the steps of the above-described data decoding method embodiment on the encoded image data and output the decoded image data to the display panel, and the display panel is used to display an image according to the decoded image data output by the decoding chip.

For specific implementation methods of each of the above tasks and their corresponding beneficial effects, please refer to the detailed description of the data encoding method embodiment and the data decoding method embodiment in the above text, and will not be described in detail here.

The data encoding method and chip, the data decoding method and chip, and the display device provided by the embodiments of the present application have been introduced in detail, and the principles and implementation methods of the present application have been explained by applying specific examples in the text, and the description of the embodiments above is only to help understand the methods of the present application and their core ideas; at the same time, those skilled in the art may change the specific implementation methods and application scope according to the ideas of the present application, and therefore, the contents of the present specification should not be understood as a limitation on the present application in summary.

Claims (20)

As a data encoding method, the data encoding method comprises:
A step of obtaining image data for input to a display panel; wherein the image data includes a plurality of sub-image data, each of the sub-image data is used to input to one row pixel unit of the display panel, and each of the sub-image data includes a plurality of data combinations;
A step of obtaining an address of specific data among each of the data combinations of each of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;
A step of recording the address and bit value of the first specific data among the above data combinations into one of the plurality of preset bit position combinations of row configuration information of the sub-image data; and
A data encoding method comprising: recording the address and bit value of the N+1th specific data among the above data combinations at the bit position where the Nth specific data among the above data combinations is located; wherein, N is a positive integer. In the first paragraph,
The above data combination includes a plurality of data blocks, and the address of the specific data includes a data block address and an address within the data block, the data block address is an address of the data block in which the specific data is located within the data combination, and the address within the data block is an address within the data block in which the specific data is located; and,
The step of obtaining the address of specific data among each data combination of each of the above sub-image data is:
A step of determining whether data on M bits corresponding to the S-th address in the K-th data block among the above data combinations is the specific data, wherein K is a positive integer less than or equal to P, the initial value of K is 1, P is a positive integer, S is a positive integer less than or equal to Q, the initial value of S is 1, and Q is a positive integer;
When the data on the M bit positions is the specific data, a step of generating the data block address of the specific data and the address within the data block;
A step of setting S to S+1 and re-executing from the step of determining whether data on the M bit positions corresponding to the S-th address in the K-th data block among the data combinations is the specific data; and
A data encoding method comprising the steps of setting K to K+1 and setting S to 1 when S+1 is greater than Q, and re-executing from the step of determining whether data on M bits corresponding to the S-th address in the K-th data block among the data combinations is the specific data, and executing the step until K+1 is greater than P. In the first paragraph,
The data combination includes a plurality of data blocks, and the address of the specific data includes a data block address and an address within the data block, the data block address is an address of the data block in which the specific data is located within the data combination, and the address within the data block is an address within the data block in which the specific data is located; each of the preset bit position combinations includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; and
The step of recording the address and bit value of the first specific data among the above data combinations into one of the preset bit position combinations among the plurality of preset bit position combinations of row configuration information of the sub-image data is:
A step of recording the data block address of the first specific data among the data combinations into the first bit position combination of the preset bit position combinations;
A step of recording the bit value of the first specific data among the data combinations into the second bit position combination of the preset bit position combinations; and
A data encoding method comprising the step of recording an address of the first of the specific data among the above data combinations within the data block into the third bit position combination of the preset bit position combinations. In the first paragraph,
The above sub-image data includes T combinations of the above data arranged in order, the row configuration information includes T combinations of the above preset bit positions arranged in order, and T is a positive integer; and
The step of recording the address and bit value of the first specific data among the above data combinations into one of the preset bit position combinations among the plurality of preset bit position combinations of row configuration information of the sub-image data is:
A data encoding method comprising the step of recording the address and bit value of the first specific data among the Rth data combinations into the Rth preset bit position combination of the row configuration information of the sub-image data, wherein R is a positive integer less than or equal to T. In paragraph 4,
The above method also includes:
A data encoding method further comprising the step of recording first preset invalid data in the Rth preset bit position combination of the row configuration information of the sub-image data when the specific data does not exist in the Rth data combination. In paragraph 4,
The above method also includes:
A data encoding method further comprising the step of recording second preset invalid data in the Rth preset bit position combination of the row configuration information of the sub-image data when the Rth above data combination does not exist. In the first paragraph,
The above method also includes:
A data encoding method further comprising the step of recording a third preset invalid data at a bit position where the last specific data among the data combinations is located. In the first paragraph,
The number of bit positions that one of the above preset bit position combinations has is a data encoding method such as M. In the first paragraph,
The above M is a data encoding method of 9. As a data decoding method, the data decoding method comprises:
A step of receiving encoded image data; wherein the image data includes a plurality of sub-image data, each of the sub-image data is for inputting into one row pixel unit of a display panel, and each of the sub-image data includes a plurality of data combinations;
A step of restoring the first replacement data among at least one data combination to specific data according to data recorded in at least one preset bit position combination of row configuration information of the sub-image data, wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; and
A data decoding method comprising: a step of restoring the (N+1)th replacement data among the data combinations to the specific data according to the Nth replacement data among the data combinations; wherein the Nth replacement data includes an address of the (N+1)th replacement data and a restored bit value, and wherein N is a positive integer. In Article 10,
The above sub-image data includes T combinations of the above data arranged in order, the row configuration information includes T combinations of the above preset bit positions arranged in order, and T is a positive integer; and
A step of restoring the first replacement data among at least one of the data combinations to specific data according to data recorded in at least one preset bit position combination of row configuration information of the above sub-image data,
A data decoding method comprising a step of restoring the first replacement data among the R-th data combinations of the sub-image data to the specific data according to the data recorded in the R-th preset bit position combination of the row configuration information of the sub-image data; wherein R is a positive integer less than or equal to T. In Article 11,
A data decoding method for terminating a decoding operation for the Rth data combination of the sub-image data when the first preset invalid data is read from the Rth preset bit position combination of the row configuration information of the sub-image data. In Article 11,
A data decoding method for terminating a decoding operation for the Rth data combination of the sub-image data when the second preset invalid data is read from the Rth preset bit position combination of the row configuration information of the sub-image data. In Article 10,
A data decoding method that terminates a decoding operation for the above data combination when the third preset invalid data is read from the above data combination. In Article 10,
The above data combination includes a plurality of data blocks, and the address of the replacement data includes a data block address and an address within the data block, the data block address is an address of the data block where the replacement data is located within the data combination, and the address within the data block is an address within the data block where the replacement data is located; and,
Each of the preset bit position combinations of the above row configuration information includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; wherein,
The data recorded in the first bit position combination of the above preset bit position combinations is a data block address of the first replacement data among the encoded data combinations;
The data recorded in the second bit position combination of the above preset bit position combination is the bit value of the first replacement data among the encoded data combinations; and,
A data decoding method wherein the data recorded in the third bit position combination of the above preset bit position combinations is an address within a data block of the first alternative data among the encoded data combinations. As an encoding chip,
The above encoding chip includes computer instructions, wherein the computer instructions include:
A step of obtaining image data for input to a display panel; wherein the image data includes a plurality of sub-image data, each of the sub-image data is used to input to one row pixel unit of the display panel, and each of the sub-image data includes a plurality of data combinations;
A step of obtaining an address of specific data among each of the data combinations of each of the sub-image data; wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2;
A step of recording the address and bit value of the first specific data among the above data combinations into one of the plurality of preset bit position combinations of row configuration information of the sub-image data; and
An encoding chip used to execute a step of recording the address and bit value of the N+1th specific data among the above data combinations at the bit position where the Nth specific data among the above data combinations is located; wherein, N is a positive integer. In Article 16,
The data combination includes a plurality of data blocks, and the address of the specific data includes a data block address and an address within the data block, the data block address is an address of the data block in which the specific data is located within the data combination, and the address within the data block is an address within the data block in which the specific data is located; and,
The above computer command also:
A step of determining whether data on M bits corresponding to the S-th address in the K-th data block among the above data combinations is the specific data, wherein K is a positive integer less than or equal to P, the initial value of K is 1, P is a positive integer, S is a positive integer less than or equal to Q, the initial value of S is 1, and Q is a positive integer;
When the data on the M bit positions is the specific data, a step of generating the data block address of the specific data and the address within the data block;
A step of setting S to S+1 and re-executing from the step of determining whether data on the M bit positions corresponding to the S-th address in the K-th data block among the data combinations is the specific data; and
An encoding chip used to execute a step of setting K to K+1 and S to 1 when S+1 is greater than Q, and executing the step of determining whether data on the M bits corresponding to the S-th address in the K-th data block among the data combinations is the specific data, and executing the step until K+1 is greater than P. In Article 16,
The data combination includes a plurality of data blocks, and the address of the specific data includes a data block address and an address within the data block, the data block address is an address of the data block in which the specific data is located within the data combination, and the address within the data block is an address within the data block in which the specific data is located; each of the preset bit position combinations includes a first bit position combination, a second bit position combination, and a third bit position combination arranged in order; and
The above computer command also:
A step of recording the data block address of the first specific data among the data combinations into the first bit position combination of the preset bit position combinations;
A step of recording the bit value of the first specific data among the data combinations into the second bit position combination of the preset bit position combinations; and
An encoding chip used to execute a step of recording an address of the first of the above specific data combinations within the above data block into the third bit position combination of the above preset bit position combinations. As a decoding chip,
The above decoding chip includes computer instructions, wherein the computer instructions include:
A step of receiving encoded image data; wherein the image data includes a plurality of sub-image data, each of the sub-image data is for inputting into one row pixel unit of a display panel, and each of the sub-image data includes a plurality of data combinations;
A step of restoring the first replacement data among at least one data combination to specific data according to data recorded in at least one preset bit position combination of row configuration information of the sub-image data, wherein the specific data has M bit positions, and the bit values on the M bit positions are all 0 or all 1, and M is an integer greater than or equal to 2; and
A decoding chip used to execute a step of restoring the (N+1)th replacement data among the data combinations to the specific data according to the Nth replacement data among the data combinations; wherein the Nth replacement data includes an address and a restored bit value of the (N+1)th replacement data, and N is a positive integer. As a display device,
The display device includes a display panel, an encoding chip, and a decoding chip, wherein the encoding chip is used to execute a data encoding method as described in any one of claims 1 to 9 on image data and output the encoded image data to the decoding chip, the decoding chip is used to execute a data decoding method as described in any one of claims 10 to 15 on the encoded image data and output the decoded image data to the display panel, and the display panel is a display device used to display an image according to the decoded image data output by the decoding chip.