KR20250075409A - Memory device that changes type of codeword stored in memory area and operation method thereof - Google Patents

Abstract

A memory device may include a memory medium including a plurality of memory units, and a controller configured to set a plurality of memory areas, each of which includes at least one of the plurality of memory units, and store a codeword in the plurality of memory areas. The controller may store at least one first codeword having a first type in a target memory area among the plurality of memory areas, search for a defective memory unit among the memory units included in the target memory area, and when a defective memory unit is searched for among the memory units included in the target memory area, convert at least one of the first codewords stored in the target memory area into a second codeword having a second type, and write the converted second codeword to the memory medium.

Description

MEMORY DEVICE THAT CHANGES TYPE OF CODEWORD STORED IN MEMORY AREA AND OPERATION METHOD THEREOF

Embodiments of the present invention relate to a memory device and method for changing the type of a codeword stored in a memory area.

Volatile memory (e.g. SRAM, DRAM) loses stored data when power is cut off, while nonvolatile memory (e.g. NAND Flash, PRAM, MRAM) retains stored data even when power is cut off.

Meanwhile, during the manufacturing process or use of volatile memory, there may be an increased possibility of defects occurring in some areas of volatile memory. If it is determined that an error occurring in a codeword stored in the area cannot be corrected using the existing ECC (Error Correction code), the volatile memory needs to improve error correction performance for areas where defects are likely to occur.

Embodiments of the present invention can provide a memory device and method thereof capable of improving error correction capability for an area where defects are likely to occur.

In one aspect, embodiments of the present invention may provide a memory device including i) a memory media including a plurality of memory units, and ii) a controller that sets a plurality of memory areas, each of which includes at least one of the plurality of memory units, and stores a codeword in the plurality of memory areas. At this time, the controller may store at least one first codeword having a first type in a target memory area among the plurality of memory areas, search for a defective memory unit among the memory units included in the target memory area, and when a defective memory unit is searched for among the memory units included in the target memory area, convert at least one of the first codewords stored in the target memory area into a second codeword having a second type, and write the converted second codeword to the memory media.

In another aspect, embodiments of the present invention can provide a method of operating a memory device, including the steps of: i) setting a plurality of memory areas, each of which includes at least one of a plurality of memory units included in a memory medium; ii) storing at least one first codeword having a first type in a target memory area among the plurality of memory areas; iii) searching for a defective memory unit among the memory units included in the target memory area; and iv) when a defective memory unit is searched for among the memory units included in the target memory area, converting at least one of the first codewords stored in the target memory area into a second codeword having a second type and writing the converted second codeword to the memory medium.

In another aspect, embodiments of the present invention may provide a memory device including i) a memory medium including a plurality of memory units, and ii) a controller including a first error detection and correction circuit that detects an error bit position for a first type of codeword and performs error correction, and a second error detection and correction circuit that detects an error bit position for a second type of codeword and performs error correction. At this time, the controller may set a plurality of memory areas each including at least one of the plurality of memory units, store at least one first codeword having a first type in a first memory area among the plurality of memory areas, store at least one second codeword having a second type in a second memory area among the plurality of memory areas, perform error correction for the first codewords through the first error detection and correction circuit, perform error correction for the second codewords through the second error detection and correction circuit, and determine at least one of the memory units included in the second memory area as a defective memory unit.

According to embodiments of the present invention, error correction capability for areas where defects are likely to occur can be improved.

FIG. 1 is a drawing showing an example of the structure of a memory device according to embodiments of the present invention.
FIG. 2 is a flowchart illustrating an example of the operation of a memory device according to embodiments of the present invention.
FIG. 3 is a diagram illustrating an example of an operation of a memory device according to embodiments of the present invention to write a second codeword.
FIG. 4 is a flowchart illustrating an example of an operation of a memory device according to embodiments of the present invention to determine whether a memory unit is a defective memory unit.
FIG. 5 is a diagram illustrating an example of an operation of a memory device according to embodiments of the present invention to generate a second codeword.
FIG. 6 is a diagram illustrating an example of an operation of a memory device according to embodiments of the present invention in which a second codeword is overwritten at a location where K first codewords are stored.
FIG. 7 is a diagram illustrating another example of an operation of a memory device according to embodiments of the present invention to generate a second codeword.
FIG. 8 is a drawing showing another example of the structure of a memory device according to embodiments of the present invention.
FIG. 9 is a diagram illustrating an example of an operation in which a memory device according to embodiments of the present invention performs error correction on a codeword stored in a target memory area.
FIG. 10 is a diagram illustrating another example of an operation in which a memory device according to embodiments of the present invention performs error correction on a codeword stored in a target memory area.
FIG. 11 is a diagram illustrating an operation of a memory device according to embodiments of the present invention to determine the type of a codeword based on a table.
FIG. 12 is a drawing showing another example of the structure of a memory device according to embodiments of the present invention.
FIG. 13 is a diagram illustrating an operating method of a memory device according to embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a drawing showing an example of the structure of a memory device (100) according to embodiments of the present invention.

Referring to FIG. 1, a memory device (100) may include memory media (110) and a controller (120).

The memory media (110) may include a plurality of memory units (VMUs). Each of the plurality of memory units (VMUs) may store data.

The controller (120) can set a plurality of memory areas (MEM_AREA) for the memory media (110). Each of the plurality of memory areas (MEM_AREA) can include one or more of a plurality of memory units (VMU).

The controller (120) can store a codeword in a plurality of memory areas (MEM_AREA). The codeword can include data of a set first unit size (e.g. 64 bytes) and parity of a second unit size (e.g. 16 bytes). The data included in the codeword can be composed of one or more symbols.

Depending on the type of codeword, the error correction capability for the codeword may vary. For example, if the codeword includes 18 parities, 9 symbol errors occurring at random locations in the codeword or 18 symbol errors occurring at specified locations can be corrected.

In embodiments of the present invention, the controller (120) may store one or more first codewords (CW1) in a target memory area (TGT_MEM_AREA) among a plurality of memory areas (MEM_AREA). The first codeword is a codeword having a first type (TYPE_1).

In FIG. 1, one first codeword (CW1) may be distributed and stored in memory units (VMU) included in a target memory area (TGT_MEM_AREA). However, one first codeword (CW1) does not necessarily have to be distributed in memory units (VMU) included in the target memory area (TGT_MEM_AREA), and one first codeword (CW1) may be stored in one memory unit.

In embodiments of the present invention, the controller (120) may change the type of a codeword stored in the target memory area (TGT_MEM_AREA) in order to improve error correction performance for the target memory area (TGT_MEM_AREA). This will be described in detail below in FIG. 2.

The controller (120) can exchange various command signals and data signals with the memory media (110) to execute the aforementioned operations.

Meanwhile, the aforementioned memory media (110) can be implemented in various ways.

For example, the memory media (110) may be implemented as a dynamic random access memory media including a plurality of banks. The memory media (110) may store data in the plurality of banks and read data stored in the plurality of banks.

The memory media (110) can perform periodic refresh operations to maintain stored data. If the power supply to the memory media (110) is cut off, the data stored in the memory media (110) is lost.

Each of the multiple banks may include multiple matrices. In this case, each of the memory units (VMUs) may be composed of one bank, multiple matrices, or one matrix.

As another example, the memory media (110) may be implemented as a dynamic random access memory media including a plurality of chips. Each of the plurality of chips included in the memory media (110) may include a plurality of banks, and each of the plurality of banks may include a plurality of matrices. In this case, each of the memory units (VMUs) may be configured as one chip, one bank, a plurality of matrices, or one matrix.

As another example, the memory media (110) may be implemented as non-volatile memory media (e.g. NAND flash). In this case, each of the memory units (VMUs) may be composed of a die, a plane, or a memory block included in the memory media (110).

Meanwhile, the controller (120) can also be implemented in various ways.

For example, the controller (120) may be implemented as an integrated circuit including logic gates for executing the above-described operations. The controller (120) may be implemented as an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or the like.

As another example, the controller (120) may include a processor that performs operations to control operations that process a plurality of operation requests and a working memory that can store data necessary to process the plurality of operation requests.

In this case, the processor can control the operation of the controller (120) by executing the firmware. The processor can drive the firmware to control the overall operation of the controller (120) and perform logical operations. The firmware is a program that is executed within the controller (120) to drive the controller (120), and can include binary data in which the code for executing the aforementioned overall operation and logical operations is defined.

The firmware may be stored in a storage space (e.g. working memory, ROM, flash) located inside or outside the controller (120). The processor may load all or part of the firmware stored in the storage space.

The working memory may store data (e.g., multiple operation requests, firmware) required for the controller (120) to process multiple operation requests. As an example, the working memory may include a separate volatile memory (e.g., SRAM).

FIG. 2 is a flowchart showing an example of the operation of a memory device (100) according to embodiments of the present invention.

Referring to FIG. 2, the controller (120) of the memory device (100) can search for a defective memory unit among the memory units (VMU) included in the aforementioned target memory area (TGT_MEM_AREA) (S210).

A defective memory unit may be defined as a memory unit in which an error may occur in a stored codeword due to factors such as a physical defect. The controller (120) may distinguish memory units (VMUs) into defective memory units and normal memory units.

And the controller (120) can determine whether a defective memory unit has been detected among the memory units (VMU) included in the target memory area (TGT_MEM_AREA) (S220). To this end, the controller (120) can determine whether each of the memory units included in the target memory area (TGT_MEM_AREA) is a defective memory unit. This will be described in detail in FIG. 4 below.

When it is determined that a defective memory unit exists among the memory units (VMU) included in the target memory area (TGT_MEM_AREA) (S220-Y), the controller (120) may convert one or more of the first codewords stored in the target memory area (TGT_MEM_AREA) into one second codeword (S230) and write the converted second codeword to the memory media (110) (S240). This will be described in detail below with reference to FIG. 3.

At this time, the second codeword may have a second type. That is, the controller (120) may convert the type of the codeword stored in the target memory area (TGT_MEM_AREA) from the first type to the second type.

In this case, a second codeword of the second type may be stored in a target memory area (TGT_MEM_AREA) among a plurality of memory areas (MEM_AREA), and a first codeword of the first type may be stored in the remaining memory areas excluding the target memory area (TGT_MEM_AREA).

On the other hand, when it is determined that there is no defective memory unit among the memory units (VMU) included in the target memory area (TGT_MEM_AREA) (S220-N), the controller (120) can maintain the first codewords stored in the target memory area (TGT_MEM_AREA) as is without converting them (S250).

FIG. 3 is a diagram showing an example of an operation of a memory device (100) according to embodiments of the present invention to write a second codeword (CW2).

Referring to FIG. 3, the controller (120) of the memory device (100) can write a second codeword (CW2) having a second type (TYPE_2) to a target memory area (TGT_MEM_AREA).

At this time, the second codeword (CW2) can be distributed and stored in memory units (VMU) included in the target memory area (TGT_MEM_AREA) similar to the first codeword (CW1) described above.

In FIG. 3, the second codeword (CW2) is stored in the target memory area (TGT_MEM_AREA) among the multiple memory areas (MEM_AREA) as an example, but the location in the memory media (110) where the second codeword (CW2) is stored is not necessarily limited to the target memory area (TGT_MEM_AREA).

For example, the controller (120) may store the second codeword (CW2) in a memory area other than the target memory area (TGT_MEM_AREA) among the multiple memory areas (MEM_AREA).

FIG. 4 is a flowchart illustrating an example of an operation of a memory device (100) according to embodiments of the present invention to determine whether a memory unit is a defective memory unit.

Referring to FIG. 4, the controller (120) of the memory device (100) can calculate the row address fail count and the column address fail count of the corresponding memory unit (S410).

The row address fail count may be determined by the number of rows in which a fail occurred in the corresponding memory unit, and the column address fail count may be determined by the number of columns in which a fail occurred in the corresponding memory unit. The controller (120) may calculate the row address fail count and the column address fail count based on accumulated error information for the corresponding memory unit.

And the controller (120) determines whether the row address fail count of the memory unit is greater than or equal to the first threshold value (S420).

When the row address fail count is greater than or equal to the first threshold value (S420-Y), the controller (120) determines whether the column address fail count of the memory unit is greater than or equal to the second threshold value (S430).

When the column address fail count is greater than or equal to the second threshold value (S430-Y), the controller (120) can determine the corresponding memory unit as a defective memory unit (S440).

On the other hand, when the row address fail count of the memory unit is less than the first threshold value (S420-N) or the column address fail count is less than the second threshold value (S430-N), the controller (120) can determine the memory unit as a normal memory unit in which no defect has occurred (S450).

Below, a specific method in which the memory device (100) converts one or more first codewords (CW1) into one second codeword (CW2) is described.

FIG. 5 is a diagram illustrating an example of an operation in which a memory device (100) according to embodiments of the present invention generates a second codeword (CW2).

Referring to FIG. 5, the controller (120) of the memory device (100) can merge K (K is a natural number greater than or equal to 2) of the first codewords (CW1) stored in the target memory area (TGT_MEM_AREA) and convert them into one second codeword (CW2). At this time, the size of the second codeword (CW2) can be K times the size of the first codeword.

For example, when the first codeword is composed of 64 bytes of data and 16 bits of parity, the controller (120) can merge two first codewords to generate one second codeword composed of 128 bytes of data and 32 bits of parity.

When merging K first codewords into one second codeword (CW2), the controller (120) can read the K first codewords from the target memory area (TGT_MEM_AREA), generate one merged data based on the data stored in the K first codewords, and reconstruct parity for the merged data. Then, the controller (120) can generate a second codeword (CW2) based on the merged data and the parity for the merged data, and write the generated second codeword (CW2) to the memory media (110).

The second codeword (CW2) has a larger parity size than the first codeword (CW1), so it has a higher error correction capability. Accordingly, even if a part of the second codeword (CW2) is stored in a defective memory unit, the controller (120) can correct an error that occurred in the second codeword (CW2) with a higher probability through an error detection and correction circuit. Through this, the error correction capability for a target memory area (TGT_MEM_AREA) with a high possibility of defect occurrence, including a defective memory unit, can be improved.

Below, the location where the converted second codeword (CW2) is written is described.

FIG. 6 is a diagram illustrating an example of an operation of a memory device (100) according to embodiments of the present invention in which a second codeword (CW1) is overwritten at a location where K first codewords (CW1) are stored.

Referring to FIG. 6, the controller (120) can overwrite the second codeword (CW2) in the location where the merged K first codewords (CW1) are stored in the target memory area (TGT_MEM_AREA).

In Fig. 6, the K first codewords (CW1) are distributed and stored in the area between offset A and offset B in the target memory area (TGT_MEM_AREA).

At this time, the controller (120) can overwrite the second codeword (CW2) generated by merging the K first codewords (CW1) between offset A and offset B, which are the locations where the K first codewords (CW1) are stored.

FIG. 7 is a diagram showing another example of an operation in which a memory device (100) generates a second codeword (CW1) according to embodiments of the present invention.

Referring to FIG. 7, the controller (120) of the memory device (100) may perform at least one of an operation of reducing the size per symbol to increase the total number of symbols, an operation of removing a cyclic redundancy check (CRC), and an operation of increasing the size of parity for one or more of the first codewords (CW1) stored in the target memory area (TGT_MEM_AREA), thereby converting them into a second codeword (CW2).

FIG. 8 is a drawing showing another example of the structure of a memory device (100) according to embodiments of the present invention.

Referring to FIG. 8, the controller (120) of the memory device (100) may additionally include a first error detection and correction circuit (ECC_1) and a second error detection and correction circuit (ECC_2).

The first error detection and correction circuit (ECC_1) is a circuit that detects the error bit location for the codeword of the first type (TYPE_1) described above and performs error correction.

The second error detection and correction circuit (ECC_2) is a circuit that detects the error bit location of the second type (TYPE_2) described above and performs error correction.

The first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) can be implemented to decode data for a codeword input as an error correction code, and can be implemented as various code decoders. For example, a decoder that performs non-systematic code decoding or a decoder that performs systematic code decoding can be used.

The first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) can calculate a bit error rate (BER) for data and determine whether errors in the input data can be corrected.

The first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) can determine the corresponding data as uncorrectable (or Fail) if, for example, the bit error rate (BER) is higher than a set reference value. On the other hand, the data can be determined as correctable (or Pass) if the bit error rate (BER) is lower than the reference value.

The first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) can output error-corrected data if the error is correctable.

In embodiments of the present invention, the error correction capabilities of the first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) may be different from each other. That is, the first error detection and correction circuit (ECC_1) and the second error detection and correction circuit (ECC_2) may have different maximum error tolerant bit numbers.

In embodiments of the present invention, the controller (120) may determine an error detection and correction circuit used for error correction of a codeword differently depending on the type of the codeword. This will be described in detail in FIGS. 9 and 10 below.

FIG. 9 is a diagram illustrating an example of an operation in which a memory device (100) according to embodiments of the present invention performs error correction on a codeword stored in a target memory area (TGT_MEM_AREA).

Referring to FIG. 9, the controller (120) of the memory device (100) can perform error correction for the codeword through the first error detection and correction circuit (ECC_1) when the type of the codeword stored in the target memory area (TGT_MEM_AREA) is the first type (TYPE_1).

FIG. 10 is a diagram illustrating another example of an operation in which a memory device (100) according to embodiments of the present invention performs error correction on a codeword stored in a target memory area (TGT_MEM_AREA).

Referring to FIG. 10, the controller (120) of the memory device (100) can perform error correction for the codeword through the second error detection and correction circuit (ECC_2) when the type of the codeword stored in the target memory area (TGT_MEM_AREA) is the second type (TYPE_2).

FIG. 11 is a diagram illustrating an operation of a memory device (100) according to embodiments of the present invention to determine the type of a codeword based on a table.

Referring to FIG. 11, the controller (120) of the memory device (100) may additionally include a storage unit (SU) that stores mapping information indicating the type of a codeword mapped to each of a plurality of memory areas (MEM_AREA).

For example, a storage unit (SU) may be implemented as a separate register, volatile memory (e.g. SRAM), non-volatile memory (e.g. NAND Flash, NOR Flash, PRAM, MRAM), etc.

Mapping information can be implemented through various data structures such as tables, lists, arrays, and hashes. Mapping information can indicate an identifier (e.g. address, index) for identifying a specific memory area and the type of codeword mapped to the identifier.

When the controller (120) receives an identifier (ID) corresponding to a target memory area (TGT_MEM_AREA), it can search for the type of codeword mapped to the identifier in the mapping information.

And the controller (120) can determine the type of the searched codeword as the type of the codeword stored in the target memory area (TGT_MEM_AREA).

Above, the operation of changing the type of a codeword stored in a specific memory area among a plurality of memory areas (MEM_AREA) by the memory device (100) has been described.

When the type of a codeword stored in a specific memory area is changed in this way, the memory device (100) can store codewords having two different types. This will be described in detail below in FIG. 12.

FIG. 12 is a drawing showing another example of the structure of a memory device (100) according to embodiments of the present invention.

Referring to FIG. 12, similarly to FIG. 1, the memory media (110) of the memory device (100) may include a plurality of memory units (VMUs).

And the controller (120) of the memory device (100) may include a first error detection and correction circuit (ECC_1) and a second error detection and correction circuit (ECC_2) as in FIG. 8.

And the controller (120) can set multiple memory areas (MEM_AREA) as in Fig. 1.

The controller (120) can store one or more first codewords (CW1) having a first type (TYPE_1) in a first memory area (MEM_AREA_1) among a plurality of memory areas (MEM_AREA).

And the controller (120) can store one or more second codewords (CW2) having a second type (TYPE_2) in a second memory area (MEM_AREA_2) among a plurality of memory areas (MEM_AREA). At this time, the controller (120) can determine one or more of the memory units included in the second memory area (MEM_AREA_2) to be a defective memory unit.

FIG. 13 is a drawing showing an operating method of a memory device (100) according to embodiments of the present invention.

Referring to FIG. 13, the operating method of the memory device (100) may include a step (S1310) of setting a plurality of memory areas (MEM_AREA). Each of the plurality of memory areas (MEM_AREA) may include one or more of a plurality of memory units (VMU) included in the memory media (110).

And the operating method of the memory device (100) may include a step (S1320) of storing one or more first codewords (CW1) having a first type (TYPE_1) in a target memory area (TGT_MEM_AREA) among a plurality of memory areas (MEM_AREA).

And the operating method of the memory device (100) may include a step (S1330) of searching for a defective memory unit among the memory units (VMU) included in the target memory area (TGT_MEM_AREA).

For example, step S1330 may determine a memory unit (VMU) included in a target memory area (TGT_MEM_AREA) in which a row address fail count is greater than or equal to a first threshold value and a column address fail count is greater than or equal to a second threshold value as a defective memory unit.

And the operating method of the memory device (100) may include a step (S1340) of converting at least one of the first codewords (CW1) stored in the target memory area (TGT_MEM_AREA) into one second codeword (CW2) having a second type (TYPE_2) and writing the converted second codeword (CW2) to the memory media (110) when a defective memory unit is searched for among the memory units (VMU) included in the target memory area (TGT_MEM_AREA).

For example, step S1340 may convert K (K is a natural number greater than or equal to 2) of the first codewords (CW1) stored in the target memory area (TGT_MEM_AREA) into one second codeword (CW2). At this time, the size of the second codeword (CW2) may be K times the size of the first codeword. Step S1340 may overwrite the converted second codeword (CW2) in the location where the K first codewords (CW1) are stored in the target memory area (TGT_MEM_AREA).

As another example, step S1340 may perform at least one of an operation of increasing the total number of symbols by reducing the size per symbol, an operation of removing a CRC, and an operation of increasing the size of a parity for one or more of the first codewords (CW1) stored in the target memory area (TGT_MEM_AREA) to convert them into a second codeword (CW2).

Meanwhile, the operating method of the memory device (100) may additionally include a step of determining the type of a codeword stored in a target memory area (TGT_MEM_AREA), and a step of performing error correction on the codeword through a first error detection and correction circuit (ECC_1) when the type of the determined codeword is a first type (TYPE_1), and a step of performing error correction on the codeword through a second error detection and correction circuit (ECC_2) when the type of the determined codeword is a second type (TYPE_2).

At this time, the step of determining the type of the codeword stored in the target memory area (TGT_MEM_AREA) may include the steps of receiving an identifier corresponding to the target memory area, searching for the type of the codeword mapped to the identifier in mapping information indicating the type of the codeword mapped to each of the plurality of memory areas (MEM_AREA), and determining the type of the searched codeword as the type of the codeword stored in the target memory area (TGT_MEM_AREA).

The above description is merely an illustrative description of the technical idea of the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims (17)

A memory medium comprising a plurality of memory units; and
Setting up a plurality of memory areas, each of which includes at least one of the plurality of memory units,
A controller for storing codewords in the plurality of memory areas;
The above controller,
Store one or more first codewords having a first type in a target memory area among the plurality of memory areas,
Search for a defective memory unit among the memory units included in the above target memory area,
A memory device that converts one or more of the first codewords stored in the target memory area into one second codeword having a second type when a defective memory unit is detected among the memory units included in the target memory area, and writes the converted second codeword to the memory media.
In the first paragraph,
The above controller,
A memory device that determines a memory unit among the memory units included in the target memory area, in which a row address fail count is greater than or equal to a first threshold value and a column address fail count is greater than or equal to a second threshold value, as a defective memory unit.
In the first paragraph,
The above controller,
Among the first codewords stored in the above target memory area, K are merged and converted into one second codeword,
A memory device in which K is a natural number greater than or equal to 2.
In the third paragraph,
A memory device in which the size of the second codeword is K times the size of the first codeword.
In the third paragraph,
The above controller,
A memory device that overwrites the converted second codeword in the target memory area at a location where the merged K first codewords are stored.
In the first paragraph,
The above controller,
A memory device that converts one or more of the first codewords stored in the target memory area into the second codeword by performing at least one of an operation of reducing the size per symbol to increase the total number of symbols, an operation of removing a CRC, and an operation of increasing the size of a parity.
In the first paragraph,
It further comprises a first error detection and correction circuit for detecting an error bit position for the first type of codeword and performing error correction, and a second error detection and correction circuit for detecting an error bit position for the second type of codeword and performing error correction,
The above controller,
Determine the type of codeword stored in the above target memory area,
When the type of the codeword stored in the target memory area is the first type, error correction for the codeword is performed through the first error detection and correction circuit,
A memory device that performs error correction for the codeword through the second error detection and correction circuit when the type of the codeword stored in the target memory area is the second type.
In Article 7,
The above controller,
It further includes a storage unit that stores mapping information indicating the type of codeword mapped to each of the plurality of memory areas,
When receiving an identifier corresponding to the target memory area, the type of the codeword mapped to the identifier is searched for in the mapping information,
A memory device that determines the type of the searched codeword as the type of the codeword stored in the target memory area.
A step of setting up a plurality of memory areas, each of which includes at least one of a plurality of memory units included in a memory medium;
A step of storing one or more first codewords having a first type in a target memory area among the plurality of memory areas;
A step of searching for a defective memory unit among the memory units included in the target memory area; and
A method of operating a memory device, comprising: when a defective memory unit is detected among memory units included in the target memory area, converting at least one of the first codewords stored in the target memory area into a second codeword having a second type and writing the converted second codeword to the memory media.
In Article 9,
The steps for searching for the above bad memory unit are:
An operating method of a memory device, wherein a memory unit among memory units included in the target memory area, in which a row address fail count is greater than or equal to a first threshold value and a column address fail count is greater than or equal to a second threshold value, is determined to be a defective memory unit.
In Article 9,
The step of writing the second codeword to the volatile memory is:
Among the first codewords stored in the above target memory area, K are merged and converted into one second codeword,
An operating method of a memory device wherein the above K is a natural number greater than or equal to 2.
In Article 11,
A method of operating a memory device in which the size of the second codeword is K times the size of the first codeword.
In Article 11,
The step of writing the second codeword to the volatile memory is:
A method of operating a memory device for overwriting the second codeword in the target memory area at a location where the merged K first codewords are stored.
In Article 9,
The step of writing the second codeword to the volatile memory is:
An operating method of a memory device that converts one or more of the first codewords stored in the target memory area into the second codeword by performing at least one of an operation of reducing the size per symbol to increase the total number of symbols, an operation of removing a CRC, and an operation of increasing the size of a parity.
In Article 9,
A step of determining the type of codeword stored in the target memory area; and
A method of operating a memory device further comprising: a step of performing error correction on a codeword through a first error detection and correction circuit that detects an error bit position for a codeword of the first type and performs error correction when the type of the determined codeword is the first type; and a step of performing error correction on a codeword through a second error detection and correction circuit that detects an error bit position for a codeword of the second type and performs error correction when the type of the determined codeword is the second type.
In Article 15,
The step of determining the type of codeword stored in the above target memory area is:
A step of receiving an identifier corresponding to the target memory area;
A step of searching for the type of the codeword mapped to the identifier in mapping information indicating the type of the codeword mapped to each of the plurality of memory areas; and
A method of operating a memory device, comprising: a step of determining the type of the searched codeword as the type of the codeword stored in the target memory area.
A memory medium comprising a plurality of memory units; and
A controller including a first error detection and correction circuit for detecting an error bit position for a codeword of a first type and performing error correction, and a second error detection and correction circuit for detecting an error bit position for a codeword of a second type and performing error correction;
The above controller,
Setting up a plurality of memory areas, each of which includes at least one of the plurality of memory units,
Store one or more first codewords having a first type in a first memory area among the plurality of memory areas,
Store one or more second codewords having a second type in a second memory area among the plurality of memory areas,
Error correction for the above first codewords is performed through the above first error detection and correction circuit,
Error correction for the above second codewords is performed through the second error detection and correction circuit,
A memory device that determines one or more of the memory units included in the second memory area as a defective memory unit.

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