KR20230144470A - Semiconductor apparatus and semicondcutor system having independent data input/output period, and an operating method of the semiconductor system - Google Patents

Abstract

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device provides a chip enable signal and a command address signal set to the second semiconductor device, and the second semiconductor device performs an internal operation based on the chip enable signal and the command address signal. The first semiconductor device provides a selection chip enable command to the second semiconductor device, and after receiving the selection chip enable command, the second semiconductor device transmits data to the first semiconductor device or transmits data to the first semiconductor device. The data can be received from a semiconductor device.

Description

Semiconductor device and semiconductor system having independent data input/output sections, method of operating the semiconductor system {SEMICONDUCTOR APPARATUS AND SEMICONDCUTOR SYSTEM HAVING INDEPENDENT DATA INPUT/OUTPUT PERIOD, AND AN OPERATING METHOD OF THE SEMICONDUCTOR SYSTEM}

The present invention relates to integrated circuit technology, and more specifically to semiconductor devices and semiconductor systems having data input/output sections.

Electronic devices include many electronic components, and among them, computer systems may include many semiconductor devices made of semiconductors. Semiconductor devices constituting a computer system may include a processor or memory controller operating as a master device and a memory device or storage device operating as a slave device. The master device can provide a command address signal to the slave device, and the slave device can perform various operations based on the command address signal. Additionally, the master device and the slave device can transmit and receive data from each other.

In a NAND flash memory system, a NAND flash memory device can communicate with a memory controller through various interface methods. In the NAND interface method, command address signals and data can be transmitted through the same input/output bus. As the operating frequency of the NAND flash memory system increases, the command overhead of the NAND interface method increases, which may cause performance degradation of the memory system. The SCA (Serial Command Address) interface method allows command address signals and data to be transmitted through different input/output buses. Although the SCA interface method can partially reduce the command overhead, it is difficult for the operations of a plurality of NAND flash memory devices to be performed in parallel.

Embodiments of the present invention can provide a semiconductor device, a semiconductor system, and a method of operating the semiconductor system using a command address signal that defines an independent data input/output section.

A semiconductor system according to an embodiment of the present invention includes a first semiconductor device that provides a chip enable signal and a first command address signal set and then provides a second command address signal set defining a data input/output section; and a second semiconductor device that performs an internal operation based on the chip enable signal and the first command address signal set and is connected to the first semiconductor device through a data bus based on the second command address signal set. It can be included.

A method of operating a semiconductor system according to an embodiment of the present invention includes providing, by a first semiconductor device, one of a data input command and a data output command and a chip enable signal to the second semiconductor device; performing an internal operation based on the chip enable signal and the first command address signal set by a second semiconductor device; providing a select chip enable command to the second semiconductor device by the first semiconductor device; and transmitting the data to the second semiconductor device by the first semiconductor device, or transmitting the data to the first semiconductor device by the second semiconductor device.

A semiconductor system according to an embodiment of the present invention provides a first chip enable signal, a second chip enable signal, a first command address signal set, a second command address signal set, and a third command address signal set, and a data bus. a semiconductor device connected to; one memory die that performs an internal operation based on the first chip enable signal and the first command address signal set and is connected to the data bus based on the second command address signal set; and a second memory die that performs an internal operation based on the second chip enable signal and the first command address signal set and is connected to the data bus based on the third command address signal set. .

A method of operating a semiconductor system according to an embodiment of the present invention includes providing a first chip enable signal and a command address signal set to a first memory die by a semiconductor device; providing a first select chip enable command to the first memory die by the semiconductor device; receiving data from or transmitting the data to the first memory die by the semiconductor device; and providing one of a first selected chip disable command and a first selected chip end command to the first memory die by the semiconductor device.

Embodiments of the present invention can improve the performance of a semiconductor system by enabling interleaved operation of a plurality of dies.

1 is a diagram showing the configuration of a semiconductor system according to an embodiment of the present invention.
FIG. 2A is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
Figure 2b is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
FIG. 3A is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
Figure 3b is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
Figure 4 is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
5 is a diagram showing the operation of a semiconductor system according to an embodiment of the present invention.
Figure 6 is a diagram showing the configuration of a command address signal according to an embodiment of the present invention.
Figure 7 is a table showing a command address signal set according to an embodiment of the present invention.
FIG. 8A is a diagram illustrating the configuration of a select chip enable command according to an embodiment of the present invention.
FIG. 8B is a diagram illustrating the configuration of a select chip disable command according to an embodiment of the present invention.

1 is a diagram showing the configuration of a semiconductor system 1 according to an embodiment of the present invention. In FIG. 1 , the semiconductor system 1 may include a first semiconductor device 110 and a second semiconductor device 120 . The first semiconductor device 110 may provide various control signals used to operate the second semiconductor device 120. The first semiconductor device 110 may include various types of master devices. For example, the first semiconductor device 110 includes a central processing unit (CPU), a graphics processing unit (GPU), a multimedia processor (MMP), and a digital signal processor. , may be a host device such as an application processor (AP) and a memory controller. The second semiconductor device 120 may be a slave device that performs various operations under the control of the first semiconductor device 110, and may be, for example, a memory device. The memory device may include volatile memory and non-volatile memory. The volatile memory may include Static RAM (SRAM), Dynamic RAM (DRAM), and Synchronous DRAM (SDRAM), and the non-volatile memory may include Read Only Memory (ROM), Programmable ROM (PROM), and Electrically Erase and EEPROM (EEPROM). Programmable ROM), EPROM (Electrically Programmable ROM), flash memory, PRAM (Phase change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

The first semiconductor device 110 may be connected to the second semiconductor device 120 through a plurality of buses. The plurality of buses may be signal transmission paths, links, or channels for transmitting signals. The plurality of buses include a command address bus 101, a chip enable bus 102, a command clock bus 103, and a data bus 104. The command address bus 101, the chip enable bus 102, and the The clock command bus 103 may be a unidirectional bus from the first semiconductor device 110 to the second semiconductor device 120, and the data bus 104 may be a bidirectional bus. The first semiconductor device 110 may provide a command address signal (CA<0:1>) to the second semiconductor device 120 through the command address bus 101. The command address signal CA<0:1> transmitted by the first semiconductor device 110 may include a command signal and an address signal. The command signal may include command information specifying an operation performed by the second semiconductor device 120. The address signal ADD may include address information for accessing the storage area of the second semiconductor device 120. For example, the command signal may include a data input command, a data output command, a select chip enable command, and a select chip disable command. In one embodiment, the command signal may further include a select chip end command. The first semiconductor device 110 may transmit the 2-bit command address signal (CA<0:1>) per unit cycle to the second semiconductor device 120 through the command address bus 101. The command address signals (CA<0:1>) transmitted over a plurality of cycles may constitute one command address signal set. The first semiconductor device 110 may transmit a chip enable signal (CE#<0:1>) to the second semiconductor device 120 through the chip enable bus 102. In FIG. 1, the chip enable signal is shown as including 2 bits, but depending on the number of memory dies or memory chips included in the second semiconductor device 120, the chip enable signal (CE#<0 :1>) The number of bits may be changed. For example, when the second semiconductor device 110 includes two memory dies or memory chips, the first semiconductor device 120 generates a first chip enable signal (CE#<0>) and a second A chip enable signal (CE#<1>) may be provided to the second semiconductor device 120 through the chip enable bus 102. The first and second chip enable signals (CE#<0>, CE#<1>) may be provided together with the command address signal (CA<0:1>). For example, the first semiconductor device 110 uses the command address signal CA<0:1> and the first chip to operate the first memory die DIE1 of the second semiconductor device 120. An enable signal (CE#<0>) can also be provided. The first semiconductor device 110 uses the command address signal CA<0:1> and the second chip enable signal to operate the second memory die DIE2 of the second semiconductor device 120. CE#<1>) can also be transmitted.

The first semiconductor device 110 may provide a command clock signal (CCK) to the second semiconductor device 120 through the command clock bus 103. The command clock bus 103 is a signal that is synchronized with the command address signal (CA<0:1>), and the second semiconductor device 120 uses the command address signal (CA<0:1>) as a valid signal. It may be a signal that defines the receiving section. For example, during a period in which the command clock signal (CCK) toggles, the second semiconductor device 120 effectively validates the command address signal (CA<0:1>) transmitted from the first semiconductor device 110. The signal can be sampled. The first semiconductor device 110 provides data (DQ<0:7>) to the second semiconductor device 120 through the data bus 104 or receives the data (DQ<0:7>) from the second semiconductor device 120. DQ<0:7>) can be received. The operation of transmitting the data (DQ<0:7>) from the first semiconductor device 110 to the second semiconductor device 120 may be a data input operation, and the operation of transmitting the data (DQ<0:7>) from the second semiconductor device 120 The operation of transmitting the data (DQ<0:7>) to the first semiconductor device 110 may be a data output operation.

The first semiconductor device 110 may include a command address generation circuit 111 and a data input/output circuit 112. The command address generation circuit 111 may generate the command address signal (CA<0:1>) and the chip enable signal (CE#<0:1>) based on the user's request (REQ). . The command address generation circuit 111 transmits the command address signal (CA<0:1>) to the second semiconductor device 120 through the command address bus 101, and the chip enable bus 102 ) can be transmitted to the second semiconductor device 120 through the chip enable signal (CE#<0:1>). The command address generation circuit 111 transmits the command address signal (CA<0:1>) to the second semiconductor device 120 for a plurality of cycles according to the length and/or total number of bits of the command address signal set. Can be transmitted. The command address generation circuit 111 generates one of a first command address signal set, a second command address signal set, and a third command address signal set so that the second semiconductor device 120 can perform at least one specific operation. One can be transmitted sequentially. The first command address signal set may include a command that can specify the type of operation performed by the second semiconductor device 120. The second and third command address signal sets may define a data input/output section of the second semiconductor device 120. The command address generation circuit 111 may transmit the first command address signal set to the second semiconductor device 120 along with the chip enable signal (CE#<0:1>). The command address generation circuit 111 may not transmit the chip enable signal (CE#<0:1>) when transmitting the second and third command address signal sets to the second semiconductor device 120. there is. The second and third command address signal sets may each include selection information for selecting one of a plurality of memory dies included in the second semiconductor device 120.

The first command address signal set may include at least one of the data output command (CMD1) and the data input command (CMD2). In one embodiment, the data output command (CMD1) may be a random data output command. The random data output command changes the column address signal after the page read operation of the second semiconductor device 120 is performed and converts the data read from the second semiconductor device 120 to the data based on the changed column address signal. (DQ) may be a command signal instructing a transmission operation to the first semiconductor device 110. The data input command (CMD2) may be a random data input command. The random data input command transmits the data (DQ) to be used in the page program operation from the first semiconductor device 110 to the second semiconductor device before the page program operation of the second semiconductor device 120 is performed. It may be a command signal instructing an operation to be transmitted to (120).

When the second semiconductor device 120 includes the first and second memory dies (DIE1, DIE2), the second command address signal set includes at least a first select chip enable command (SCE1) and a first select It may include a chip disable command (SCD1). The third command address signal set may include at least a second select chip enable command (SCE2) and a second select chip disable command (SCD2). The first select chip enable command (SCE1) and the first select chip disable command (SCD1) are used to control the data input/output section of the first memory die (DIE1) and/or the data input/output section of the first memory die (DIE1). A section connected to the bus 104 can be defined. The second select chip enable command (SCE2) and the second select chip enable command (SCD2) are used to control the data input/output section of the second memory die (DIE2) and/or the data input/output section of the second memory die (DIE2). A section connected to the bus 104 can be defined. The data input/output section of the first memory die (DIE1) and the data input/output section of the second memory die (DIE2) may not overlap and may be set independently from each other. The command address generation circuit 111 generates the first and second select chip disable commands (SCD1 and SCD21) to prevent the data input/output sections of the first and second memory dies (DIE1 and DIE2) from overlapping. After one of the second and first selection chip enable commands (SCE2 and SCE1) is transmitted, one of the second and first selection chip enable commands (SCE2 and SCE1) may be transmitted. In one embodiment, the second command address signal set may further include a first selected chip end command, and the third command address signal set may further include a second selected chip end command. The first and second selected chip end commands may replace the first and second selected chip disable commands SCD1 and SCD2. The first and second selection chip end commands will be described later.

The data input/output circuit 112 is connected to the data bus 101 and can transmit and receive the data (DQ<0:7>) through the data bus 101. During the data output operation, the data input/output circuit 112 may receive the data (DQ<0:7>) transmitted from the second semiconductor device 120 and generate the internal data (DATA1). During the data input operation, the data input/output circuit 112 generates the data (DQ<0:7>) from the internal data (DATA1) and transmits the data (DQ<0:7>) to the second semiconductor. It can be transmitted to device 120. The data input/output circuit 112 generates the second semiconductor device 120 after the second command address signal set or the third command address signal set is transmitted by the command address generation circuit 111 during the data output operation. ) can receive the data (DQ<0:7>) from. The data input/output circuit 112 generates the second semiconductor device 120 after the second command address signal set or the third command address signal set is transmitted by the command address generation circuit 111 during the data input operation. ), the data (DQ<0:7>) can be transmitted.

The second semiconductor device 120 may include a plurality of memory dies. Each of the plurality of memory dies may perform data input/output operations independently from the first semiconductor device 110 . For example, the second semiconductor device 120 may include at least a first memory die (DIE1) and a second memory die (DIE2). The first memory die 121 and the second memory die 122 may have substantially the same configuration. The first and second memory dies DIE1 and DIE2 may include memory cell arrays 131 and 141, respectively. Each of the memory cell arrays 131 and 141 may include a plurality of planes. Each of the plurality of planes may include a plurality of blocks. One block may refer to a unit that can be erased at once. Each of the plurality of blocks may include a plurality of pages. The page may refer to a unit that can be programmed or read at one time. Each of the plurality of blocks is composed of the plurality of pages and the plurality of strings, and a plurality of memory cells may be connected to a point where the plurality of pages and the plurality of strings intersect. When a specific page among the plurality of pages and a specific string among the plurality of strings are selected, a memory cell connected between the selected page and the selected string may be accessed. Although not shown, the memory cell arrays 131 and 141 may include a row decoding circuit for selecting a specific page based on a row address signal and a column decoding circuit for selecting a specific string based on a column address signal. .

The first memory die DIE1 may include a control circuit 132, a data input/output circuit 133, and a page buffer group 134. The control circuit 132 is connected to the command address bus 101, the chip enable bus 102, and the command clock bus 103, and the command address bus 101 and the chip enable bus 102 ) and the command address signal (CA<0:1>), the chip enable signal (CE#<0:1>), and the command from the first semiconductor device 110 through the command clock bus 103. A clock signal (CCK) can be received. The control circuit 132 generates a memory cell array control signal based on the command address signal (CA<0:1>), the chip enable signal (CE#<0:1>), and the command clock signal (CCK). (MCS) and buffer control signal (BCS) can be generated. The control circuit 132 may provide the memory cell control signal (MCS) to the memory cell array 131 and the buffer control signal (BCS) to the page buffer group 134 . The control circuit 132 may receive the first chip enable signal (CE#<0>). The control circuit 132 generates the memory cell array control signal (MCS) based on the command address signal (CA<0:1>) received together with the first chip enable signal (CE#<0>) and The buffer control signal (BCS) can be generated. For example, the control circuit 132 controls the memory cell array control signal (MCS) and the memory cell array control signal (MCS) according to the first command address signal set when the first chip enable signal (CE#<0>) is enabled. A buffer control signal (BCS) can be generated. The control circuit 132 controls the memory cell array control signal (MCS) and the buffer control signal even if the first command address signal set is input when the first chip enable signal (CE#<0>) is disabled. (BCS) may not be generated. Although not limiting, the memory cell array control signal (MCS) may include a low voltage, the row address signal, the column address signal, etc. The low voltage may have various voltage levels depending on the type of operation performed by the first memory die DIE1. For example, the low voltage may include a plurality of program voltages, a plurality of verification voltages, a plurality of read voltages, an erase voltage, or a plurality of pass voltages. The low voltage may be applied to the page selected by the row address signal. The row address signal and the column address signal may be generated based on the address signal included in the command address signal (CA<0:1>). The buffer control signal BCS may include a plurality of control signals so that the page buffer group 134 can perform write and read operations on the memory cell array 131.

The control circuit 132 may generate a first data enable signal (EN#1) based on the command address signal (CA<0:1>). The control circuit 132 may provide the first data enable signal (EN#1) to the data input/output circuit 133. When receiving the second command address signal set, the control circuit 132 may enable the first data enable signal EN#1 based on the second command address signal set. The enable period of the first data enable signal EN#1 may be defined based on the second command address signal set. For example, the control circuit 132 enables the first data enable signal (EN#1) based on the first select chip enable signal (SCE1) and executes the first select chip disable command. The first data enable signal (EN#1) can be disabled based on (SCD1).

The data input/output circuit 133 may be connected to the data bus 104 and connected to the first semiconductor device 110 through the data bus 104. When the first memory die (DIE1) performs the data output operation based on the data output command (CMD1), the data input/output circuit 133 inputs the internal data (DATA21) of the first memory die (DIE1). can be received from the page buffer group 134. The data input/output circuit 133 generates the data (DQ<0:7>) based on the internal data (DATA21) of the first memory die (DIE1), and stores the data (DQ<0:7>). It can be transmitted to the first semiconductor device 110 through the data bus 104. When the first memory die (DIE1) performs the data input operation based on the data input command (CMD2), the data input/output circuit 133 inputs the first semiconductor device ( 110), the data (DQ<0:7>) transmitted from the device may be received, and internal data (DATA21) of the first memory die (DIE1) may be generated based on the data (DQ<0:7>). there is. The data input/output circuit 133 may provide internal data DATA21 of the first memory die DIE1 to the page buffer group 134. The data input/output circuit 133 serializes the internal data (DATA21) of the first memory die (DIE1) to generate the data (DQ<0:7>) or parallelizes the data (DQ<0:7>). Thus, it may include a serializer-desrializer (SERDES) that generates the internal data (DATA21). The data input/output circuit 133 may receive the first data enable signal (EN#1) from the control circuit 132. The data input/output circuit 133 may be selectively connected to the data bus 104 based on the first data enable signal (EN#1). For example, when the first data enable signal (EN#1) is enabled, the data input/output circuit 133 is connected to the data bus 104, and the first data enable signal (EN#1) is connected to the data bus 104. ) is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked.

The page buffer group 134 may receive the buffer control signal (BCS) from the control circuit 132 and be connected to the string selected by the column address signal. The page buffer group 134 includes the same number of page buffers as the plurality of strings provided in the memory cell array 210, and the plurality of page buffers may be connected one-to-one with the plurality of strings. The page buffer group 134 may set up the voltage levels of the plurality of strings based on the buffer control signal BCS. The page buffer group 134 reads data stored in the memory cell array 131 based on the buffer control signal BCS, and reads the internal data DATA21 of the first memory die DIE1 from the read data. ) can be created. The page buffer group 134 may write and/or program the internal data DATA21 of the first memory die DIE1 to the memory cell array 131 based on the buffer control signal BCS. .

When the first memory die DIE1 performs the data output operation based on the data output command CMD1, the page buffer group 134 operates the memory cell array based on the buffer control signal BCS. Data stored in 210 may be read, and the read data may be output as internal data (DATA21) of the first memory die (DIE1). The control circuit 132 may serialize the internal data (DATA21) and generate the data (DQ<0:7>). The data input/output circuit 133 transmits the data (DQ<0:7>) to the first semiconductor device (DQ<0:7>) through the data bus 104 when the first data enable signal (EN#1) is enabled. 110). When the first memory die DIE1 performs the data input operation based on the data input command CMD2, the page buffer group 134 stores the plurality of pages based on the buffer control signal BCS. The latch values of the latch circuits provided in the buffer can be initialized. When the first data enable signal EN#1 is enabled, the data input/output circuit 133 inputs the data (DQ< 0:7>), and the internal data (DATA21) can be generated by parallelizing the data (DQ<0:7>). The page buffer group 134 can set a latch value corresponding to the internal data (DATA21).

The second memory die DIE2 may include a control circuit 142, a data input/output circuit 143, and a page buffer group 144. The control circuit 142, the data input/output circuit 143, and the page buffer group 144 are the control circuit 132, the data input/output circuit 133, and the page buffer of the first memory die (DIE1). It may have substantially the same configuration as the group 134 and perform substantially the same function. Redundant descriptions of substantially the same functions performed by substantially the same components will be omitted. The control circuit 142 may receive the second chip enable signal (CE#<1>). The control circuit 142 generates the memory cell array control signal (MCS) based on the command address signal (CA<0:1>) received together with the second chip enable signal (CE#<1>) and The buffer control signal (BCS) can be generated. For example, the control circuit 142 controls the memory cell array control signal (MCS) and the memory cell array control signal (MCS) according to the first command address signal set when the second chip enable signal (CE#<1>) is enabled. A buffer control signal (BCS) can be generated. The control circuit 142 controls the memory cell array control signal (MCS) and the buffer control signal even if the first command address signal set is input when the second chip enable signal (CE#<1>) is disabled. (BCS) may not be generated.

The control circuit 142 may generate a second data enable signal (EN#2) based on the command address signal (CA<0:1>). The control circuit 142 may provide the second data enable signal (EN#2) to the data input/output circuit 143. When receiving the third command address signal set, the control circuit 142 may enable the second data enable signal EN#2 based on the third command address signal set. The enable period of the second data enable signal EN#2 may be defined based on the third command address signal set. For example, the control circuit 142 enables the second data enable signal (EN#2) based on the second select chip enable signal (SCE2) and sends the second select chip disable command. The second data enable signal (EN#2) can be disabled based on (SCD2).

The data input/output circuit 143 may be connected to the data bus 104 and connected to the first semiconductor device 110 through the data bus 104. When the second memory die (DIE2) performs the data output operation based on the data output command (CMD1), the data input/output circuit 143 inputs the internal data (DATA22) of the second memory die (DIE2). can be received from the page buffer group 144. The data input/output circuit 143 generates the data (DQ<0:7>) based on the internal data (DATA22) and transmits the data (DQ<0:7>) through the data bus 104. It can be transmitted to the first semiconductor device 110. When the second memory die (DIE2) performs the data input operation based on the data input command (CMD2), the data input/output circuit 143 inputs the first semiconductor device ( The data (DQ<0:7>) transmitted from 110) may be received, and the internal data (DATA22) may be generated based on the data (DQ<0:7>). The data input/output circuit 143 may provide the internal data (DATA22) to the page buffer group 144. The data input/output circuit 143 serializes the internal data (DATA22) to generate the data (DQ<0:7>) or parallelizes the data (DQ<0:7>) to generate the internal data (DATA22). It can include a serializer-deserializer (SERDES) that generates. The data input/output circuit 143 may receive the second data enable signal (EN#2) from the control circuit 142. The data input/output circuit 143 may be selectively connected to the data bus 104 based on the second data enable signal (EN#2). For example, when the second data enable signal (EN#2) is enabled, the data input/output circuit 143 is connected to the data bus 104, and the second data enable signal (EN#2) is connected to the data bus 104. ) is disabled, the connection between the data input/output circuit 143 and the data bus 104 may be blocked.

When the second memory die DIE2 performs the data output operation based on the data output command CMD1, the page buffer group 144 operates the memory cell array based on the buffer control signal BCS. Data stored in 141 may be read, and the read data may be output as the internal data DATA22 of the second memory die DIE2. The data input/output circuit 143 may serialize the internal data (DATA22) and generate the data (DQ<0:7>). The data input/output circuit 143 transmits the data (DQ<0:7>) to the first semiconductor device (DQ<0:7>) through the data bus 104 when the second data enable signal (EN#2) is enabled. 110). When the second memory die DIE2 performs the data input operation based on the data input command CMD1, the page buffer group 144 stores the plurality of pages based on the buffer control signal BCS. The latch values of the latch circuits provided in the buffer can be initialized. The data input/output circuit 143 receives the data (DQ<) transmitted from the first semiconductor device 110 through the data bus 104 when the second data enable signal EN#2 is enabled. 0:7>), and serialize the data (DQ<0:7>) to generate the internal data (DATA22). The page buffer group 144 can set a latch value corresponding to the internal data (DATA22).

FIG. 2A is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 2A may illustrate the data output operation performed by the first memory die DIE1 of FIG. 1. Referring to FIGS. 1 and 2A , the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data output operation. >) and the command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The first memory die (DIE1) receives the data output command (CMD1) as a valid command based on the enabled first chip enable signal (CE#<0>), and receives the data output command (CMD1) as a valid command. ), internal operations can be performed based on . The control circuit 132 of the first memory die (DIE1) generates the memory cell array control signal (MCS) and the buffer control signal (BCS) based on the data output command (CMD1), and the page buffer The group 134 may read data stored in the memory cell array 131 to generate internal data (DATA21) of the first memory die (DIE1). The data input/output circuit 133 may generate the data (DQ<0:7>, DOUT) by serializing the internal data (DATA21) of the first memory die (DIE).

The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then sends the second command address to the second semiconductor device 120. The command address signal (CA<0:7>) corresponding to the signal set may be provided to the second semiconductor device 120. When providing the second command address signal set, the first semiconductor device 110 may not provide the first chip enable signal (CE#<0>). The first semiconductor device 110 may maintain the first chip enable signal CE#<0> in a disabled state. The second command address signal set may include selection information for selecting the first memory die (DIE1) and includes a first select chip enable command (SCE1) and a first select chip disable command (SCD1). can do. The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal (EN#1) is enabled, the data input/output circuit 133 is connected to the data bus 104 and transmits the data (DOUT) to the data bus 104. It can be transmitted to the first semiconductor device 110. The first semiconductor device 110 may provide the first select chip enable command (SCE1) and then provide the first select chip disable command (SCD1) to the second semiconductor device 120. In one embodiment, the first semiconductor device 110 sends the first selection chip disable command (SCD1) to the second semiconductor device at the time when the transmission of the data (DOUT) from the second semiconductor device 120 is completed. It can be provided by device 120. In one embodiment, the first semiconductor device 110 provides the first selection chip enable command (SCE1) and sends the first selection chip disable command (SCD1) to the second semiconductor device when a predetermined time has elapsed. It can be provided by device 120. The control circuit 132 may disable the first data enable signal (EN#1) based on the first select chip disable command (SCD1). When the first data enable signal EN#1 is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked.

FIG. 2B is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 2B may illustrate the data input operation performed by the first memory die DIE1 of FIG. 1. Referring to FIGS. 1 and 2B, the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data input operation. >) and the command address signal (CA<0:7>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data input command (CMD2). The first memory die (DIE1) receives the data input command (CMD2) as a valid command based on the enabled first chip enable signal (CE#<0>), and receives the data input command (CMD2) as a valid command. ), internal operations can be performed based on . The control circuit 132 of the first memory die (DIE1) generates the memory cell array control signal (MCS) and the buffer control signal (BCS) based on the data input command (CMD2), and the page buffer Group 134 may initialize latch values of the latch circuits.

The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then sends the second command address to the second semiconductor device 120. The command address signal (CA<0:1>) corresponding to the signal set may be provided to the second semiconductor device 120. When providing the second command address signal set, the first semiconductor device 110 may not provide the first chip enable signal (CE#<0>). The first semiconductor device 110 may maintain the first chip enable signal CE#<0> in a disabled state. The second command address signal set may include selection information for selecting the first memory die (DIE1) and includes a first select chip enable command (SCE1) and a first select chip disable command (SCD1). can do. The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal EN#1 is enabled, the data input/output circuit 133 may be connected to the data bus 104. After providing the first select chip enable command (SCE1), the first semiconductor device 110 transmits the data (DQ<0:7>, DIN) to the second semiconductor device through the data bus 104. It can be provided by device 120. The data input/output circuit 133 receives the data (DIN) through the data bus 104 and parallelizes the data (DIN) to generate internal data (DATA21) of the first memory die (DIE1). You can. The data input/output circuit 133 may provide the internal data (DATA22) to the page buffer group 134. The first semiconductor device 110 may provide the first select chip disable command (SCE1) to the second semiconductor device 120 after providing the data (DIN). In one embodiment, the first semiconductor device 110 sends the first selection chip disable command (SCD1) to the second semiconductor device at the time when the transmission of the data (DIN) to the second semiconductor device 120 is completed. It can be provided by device 120. In one embodiment, the first semiconductor device 110 provides the first selection chip enable command (SCE1) and sends the first selection chip disable command (SCD1) to the second semiconductor device when a predetermined time has elapsed. It can be provided by device 120. The control circuit 132 may disable the first data enable signal (EN#1) based on the first select chip disable command (SCD1). When the first data enable signal EN#1 is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked.

FIG. 3A is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 3A shows the first and second memory dies DIE1 and DIE2 of FIG. 1 performing an interleaved data output operation. Referring to FIGS. 1 and 3A , the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data output operation. >) and the command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The first memory die (DIE1) receives the data output command (CMD1) as a valid command based on the enabled first chip enable signal (CE#<0>), and receives the data output command (CMD1) as a valid command. ), internal operations can be performed based on . The control circuit 132 of the first memory die (DIE1) generates the memory cell array control signal (MCS) and the buffer control signal (BCS) based on the data output command (CMD1), and the page buffer The group 134 may read data stored in the memory cell array 131 to generate internal data (DATA21) of the first memory die (DIE1). The data input/output circuit 133 may generate the data (DQ<0:7>) by serializing the internal data (DATA21).

The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then sends the second command address to the second semiconductor device 120. The command address signal (CA<0:1>) corresponding to the signal set may be provided to the second semiconductor device 120. When providing the second command address signal set, the first semiconductor device 110 may not provide the first chip enable signal (CE#<0>). The first semiconductor device 110 may maintain the first chip enable signal CE#<0> in a disabled state. The second command address signal set may include selection information for selecting the first memory die (DIE1) and includes a first select chip enable command (SCE1) and a first select chip disable command (SCD1). can do. The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal (EN#1) is enabled, the data input/output circuit 133 is connected to the data bus 104 and transmits the data (DQ<0:7>, DOUT1) to the data. It can be transmitted to the first semiconductor device 110 through the bus 104.

The first semiconductor device 110 uses the first chip enable signal (CE#<0>) and the first command address to perform the data output operation of the second memory die (DIE2) in parallel. After providing a set of signals to the second semiconductor device 120, the second chip enable signal (CE#<1>) instructs the second memory die (DIE2) to perform the data output operation, and The command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The second memory die (DIE2) receives the data output command (CMD1) as a valid command based on the enabled second chip enable signal (CE#<1>), and receives the data output command (CMD1) as a valid command. ), internal operations can be performed based on . In FIG. 3A, the second chip enable signal (CE#<1>) and the data output command (CMD1) are illustrated as being transmitted later than the first selection chip enable command (SCE1). 1 The point at which the semiconductor device 110 provides the second chip enable signal (CE#<1>) and the data output command (CMD1) to the second semiconductor device 120 is when the first semiconductor device 110 ) may be earlier or later than the time of providing the first selection chip enable command (SCE1). The point at which the second chip enable signal (CE#<1>) and the data output command (CMD1) are transmitted from the first semiconductor device 110 to the second semiconductor device 120 is the second semiconductor device ( 120) may overlap with the time point at which the data (DQ<0:7>) is transmitted to the first semiconductor device 110 through the data bus 104. Since the second chip enable signal (CE#<1>) is enabled when the data output command (CMD1) is transmitted, the first memory die (DIE1) receives the data output command (CMD1) as a valid command. You may not receive it. Additionally, the second memory die DIE2 may not be connected to the data bus 104.

The first semiconductor device 110 may provide the first select chip enable command (SCE1) and then provide the first select chip disable command (SCD1) to the second semiconductor device 120. The control circuit 132 may disable the first data enable signal (EN#1) based on the first select chip disable command (SCD1). When the first data enable signal EN#1 is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked.

After providing the first selection chip disable command (SCD1), the first semiconductor device 110 sends the command address signal (CA<0:1>) corresponding to the third command address signal set to the second semiconductor device. It can be provided by device 120. When providing the third command address signal set, the first semiconductor device 110 may not provide the second chip enable signal CE#<1>. The third command address signal set may include selection information for selecting the second memory die (DIE2) and includes a second select chip enable command (SCE2) and a second select chip disable command (SCD2). can do. The first semiconductor device 110 provides the first selection chip enable command (SCE2) to the second semiconductor device 120 and then sends the second selection chip enable command (SCD2) to the second semiconductor device 120. It can be provided by device 120. The control circuit 142 of the second die DIE2 may enable the second data enable signal EN#2 based on the second select chip enable command SCE2. When the second data enable signal (EN#2) is enabled, the data input/output circuit 143 is connected to the data bus 104 and transmits the data (DQ<0:7>, DOUT2) to the data. It can be transmitted to the first semiconductor device 110 through the bus 104.

The first semiconductor device 110 may provide the second select chip enable command (SCE2) and then provide the second select chip disable command (SCD2) to the second semiconductor device 120. The control circuit 142 may disable the second data enable signal (EN#2) based on the second select chip disable command (SCD2). When the second data enable signal EN#2 is disabled, the connection between the data input/output circuit 143 and the data bus 104 may be blocked. The first semiconductor device 110 sends the first and second select chip enable commands (SCE1, SCE2) and the first and second select chip disable commands (SCD1, SCD2) to the second semiconductor device 120. ) can be provided to independently set the data output section of the first and second memory dies (DIE1, DIE2), so that the first and second memory dies (DIE1, DIE2) perform the data output operation in parallel. It can make it possible to carry out.

FIG. 3B is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 3B shows the first and second memory dies DIE1 and DIE2 of FIG. 1 performing an interleaved data input operation. 1 and 3B, the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data input operation. >) and the command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data input command (CMD2). The first memory die (DIE1) receives the data input command (CMD2) as a valid command based on the enabled first chip enable signal (CE#<0>), and receives the data input command (CMD2) as a valid command. ), internal operations can be performed based on . The control circuit 132 of the first memory die (DIE1) generates the memory cell array control signal (MCS) and the buffer control signal (BCS) based on the data input command (CMD2), and the page buffer Group 134 may initialize latch values of the latch circuits.

The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then sends the second command address to the second semiconductor device 120. The command address signal (CA<0:1>) corresponding to the signal set may be provided to the second semiconductor device 120. When providing the second command address signal set, the first semiconductor device 110 may maintain the first chip enable signal CE#<0> in a disabled state. The second command address signal set may include selection information for selecting the first memory die (DIE1) and includes a first select chip enable command (SCE1) and a first select chip disable command (SCD1). can do. The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal EN#1 is enabled, the data input/output circuit 133 may be connected to the data bus 104. The first semiconductor device 110 provides the first select chip enable command (SCE1) to the second semiconductor device 120 and then sends the data (DQ<0:7>, DIN1) to the second semiconductor device. It can be provided by device 120. The data input/output circuit 133 receives the data (DIN1) through the data bus 104 and parallelizes the data (DIN1) to generate internal data (DATA21) of the first memory die (DIE1). You can.

The first semiconductor device 110 uses the first chip enable signal (CE#<0>) and the first command address to perform the data input operation of the second memory die (DIE2) in parallel. After providing a set of signals to the second semiconductor device 120, the second chip enable signal (CE#<1>) instructs the second memory die (DIE2) to perform the data input operation, and The command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data input command (CMD2). The second memory die (DIE2) receives the data input command (CMD2) as a valid command based on the enabled second chip enable signal (CE#<1>), and receives the data input command (CMD2) as a valid command. ), internal operations can be performed based on . In FIG. 3B, the second chip enable signal (CE#<1>) and the data input command (CMD2) are illustrated as being transmitted later than the first selection chip enable command (SCE1). 1 The point at which the semiconductor device 110 provides the second chip enable signal (CE#<1>) and the data input command (CMD2) to the second semiconductor device 120 is when the first semiconductor device 110 ) may be earlier or later than the time of providing the first selection chip enable command (SCE1). The point at which the second chip enable signal (CE#<1>) and the data input command (CMD2) are transmitted from the first semiconductor device 110 to the second semiconductor device 120 is the time when the first semiconductor device ( 110) may overlap with the time of transmitting the data (DIN1) to the second semiconductor device 120 through the data bus 104. Since the second chip enable signal (CE#<1>) is enabled when the data input command (CMD2) is transmitted, the first memory die (DIE1) receives the data input command (CMD2) as a valid command. You may not receive it. Additionally, since the second memory die DIE2 is not connected to the data bus 104, it may not receive the data DIN1 transmitted from the first semiconductor device 110.

The first semiconductor device 110 may provide the first select chip disable command (SCD1) to the second semiconductor device 120 after providing the data (DIN1) to the second semiconductor device. The control circuit 132 may disable the first data enable signal (EN#1) based on the first select chip disable command (SCD1). When the first data enable signal EN#1 is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked.

After providing the first selection chip disable command (SCD1), the first semiconductor device 110 sends the command address signal (CA<0:1>) corresponding to the third command address signal set to the second semiconductor device. It can be provided by device 120. When providing the third command address signal set, the first semiconductor device 110 may maintain the second chip enable signal CE#<1> in a disabled state. The third command address signal set may include selection information for selecting the second memory die (DIE2) and includes a second select chip enable command (SCE2) and a second select chip disable command (SCD2). can do. The first semiconductor device 110 provides the second selection chip enable command (SCE2) to the second semiconductor device 120 and then sends the second selection chip disable command (SCD2) to the second semiconductor device 120. It can be provided by device 120. The control circuit 142 may enable the second data enable signal EN#2 based on the second select chip enable command SCE2. When the second data enable signal EN#2 is enabled, the data input/output circuit 143 may be connected to the data bus 104.

After providing the second select chip enable command (SCE2) to the second semiconductor device 120, the first semiconductor device 110 sends the data (DQ<0:7>, DIN2) to the second semiconductor device 120. It can be provided as a semiconductor device 120. The data input/output circuit 144 receives the data (DIN2) through the data bus 104, parallelizes the data (DIN2), and generates internal data (DATA22) of the second memory die (DIE2). You can. The first semiconductor device 110 may provide the second select chip disable command (SCD2) to the second semiconductor device 120 after providing the data (DIN2). The control circuit 142 may disable the second data enable signal (EN#2) based on the second select chip disable command (SCD2). When the second data enable signal EN#2 is disabled, the connection between the data input/output circuit 143 and the data bus 104 may be blocked. The first semiconductor device 110 sends the first and second select chip enable commands (SCE1, SCE2) and the first and second select chip disable commands (SCD1, SCD2) to the second semiconductor device 120. ) can be provided to independently set the data input section of the first and second memory dies (DIE1, DIE2), so that the first and second memory dies (DIE1, DIE2) perform the data input operation in parallel. It can make it possible to carry out.

FIG. 4 is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 4 may illustrate the first memory die DIE1 of FIG. 1 performing the data output operation. Referring to FIGS. 1 and 4 , the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data output operation. >) and the command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The control circuit 132 of the first memory die DIE1 receives the data output command CMD1 as a valid command based on the enabled first chip enable signal CE#<0>, Internal operations can be performed based on the data output command (CMD1). The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set, and then sends the second command address signal set to the second semiconductor device ( 120). When providing the second command address signal set, the first semiconductor device 110 may maintain the first chip enable signal CE#<0> in a disabled state. The second command address signal set may include selection information for selecting the first memory die (DIE1), and may include a first select chip enable command (SCE1) and a first select chip end command (SCT1). You can. The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the data output command (CMD1) to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal (EN#1) is enabled, the data input/output circuit 133 is connected to the data bus 104 and transmits the data (DQ<0:7>, DOUT) to the data. It can be transmitted to the first semiconductor device 110 through the bus 104. The first semiconductor device 110 may provide the first selected chip end command (SCT1) to the second semiconductor device 120 after providing the first selected chip enable command (SCE1). The first semiconductor device 110 performs the second operation of FIG. 2A when the first memory die DIE1 does not need to perform another operation other than the data output operation indicated by the data output command CMD1. Instead of the first selection chip disable command (SCD1), the first selection chip termination command (SCT1) may be provided to the second semiconductor device 120. In one embodiment, the first semiconductor device 110 sends the first selection chip end command (SCT1) at the time when the transmission of the data (DOUT) from the second semiconductor device 120 is completed. It can be provided as (120). In one embodiment, the first semiconductor device 110 provides the first selection chip enable command (SCE1) and sends the first selection chip end command (SCT1) to the second semiconductor device when a predetermined time has elapsed. It can be provided as (120). The control circuit 132 may disable the first data enable signal (EN#1) based on the first selected chip end command (SCT1). When the first data enable signal EN#1 is disabled, the connection between the data input/output circuit 133 and the data bus 104 may be blocked. Additionally, the first memory die DIE1 may enter a low power mode based on the first select chip end command SCT1. The low power mode may be a standby mode that does not perform normal operation, and may include a power down mode, deep power down mode, sleep mode, etc. In FIG. 2A, when the first semiconductor device 110 provides the first select chip disable command (SCD1), the first memory die (DIE1) is in the ready state rather than the low power mode, and the first memory die (DIE1) is in the ready state instead of the low power mode. 1 Die (DIE1) can remain activated to perform another operation. When the first memory die (DIE1) does not need to perform another operation, the first semiconductor device 110 typically provides a low-power mode entry command to place the first memory die (DIE1) in the low-power mode. It is necessary to enter. The first semiconductor device 110 provides the first select chip termination command (SCT1) to disconnect the first memory die 110 and the data bus 104 and disconnects the first memory die 110 from the data bus 104. DIE1) may indicate entry into the low power entry mode. Accordingly, the number of commands and command overhead used for the first memory die DIE1 to enter the low power mode can be reduced, and the performance of the semiconductor system 100 can be improved.

Figure 5 is a diagram showing the operation of the semiconductor system 100 according to an embodiment of the present invention. FIG. 5 may illustrate that the first and second memory dies DIE1 and DIE2 of FIG. 1 perform an interleaved data output operation. Referring to FIGS. 1 and 5 , the first semiconductor device 110 sends the first chip enable signal (CE#<0) to indicate that the first memory die (DIE1) performs the data output operation. >) and the command address signal (CA<0:1>) corresponding to the first command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The first memory die (DIE1) receives the data output command (CMD1) as a valid command based on the enabled first chip enable signal (CE#<0>), and receives the data output command (CMD1) as a valid command. ), internal operations can be performed based on .

The first semiconductor device 110 provides the first chip enable signal (CE#<0>) and the first command address signal set to the second semiconductor device 120, and then selects the first chip. An enable command (SCE1) may be provided to the second semiconductor device 120. The control circuit 132 may enable the first data enable signal (EN#1) based on the first select chip enable command (SCE1). When the first data enable signal (EN#1) is enabled, the data input/output circuit 133 is connected to the data bus 104 and transmits the data (DQ<0:7>, DOUT1) to the data. It can be transmitted to the first semiconductor device 110 through the bus 104.

The first semiconductor device 110 uses the first chip enable signal (CE#<0>) and the first command address to perform the data output operation of the second memory die (DIE2) in parallel. After providing a signal set to the second semiconductor device, the second chip enable signal (CE#<1>) and the first chip enable signal (CE#<1>) instructing the second memory die (DIE2) to perform the data output operation. The command address signal (CA<0:7>) corresponding to the command address signal set may be provided to the second semiconductor device 120. The first command address signal set may include the data output command (CMD1). The second memory die (DIE2) receives the data output command (CMD1) as a valid command based on the enabled second chip enable signal (CE#<1>), and receives the data output command (CMD1) as a valid command. ), internal operations can be performed based on .

The first semiconductor device 110 may provide the first select chip enable command (SCE1) and then provide the first select chip disable command (SCD1) to the second semiconductor device 120. The control circuit 132 may disable the first data enable signal (EN#1) based on the first select chip disable command (SCD1). When the first data enable signal (EN#1) is disabled, the connection between the data input/output circuit 133 and the data bus 104 is cut off, and the first memory die (DIE1) performs another operation. It can be in a ready state that can perform. In one embodiment, when the first memory die (DIE1) does not need to perform another operation, the first semiconductor device 110 sends the first select chip disable command (SCD1) in FIG. 4 instead of the first select chip disable command (SCD1). The illustrated first selection chip end command (SCT1) may be provided to the second semiconductor device 120 . When the first selected chip end command (SCT1) is provided from the first semiconductor device 110, the first memory die (DIE1) may enter a low power mode.

The first semiconductor device 110 may provide the first select chip disable command (SCD1) and then provide the second select chip enable command (SCE2) to the second semiconductor device 120. . The control circuit 142 may enable the second data enable signal EN#2 based on the second select chip enable command SCE2. When the second data enable signal (EN#2) is enabled, the data input/output circuit 143 is connected to the data bus 104 and transmits the data (DQ<0:7>, DOUT2) to the data. It can be transmitted to the first semiconductor device 110 through the bus 104.

The first semiconductor device 110 may provide the second select chip enable command (SCE2) and then provide the second select chip end command (SCT2) to the second semiconductor device 120. The control circuit 142 may disable the second data enable signal (EN#2) based on the second selection chip end command (SCT2). When the second data enable signal EN#2 is disabled, the connection between the data input/output circuit 143 and the data bus 104 may be blocked. Additionally, the second memory die DIE2 may enter the low power mode based on the second select chip end command SCT2. In one embodiment, when the second memory die (DIE2) needs to perform another operation, the first semiconductor device 110 sends the second select chip termination command (SCT2) instead of the second memory die (DIE2) shown in FIG. 3A. The second selection chip disable command (SCD2) may be provided to the second semiconductor device 120. When the second select chip disable command (SCD2) is provided from the first semiconductor device 110, the second memory die (DIE2) is in a ready state in which another operation can be performed without entering the low power mode. It can be.

Figure 6 is a diagram showing the configuration of command address signals (CA<0>, CA<1>) according to an embodiment of the present invention. Referring to FIG. 6, the command address signals (CA<0>, CA<1>) transmitted during a unit cycle may include 2 bits, and a total of 12 bits of command address signals transmitted during 6 unit cycles may be One command address signal set can be configured. The first header and the second header of the command address signal set may be transmitted in the first unit cycle (UC1) and the second unit cycle (UC2). During the first unit cycle (UC1), the first and second bits (CA<0>, CA<1>) of the first header may be transmitted, and during the second unit cycle (UC2), the second bits (CA<0>, CA<1>) of the first header may be transmitted. The first and second bits (CA<0>, CA<1>) of the header may be transmitted. The first body, second body, third body and A fourth body may be transmitted. The first and second bits (CA<0>, CA<1>) of the first body may be transmitted during the third unit cycle (US3), and the second body may be transmitted during the fourth unit cycle (UC4) The first and second bits (CA<0>, CA<1>) may be transmitted. The first and second bits (CA<0>, CA<1>) of the third body may be transmitted during the fifth unit cycle (UC5), and the fourth bits (CA<0>, CA<1>) may be transmitted during the sixth unit cycle (UC6). The first and second bits (CA<0>, CA<1>) of the body may be transmitted. The command address signal set may be transmitted in synchronization with the command clock signal (CCK). The command address signals CA<0> and CA<1> may be transmitted in synchronization with the rising edge and falling edge of the command clock signal CCK. For example, the first unit cycle (UC1) may be synchronized to the first rising edge of the command clock signal (CCK), and the first and second bits (CA<0>, CA) of the first header <1>) may be transmitted in synchronization with the first rising edge of the command clock signal (CCK). The second unit cycle (UC2) may be synchronized to the first falling edge of the command clock signal (CCK), and the first and second bits (CA<0>, CA<1>) of the second header may be transmitted in synchronization with the first falling edge of the command clock signal (CCK). The third unit cycle (UC3) may be synchronized to the second rising edge of the command clock signal (CCK), and the first and second bits (CA<0>, CA<1>) of the first body are It may be transmitted in synchronization with the second rising edge of the command clock signal (CCK). The fourth unit cycle (UC4) may be synchronized with the second falling edge of the command clock signal (CCK), and the second The first and second bits (CA<0>, CA<1>) of the body may be transmitted in synchronization with the second falling edge of the command clock signal (CCK). The fifth unit cycle (UC5) is It may be synchronized to the third rising edge of the command clock signal (CCK), and the first and second bits (CA<0>, CA<1>) of the third body are of the command clock signal (CCK). The sixth unit cycle UC6 may be synchronized to the third falling edge of the command clock signal CCK, and the first and second bits of the fourth body may be transmitted in synchronization with the third rising edge. CA<0>, CA<1> may be transmitted in synchronization with the third falling edge of the command clock signal CCK.

Figure 7 is a table showing a command address signal set according to an embodiment of the present invention. Referring to FIG. 7, the command address signal set specifies the characteristics and/or type of the command address signal set according to the logic levels of the bits (CA<0>, CA<1>) of the first and second headers. can do. When the first and second bits (CA<0>, CA<1>) of the first header and the second header are at a low logic level, the command address signal set may correspond to a data output command (Data Output). there is. The first and second bits (CA<0>, CA<1>) of the first header are all at a low logic level, the first bit (CA<0>) of the second header is at a low logic level, and the first bit (CA<0>) of the second header is at a low logic level. 2 When the second bit (CA<1>) of the header is at a high logic level, the command address signal set may correspond to the data input command (Data Input). The first bit (CA<0>) of the first header is at a high logic level, the second bit (CA<1>) of the first header is at a low logic level, and the first and second bits of the second header When (CA0>, CA<1>) are both low logic levels, the command address signal set may correspond to an address input, and the bodies transmitted after the first and second headers are converted to an address signal. can be provided. The first bit (CA<0>) of the first header is at a low logic level, the second bit (CA<1>) of the first header is at a high logic level, and the first and second bits of the second header are When (CA<0>, CA<1>) are both low logic levels, the command address signal set may correspond to a command input, and the bodies transmitted after the first and second headers are the The command address signal set may contain information about the type of command defined.

The first and second bits (CA<0>, CA<1>) of the first header are both at a high logic level, the first bit (CA<0>) of the second header is at a high logic level, and the second bit (CA<0>) is at a high logic level. When the second bit (CA<1>) of the header is at a low logic level, the command address signal set may correspond to the select chip enable command (SCE). Bodies transmitted after the first and second headers may include selection information for selecting a memory die that receives the select chip enable command (SCE). The first and second bits (CA<0>, CA<1>) of the first header are all at a high logic level, the first bit (CA<0>) of the second header is at a low logic level, and the first bit (CA<0>) of the second header is at a low logic level. 2 When the second bit (CA<1>) of the header is at a high logic level, the command address signal set may correspond to the select chip disable command (SCD). Bodies transmitted after the first and second headers may include selection information for selecting a memory die that receives the select chip disable command (SCD). The first and second bits (CA<0>, CA<1>) of the first header and the first and second bits (CA<0>, CA<1>) of the second header are all high logic. When level, the command address signal set may correspond to the select chip end command (SCT). Bodies transmitted after the first and second headers may include selection information for selecting a memory die that receives the select chip termination command (SCT). The first and second bits (CA<0>, CA<1>) of the first header are all at high logic level, and the first and second bits (CA<0>, CA<1>) of the second header are at a high logic level. ) are all at a low logic level, the command address signal set may correspond to a LUN (Logical Unit Number) selection command (LUN Selection). Bodies transmitted after the first and second headers may include selection information for selecting a memory die that receives the LUN selection command (LUN Selection).

The first and second headers transmitted after the first and second headers of the selection chip enable command (SCE), the selection chip disable command (SCD), the selection chip end command (SCT), and the LUN selection command (LUN Selection) The first and second bits (CA<0>, CA<1>) of the first to fourth bodies may be used as information to select a plurality of memory dies. The first and second bits (CA<0>, CA<1>) of the first and fourth bodies can be used as information to select different memory dies, and are 256 by the logic values of the body bits. Different memory dies can be selected independently. For example, when the first bit of the first body to the second bit (S0, S1, S2, S3, S4, S5, S6, S7) of the fourth body are all low logic level, the first memory die can be selected The first bit (S0) of the first body is at a high logic level, and the second bits (S1, S2, S3, S4, S5, S6, S7) of the second to fourth bodies of the first body are all at low logic. When level, a second memory die may be selected. The second bit (S1) of the first body is at a high logic level, the first bit (S0) of the first body, the first bit of the second body to the second bits (S2, S3, S4, When S5, S6, and S7) are at a low logic level, a third memory die may be selected. When the first bit of the first body to the second bit (S0, S1, S2, S3, S4, S5, S6, S7) of the fourth body are all at a high logic level, the 256th memory die may be selected. . The control circuits 132 and 142 shown in FIG. 1 determine the logic levels of the header bits and body bits constituting the command address signal set and convert the command address signal set into the data output command (CMD1), The data input command (CMD2), the first selected chip enable command (SCE1), the first selected chip disable command (SCD1), the first selected chip end command (SCT1), and the second selected chip enable command It can be received as a command (SCE2), the second selected chip disable command (SCD2), and the second selected chip end command (SCT2).

FIG. 8A is a diagram illustrating the configuration of a select chip enable command according to an embodiment of the present invention. The first and second bits (CA<0>, CA<1>) of the first header of the command address signal set are both at high logic level, and the first bit (CA<0>) of the second header is at high logic level. level and the second bit (CA<1>) of the second header is at a low logic level, the command address signal set may correspond to the select chip enable command (SCE) of FIG. 7. Since all body bits are at a low logic level, the command address signal set may include selection information for selecting the first memory die (DIE1). Accordingly, the command address signal set may correspond to the first select chip enable command (SCE1) shown in FIGS. 2A to 5.

FIG. 8B is a diagram illustrating the configuration of a select chip disable command according to an embodiment of the present invention. The first and second bits (CA<0>, CA<1>) of the first header of the command address signal set are all at high logic level, and the first bit (CA<0>) of the second header is at low logic level. level and the second bit (CA<1>) of the second header is at a high logic level, the command address signal set may correspond to the select chip disable command (SCD) of FIG. 7. Since the first bit (CA<0>) of the first body is at a high logic level and all remaining body bits are at a low logic level, the command address signal set may include selection information for selecting the second memory die (DIE2). You can. Accordingly, the command address signal set may correspond to the second select chip disable command (SCD2) shown in FIGS. 3A, 3B, and 5.

Those skilled in the art to which the present invention pertains should understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features, and that the embodiments described above are illustrative in all respects and not restrictive. Just do it. The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

Claims (39)

A first semiconductor device that provides a chip enable signal and a first command address signal set and then provides a second command address signal set defining a data input/output section; and
A second semiconductor device performs an internal operation based on the chip enable signal and the first command address signal set, and is connected to the first semiconductor device through a data bus based on the second command address signal set. semiconductor system. According to claim 1,
The first command address signal set includes at least one of a data output command and a data input command. According to claim 1,
The second command address signal includes a select chip enable command,
The second semiconductor device is connected to the data bus based on the select chip enable command. According to claim 3,
The second command address signal further includes a select chip disable command,
A semiconductor system wherein the second semiconductor device is disconnected from the data bus based on the select chip disable command. According to claim 4,
The first semiconductor device provides the selection chip enable command to the second semiconductor device and then receives data from the second semiconductor device through the data bus, and after receiving the data, sends the selection chip disable command. A semiconductor system providing the second semiconductor device. According to claim 4,
The first semiconductor device provides data to the second semiconductor device through the data bus after providing the select chip enable command to the second semiconductor device, and provides the select chip disable command after the data is provided. A semiconductor system provided by the second semiconductor device. According to claim 1,
The second command address signal set includes a select chip enable command and a select chip end command,
A semiconductor system wherein the second semiconductor device is connected to the data bus based on the select chip enable command and enters a low power mode based on the select chip end command. According to claim 7,
The first semiconductor device transmits the selection chip enable command to the second semiconductor device, receives data from the second semiconductor device through the data bus, and sends the selection chip end command after the data is received. A semiconductor system provided by the second semiconductor device. According to claim 7,
The first semiconductor device provides the data to the second semiconductor device through the data bus after providing the selection chip enable command to the second semiconductor device, and provides the selection chip end command after the data is provided. A semiconductor system transmitting to the second semiconductor device. providing, by a first semiconductor device, one of a data input command and a data output command and a chip enable signal to the second semiconductor device;
performing an internal operation based on the chip enable signal and the first command address signal set by a second semiconductor device;
providing a select chip enable command to the second semiconductor device by the first semiconductor device; and
A method of operating a semiconductor system comprising transmitting data to the second semiconductor device by the first semiconductor device, or transmitting the data to the first semiconductor device by the second semiconductor device. According to claim 10,
A method of operating a semiconductor system wherein the second semiconductor device is connected to the first semiconductor device through a data bus based on the select chip enable command. According to claim 10,
After transmitting the data, providing a select chip disable command to the second semiconductor device by the first semiconductor device,
A method of operating a semiconductor system in which the second semiconductor device is disconnected from a data bus through which the data is transmitted based on the selection chip disable command. According to clause 9,
After the step of transmitting the data, providing a select chip end command to the second semiconductor device by the first semiconductor device,
A method of operating a semiconductor system in which the second semiconductor device enters a low power mode based on the selected chip end command. A semiconductor device that provides a first chip enable signal, a second chip enable signal, a first command address signal set, a second command address signal set, and a third command address signal set, and is connected to a data bus;
one memory die that performs an internal operation based on the first chip enable signal and the first command address signal set and is connected to the data bus based on the second command address signal set; and
A semiconductor system comprising a second memory die that performs an internal operation based on the second chip enable signal and the first command address signal set, and is connected to the data bus based on the third command address signal set. According to claim 14,
The first command address signal set includes at least one of a data input command and a data output command. According to claim 14,
the second command address signal set includes selection information for selecting the first memory die,
The third command address signal set includes selection information for selecting the second memory die. According to claim 14,
The second command address signal set includes a first select chip enable command and a first select chip disable command,
The semiconductor system wherein the first memory die is connected to the data bus based on the first select chip enable command and disconnected from the data bus based on the first select chip disable command. According to claim 17,
The third command address signal set includes a second select chip enable command and a second select chip disable command,
The semiconductor system wherein the second memory die is connected to the data bus based on the second select chip enable command and disconnected from the data bus based on the second select chip disable command. According to claim 17,
The semiconductor device provides the first chip enable signal and the first command address signal set and then provides the first selection chip enable command to the first memory die. According to claim 17,
The semiconductor device provides data to the first memory die through the data bus or receives the data from the first memory die and then provides the first selection chip disable command to the first memory die. . According to claim 18,
The semiconductor device provides the second chip enable signal and the first command address signal set and then provides the second chip select chip enable command to the second memory die. According to claim 18,
The semiconductor device provides data to the second memory die through the data bus or receives the data from the second memory die and then provides the second selection chip disable command to the second memory die. . According to claim 18,
The first semiconductor device provides the first chip enable signal and the first command address signal set to the first memory die and then provides the second chip enable signal and the first command address signal set to the second memory die. Semiconductor system provided by . According to claim 23,
The first semiconductor device provides the first select chip disable command to the first memory die and then provides the second select chip enable command to the second memory die. According to claim 14,
The second command address signal set includes a first select chip enable command and a first select chip end command,
The semiconductor system wherein the first memory die is connected to the data bus based on the first selected chip enable command and enters a low power mode based on the first selected chip end command. According to claim 25,
The third command address signal set includes a second select chip enable command and a second select chip end command,
The semiconductor system wherein the second memory die is connected to the data bus based on the second select chip enable command and enters the low power mode based on the second select chip end command. According to claim 14,
The first memory die includes a control circuit that generates a data enable signal based on the second command address signal set; and
A semiconductor system comprising a data input/output circuit connected to the data bus to transmit data to the semiconductor device or receive the data transmitted from the semiconductor device based on the data enable signal. According to clause 27,
The second command address signal set includes a first select chip enable command and a first select chip disable command,
The control circuit enables the data enable signal based on the first select chip enable command and disables the data enable signal based on the first select chip disable command. According to claim 14,
The second memory die includes a control circuit that generates a data enable signal based on the third command address signal set; and
A semiconductor system comprising a data input/output circuit connected to the data bus to transmit data to the semiconductor device or receive the data transmitted from the semiconductor device based on the data enable signal. According to clause 29,
The third command address signal set includes a second select chip enable command and a second select chip disable command,
The control circuit enables the data enable signal based on the second select chip enable command and disables the data enable signal based on the second select chip disable command. providing a first chip enable signal and a set of command address signals to a first memory die by a semiconductor device;
providing a first select chip enable command to the first memory die by the semiconductor device;
receiving data from or transmitting the data to the first memory die by the semiconductor device; and
A method of operating a semiconductor system comprising providing one of a first selected chip disable command and a first selected chip shutdown command to the first memory die by the semiconductor device. According to claim 31,
A method of operating a semiconductor system further comprising performing an internal operation by the first memory die after providing the first chip enable signal and the command address signal set. According to claim 31,
The first memory die is in a ready state based on the first select chip disable command,
A method of operating a semiconductor system entering a low power mode based on the first selected chip shutdown command. According to claim 31,
After providing the first chip enable signal and the command address signal set, the semiconductor device further includes providing a second chip enable signal and the command address signal set to a second memory die by the semiconductor device. How the system works. According to claim 34,
A method of operating a semiconductor system further comprising performing an internal operation by the second memory die after providing the second chip enable signal and the command address signal set. According to claim 34,
After providing one of the first select chip disable command and the first select chip shutdown command, providing a second select chip enable command to the second memory die by the semiconductor device. A method of operating a semiconductor system. According to claim 32,
After providing the second select chip enable command, operation of a semiconductor system comprising receiving the data from the second memory die or transmitting the data to the second memory die by the semiconductor device. method. According to clause 37,
After receiving data from or transmitting the data to the second memory die, providing a second select chip disable command to the second memory die by the semiconductor device. do,
A method of operating a semiconductor system in which the second memory die is in a ready state based on the second select chip disable command. According to clause 37,
After receiving the data from or transmitting the data to the second memory die, providing a second select chip termination command to the second memory die by the semiconductor device. do,
A method of operating a semiconductor system in which the second memory die enters a low power mode based on the second selected chip end command.

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