KR20220131815A - image sensor - Google Patents

Abstract

An image sensor is disclosed. The image sensor includes: a semiconductor substrate including first and second surfaces facing each other; a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface; a buried transfer gate electrode disposed in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate; a first gate electrode surrounding a sidewall of the semiconductor pattern and having a ring-shaped horizontal cross-section; and a color filter disposed on the second surface of the semiconductor substrate.

Description

Image sensors

The technical idea of the present invention relates to an image sensor, and more particularly, to an image sensor including a photodiode.

An image sensor is a device that converts an optical image signal into an electrical signal. The image sensor has a plurality of pixels, and each pixel receives incident light, converts it into an electric signal, and includes a photodiode region and a pixel circuit for outputting a pixel signal using electric charges generated in the photodiode region. As the degree of integration of the image sensor increases, the size of each pixel decreases and the size of each component of the pixel circuit also decreases, so that leakage current through the pixel circuit occurs, thereby degrading the quality of the image sensor.

An object of the present invention is to provide an image sensor having improved image quality by reducing read noise of a pixel circuit.

According to an aspect of the present invention, there is provided an image sensor, comprising: a semiconductor substrate including a first surface and a second surface facing each other; a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface; a buried transfer gate electrode disposed in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate; and a first gate electrode surrounding a sidewall of the semiconductor pattern and having a ring-shaped horizontal cross-section.

According to an aspect of the present invention, there is provided an image sensor, comprising: a semiconductor substrate including a first surface and a second surface facing each other; a buried transfer gate electrode disposed in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate; a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface; and a first gate electrode disposed on a sidewall of the semiconductor pattern, the main electrode extending in the first direction, and an extension connected to the main electrode and extending on the first surface of the semiconductor substrate; , a first gate electrode.

According to an aspect of the present invention, there is provided an image sensor, comprising: a semiconductor substrate including a first surface and a second surface facing each other; a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface; a device isolation layer provided on the first surface of the semiconductor substrate and defining an active region; a buried transfer gate electrode spaced apart from the semiconductor pattern in a second direction parallel to the first surface of the semiconductor substrate and arranged in a transfer gate trench extending into the semiconductor substrate; a first gate insulating layer surrounding a sidewall of the semiconductor pattern; a first gate electrode surrounding the sidewall of the semiconductor pattern on the first gate insulating layer and including a main electrode part having a ring-shaped horizontal cross-section; a first source/drain region disposed inside the semiconductor substrate under the semiconductor pattern; and a second source/drain region disposed above the semiconductor pattern.

According to the inventive concept, an image sensor may include a buried transfer gate electrode extending into the semiconductor substrate, a semiconductor pattern disposed on the upper surface of the semiconductor substrate, and a first gate electrode surrounding the sidewall of the semiconductor pattern. have. Since the first gate electrode constitutes a gate-around type transistor surrounding the sidewall of the semiconductor pattern, read noise of the pixel circuit may be reduced, and thus the image sensor may have excellent quality.

1 is a layout diagram illustrating an image sensor according to example embodiments.
FIG. 2 is an enlarged layout of a portion II of FIG. 1 .
3 is a cross-sectional view taken along lines A1-A1' and A2-A2' of FIG. 2;
4 is an enlarged view of a portion CX2 of FIG. 3 .
5A and 5B are layout views of a first gate electrode according to example embodiments.
6 is an equivalent circuit diagram of a pixel of an image sensor according to example embodiments.
7 is a layout diagram illustrating an image sensor according to example embodiments.
8 is a layout diagram illustrating an image sensor according to example embodiments.
9 is a cross-sectional view taken along lines A1-A1' and A2-A2' of FIG. 8 .
10 is a layout diagram illustrating an image sensor according to example embodiments.
11 is a layout diagram illustrating an image sensor according to example embodiments.
12 is a layout diagram illustrating an image sensor according to example embodiments.
13 is a layout diagram illustrating an image sensor according to example embodiments.
14 is a cross-sectional view taken along line A3-A3' of FIG. 13 .
15 is a layout diagram illustrating an image sensor according to example embodiments.
16 is a cross-sectional view illustrating an image sensor according to example embodiments.
17 is a cross-sectional view illustrating an image sensor according to example embodiments.
18 is a cross-sectional view illustrating an image sensor according to example embodiments.
19 is a schematic diagram illustrating an image sensor according to example embodiments.
Fig. 20 is a block diagram showing the configuration of an image sensor according to an exemplary embodiment.

Hereinafter, preferred embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings.

1 is a layout diagram illustrating an image sensor 100 according to example embodiments. FIG. 2 is an enlarged layout of a portion II of FIG. 1 . 3 is a cross-sectional view taken along lines A1-A1' and A2-A2' of FIG. 2; 4 is an enlarged view of a portion CX2 of FIG. 3 . 5A and 5B are layout views of the first gate electrode 150 according to example embodiments. 1 and 2 show only a partial configuration of the image sensor 100 for convenience.

1 to 5B , the image sensor 100 may include an active pixel region APR, a peripheral circuit region PCR, and a pad region PDR formed on a semiconductor substrate 110 .

The active pixel region APR may be disposed in a central portion of the semiconductor substrate 110 , and peripheral circuit regions PCR may be disposed on both sides of the active pixel region APR. A pad region PDR may be disposed at an edge portion of the semiconductor substrate 110 .

The active pixel region APR includes a plurality of pixels PX, and a plurality of photoelectric conversion regions 120 may be respectively disposed in the plurality of pixels PX. In the active pixel region APR, the plurality of pixels PX are arranged in a first direction X parallel to the top surface of the semiconductor substrate 110 and perpendicular to the first direction and parallel to the top surface of the semiconductor substrate 110 . It may be arranged in a matrix shape forming columns and rows along the second direction Y.

Although the peripheral circuit region PCR is exemplarily illustrated as being disposed on both sides of the active pixel region APR in a plan view, the present invention is not limited thereto, and the peripheral circuit region PCR may be disposed to surround the entire active pixel region APR. Alternatively, as shown in FIG. 19 , the peripheral circuit region PCR may be formed on another substrate and connected to the substrate on which the active pixel region APR is formed in a stack form. A conductive pad PAD may be disposed in the pad region PDR. The conductive pad PAD may be disposed on the edge portion of the semiconductor substrate 110 .

The semiconductor substrate 110 may include a first surface 110F1 and a second surface 110F2 opposite to each other. Here, for convenience, the surface of the semiconductor substrate 110 on which the color filter 186 is disposed is referred to as the second surface 110F2, and the surface opposite to the second surface 110F2 is referred to as the first surface 110F1. However, the technical spirit of the present invention is not limited thereto.

In example embodiments, the semiconductor substrate 110 may include a p-type semiconductor substrate. For example, the semiconductor substrate 110 may include any one of Si, Ge, SiGe, SiC, GaAs, InAs, and InP. For example, the semiconductor substrate 110 may be formed of a p-type silicon substrate. In example embodiments, the semiconductor substrate 110 may include a p-type bulk substrate and a p-type or n-type epitaxial layer grown thereon. In other embodiments, the semiconductor substrate 110 may include an n-type bulk substrate and a p-type or n-type epitaxial layer grown thereon. Alternatively, the semiconductor substrate 110 may be formed of an organic plastic substrate. A well region 114 may be disposed in the semiconductor substrate 110 adjacent to the first surface 110F1 of the semiconductor substrate 110 . The well region 114 may be a region doped with a p-type impurity.

A plurality of pixels PX may be arranged in a matrix in the semiconductor substrate 110 in the active pixel region APR. A plurality of photoelectric conversion regions 120 may be respectively disposed in the plurality of pixels PX. The plurality of photoelectric conversion regions 120 may be regions in which light incident from the second surface 110F2 of the semiconductor substrate 110 is converted into an electrical signal.

A pixel device isolation layer 130 may be disposed in the semiconductor substrate 110 in the active pixel region APR, and a plurality of pixels PX may be defined by the pixel device isolation layer 130 . The pixel device isolation layer 130 may be disposed between one of the plurality of photoelectric conversion regions 120 and the photoelectric conversion region 120 adjacent thereto. One photoelectric conversion region 120 and another photoelectric conversion region 120 adjacent thereto may be physically and electrically separated by the pixel device isolation layer 130 . The pixel device isolation layer 130 is disposed between each of the plurality of photoelectric conversion regions 120 arranged in a matrix form, and may have a grid or mesh shape in a plan view.

The pixel device isolation layer 130 may be formed in the pixel trench 130T passing through the semiconductor substrate 110 from the first surface 110F1 to the second surface 110F2 of the semiconductor substrate 110 . The pixel device isolation layer 130 includes an insulating layer 132 conformally formed on a sidewall of the pixel trench 130T, a conductive layer 134 filling the inside of the pixel trench 130T on the insulating layer 132, and an upper insulating layer. layer 136 . The upper insulating layer 136 may be disposed in a portion of the pixel trench 130T adjacent to the first surface 110F1 of the semiconductor substrate 110 . In example embodiments, the upper insulating layer 136 is formed by etching back a portion of the insulating layer 132 and the conductive layer 134 disposed at the entrance of the pixel trench 130T and filling the remaining space with an insulating material. can be

In example embodiments, the insulating layer 132 may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, or the like. In this case, the insulating layer 132 may act as a negative fixed charge layer, but the technical spirit of the present invention is not limited thereto. In other embodiments, the insulating layer 132 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The conductive layer 134 may include at least one of doped polysilicon, metal, metal silicide, metal nitride, or a metal-containing layer.

In FIG. 3 , the pixel device isolation layer 130 exemplarily extends from the first surface 110F1 to the second surface 110F2 of the semiconductor substrate 110 through the semiconductor substrate 110 , but in another embodiment 3 , the pixel device isolation layer 130 extends from the second surface 110F2 of the semiconductor substrate 110 toward the inside of the semiconductor substrate 110 and extends from the first surface of the semiconductor substrate 110 . It may not be exposed to (110F1). In this case, a barrier doped region (not shown) may be formed between the first surface 110F1 of the semiconductor substrate 110 and one end of the pixel device isolation layer 130 adjacent to the first surface 110F1, and the barrier The doped region may be a region doped with a high concentration of p-type impurities.

3 , a device isolation layer 112 defining an active region (not shown) may be formed on the first surface 110F1 of the semiconductor substrate 110 . The device isolation layer 112 is disposed in a device isolation trench (not shown) formed to a predetermined depth on the first surface 110F1 of the semiconductor substrate 110 and may include an insulating material. The device isolation layer 112 may be disposed to surround an upper sidewall of the pixel device isolation layer 130 (eg, a sidewall of the upper insulating layer 136 ).

Transistors constituting a pixel circuit (not shown) may be disposed on the active region. The active region may be a portion of the semiconductor substrate 110 having a transfer gate TG, a source follower gate SF, a selection gate SEL, and a reset gate RG disposed thereon. For example, the active region may include a ground region GND, a floating diffusion region FD, and a first source/drain region SD1 . The ground region GND, the floating diffusion region FD, and the first source/drain region SD1 may be disposed to be spaced apart from each other by the device isolation layer 112 .

In some example embodiments, as shown in FIG. 2 , the first pixel PX-1, the second pixel PX-2, the third pixel PX-3, and the fourth pixel PX- 4) may be disposed in a matrix shape, and the first pixel PX-1 and the third pixel PX-3 disposed side by side in the second direction Y may have a mirror-symmetric shape with each other. The first pixel PX-1 and the second pixel PX-2 arranged side by side in the direction X may have a mirror-symmetrical shape.

In some example embodiments, the first pixel PX-1 and the second pixel PX-2 may include a transfer gate TG and a source follower gate SF, and the third pixel PX- 3) may include a transfer gate TG and a reset gate RG, and the fourth pixel PX-4 may include a transfer gate TG and a selection gate SEL. However, the layout of the transistors illustrated in FIG. 2 corresponds to the layout of the transistors according to some embodiments, and the layout of the transistors or the shape of the active region ACT is not limited thereto.

In exemplary embodiments, the transfer gate TG may constitute a transfer transistor TX (see FIG. 6 ), and the transfer transistor TX transfers charges generated in the photoelectric conversion region 120 to the floating diffusion region ( FD). The reset gate RG may constitute a reset transistor RX (refer to FIG. 6 ), and the reset transistor RX may be configured to periodically reset charges stored in the floating diffusion region FD. The source follower gate SF may constitute a drive transistor DX (see FIG. 6 ), and the drive transistor DX serves as a source follower buffer amplifier and charges charged in the floating diffusion region. It may be configured to buffer a signal according to The selection gate SEL may constitute the selection transistor SX (refer to FIG. 6 ), and the selection transistor SX may serve as switching and addressing for selecting the pixel PX.

As exemplarily illustrated in FIG. 3 , the transfer gate TG may be referred to as a buried transfer gate electrode 140 , and the buried transfer gate electrode 140 is formed on the first surface 110F1 of the semiconductor substrate 110 . It may be disposed inside the transfer gate trench 140T extending from the inside of the semiconductor substrate 110 into the semiconductor substrate 110 . A transfer gate insulating layer 142 may be conformally disposed on the inner wall of the transfer gate trench 140T, and the buried transfer gate electrode 140 may fill the inside of the transfer gate trench 140T on the transfer gate insulating layer 142. have.

For example, the top surface of the buried transfer gate electrode 140 may be disposed at a level higher than the first surface 110F1 of the semiconductor substrate 110 , and the transfer gate spacer 144 is disposed on the sidewall of the buried transfer gate electrode 140 . ) can be placed.

In example embodiments, the buried transfer gate electrode 140 may include at least one of doped polysilicon, metal, metal silicide, metal nitride, or a metal-containing layer. The transfer gate insulating layer 142 may include silicon oxide or metal oxide, and the transfer gate spacer 144 may include silicon nitride, silicon oxynitride, or silicon oxide.

The reset gate RG, the source follower gate SF, and the selection gate SEL may be referred to as a first gate electrode 150 , and the first gate electrode 150 is formed on the first surface ( It may be disposed to surround the sidewall APS of the semiconductor pattern AP disposed on the 110F1 . The semiconductor pattern AP and the first gate electrode 150 surrounding the semiconductor pattern AP may constitute a gate-all-around type transistor.

The semiconductor pattern AP may extend along the vertical direction Z from the first surface 110F1 of the semiconductor substrate 110 . For example, the semiconductor pattern AP may include any one of Si, Ge, SiGe, SiC, GaAs, InAs, and InP.

In example embodiments, the semiconductor pattern AP may include a material layer epitaxially grown using the first surface 110F1 of the semiconductor substrate 110 as a seed layer. In other embodiments, the semiconductor pattern AP is a part of the semiconductor substrate 110 , and after forming a mask pattern (not shown) on the first surface 110F1 of the semiconductor substrate 110 , the semiconductor substrate 110 . may be formed by etching to a predetermined thickness, and may be a portion of the semiconductor substrate 110 remaining to protrude from the first surface of the semiconductor substrate 110 in the vertical direction (Z).

For example, the second surface 110F2 of the semiconductor substrate 110 is disposed at the first vertical level LV1 , and the first surface 110F1 of the semiconductor substrate 110 is disposed at the second vertical level LV2 . do. Based on the first vertical level LV1 , the upper surface of the semiconductor pattern AP may be disposed at a third vertical level LV3 higher than the second vertical level LV2 . For example, the distance from the top surface of the semiconductor pattern AP to the second surface 110F2 of the semiconductor substrate 110 is from the first surface 110F1 of the semiconductor substrate 110 to the second surface of the semiconductor substrate 110 . It may be greater than the distance to 110F2 (ie, the height of the semiconductor substrate 110 ).

As shown in FIG. 3 , the semiconductor pattern AP may have a first height h11 in the vertical direction Z, and the first height h11 may be in a range of about 10 to 500 nm, The present invention is not limited thereto.

In FIG. 3 , the semiconductor pattern AP has a sidewall APS perpendicular to the first surface 110F1 of the semiconductor substrate 110 and has a width in the first direction X substantially over the entire height h11. The same is illustrated by way of example. However, the slope of the sidewall of the semiconductor pattern AP may vary according to the formation process of the semiconductor pattern AP. For example, a mold layer (not shown) having an opening (not shown) is formed on the first surface 110F1 of the semiconductor substrate 110 , and a semiconductor pattern AP is formed in the mold layer by an epitaxial process. may be formed, and in this case, the width of the top surface of the semiconductor pattern AP may be greater than the width of the bottom surface of the semiconductor pattern AP. Conversely, when the semiconductor pattern AP is formed by etching a predetermined thickness from the first surface 110F1 of the semiconductor pattern AP, the width of the top surface of the semiconductor pattern AP is the width of the bottom surface of the semiconductor pattern AP. may be smaller than

In FIG. 2 , the semiconductor pattern AP is illustrated as having a substantially circular horizontal cross-section. However, in other embodiments, as shown in FIG. 5A , the semiconductor pattern AP may have an elliptical horizontal cross-section, and for example, a width along the first direction X may increase in the second direction Y. (or conversely, the width along the first direction (X) may be smaller than the width along the second direction (Y)). In other embodiments, as illustrated in FIG. 5B , the semiconductor pattern AP may have a rectangular horizontal cross-section, but the horizontal cross-sectional shape of the semiconductor pattern AP is not limited thereto.

The first gate electrode 150 may surround the sidewall APS of the semiconductor pattern AP on the first surface 110F1 of the semiconductor substrate 110 . For example, the first gate electrode 150 includes the main electrode part MP surrounding the sidewall APS of the semiconductor pattern AP, and the main electrode part MP extending in a horizontal direction from the semiconductor substrate 110 . It may include an extension EXP that is disposed on the first surface 110F1 of the . For example, the main electrode part MP may extend in the vertical direction Z from the sidewall APS of the semiconductor pattern AP to a fourth vertical level LV4 lower than the top surface of the semiconductor pattern AP. In a plan view, the main electrode part MP may have a ring shape, and may surround the entire sidewall APS of the main electrode part MP.

The extension EXP may be formed on the first surface 110F1 of the semiconductor substrate 110 to have a flat top level and to have a predetermined width. A contact 162 (eg, the second contact CA2 ) may be disposed on the extension part EXP, so that an electrical signal is applied to the first gate electrode 150 through the contact 162 . can be As the first gate electrode 150 includes the extension part EXP having a flat top surface extending from the main electrode part MP, a process defect for forming the contact 162 to the first gate electrode 150 may occur. can be prevented. In example embodiments, the upper surface of the extension EXP may be disposed at the same level as the upper surface of the buried transfer gate electrode 140 , but is not limited thereto.

The first gate insulating layer 152 may be interposed between the semiconductor pattern AP and the first gate electrode 150 and surround the sidewall APS of the semiconductor pattern AP. The first gate insulating layer 152 may extend from the sidewall APS of the semiconductor pattern AP to the first surface 110F1 of the semiconductor substrate 110 , but is not limited thereto. The first gate insulating layer 152 may be formed as a continuous material layer extending to the inside of the transfer gate trench 140T and connected to the transfer gate insulating layer 142 . Unlike this, the first gate insulating layer 152 may extend on the first surface 110F1 of the semiconductor substrate 110 but may not extend to the inside of the transfer gate trench 140T, and may be different from the transfer gate insulating layer 142 . It may be formed as a separate material layer.

The semiconductor pattern AP may be disposed on the first source/drain region SD1 , and an upper side of the semiconductor pattern AP may not be covered by the main electrode part MP, and A second source/drain region SD2 may be disposed on the upper side. The first source/drain region SD1 and the second source/drain region SD2 may be regions doped with a high concentration of impurities. For example, the semiconductor pattern AP, the main electrode part MP of the first gate electrode 150 , the first source/drain regions SD1 , and the second source/drain regions SD2 are gate-all- An around-type transistor can be configured.

In example embodiments, the first gate electrode 150 may include at least one of doped polysilicon, metal, metal silicide, metal nitride, or a metal-containing layer. The first gate insulating layer 152 may include, but is not limited to, silicon oxide or metal oxide.

A buried insulating layer 160 may be disposed on the first surface 110F1 of the semiconductor substrate 110 . The buried insulating layer 160 covers the ground region GND, the floating diffusion region FD, the device isolation layer 112 , the buried transfer gate electrode 140 , the semiconductor pattern AP, and the first gate electrode 150 . can do. The buried insulating layer 160 may be formed to have a sufficient height to cover the semiconductor pattern AP and the upper surfaces of the first gate electrode 150 .

In example embodiments, the buried insulating layer 160 may include silicon nitride or silicon oxynitride. In some examples, the buried insulating layer 160 may be formed in a stacked structure of a first insulating layer (not shown) and a second insulating layer (not shown). In other examples, an etch stop layer (not shown) may be interposed between the buried insulating layer 160 and the first surface 110F1 of the semiconductor substrate 110 , and the etch stop layer is the buried insulating layer 160 . It may include a material having an etch selectivity with respect to .

A contact 162 penetrating through the buried insulating layer 160 may be disposed on the first surface 110F1 of the semiconductor substrate 110 . For example, the contact 162 may pass through the buried insulating layer 160 to be electrically connected to the active region (not shown), the buried transfer gate electrode 140 , and the first gate electrode 150 . The contact 162 may include a first contact CA1 , a second contact CA2 , and a third contact CA3 .

The first contact CA1 may be disposed in the first contact hole CA1H passing through the buried insulating layer 160 . The first contact hole CA1H may expose a top surface of the first surface 110F1 of the semiconductor substrate 110 , for example, the ground region GND and the floating diffusion region FD. The first contact CA1 may fill the inside of the first contact hole CA1H and may be connected to the ground region GND and the floating diffusion region FD.

The second contact CA2 may be disposed in the second contact hole CA2H passing through the buried insulating layer 160 . The second contact hole CA2H may expose a top surface of the buried transfer gate electrode 140 and a top surface of the first gate electrode 150 . For example, the second contact hole CA2H may expose a top surface of the extension part EXP of the first gate electrode 150 . The second contact CA2 may fill the inside of the second contact hole CA2H and may be connected to the top surface of the buried transfer gate electrode 140 and the top surface of the extension part EXP of the first gate electrode 150 .

The third contact CA3 may be disposed in the third contact hole CA3H passing through the buried insulating layer 160 . The third contact hole CA3H may expose the top surface of the semiconductor pattern AP or the top surface of the second source/drain region SD2 . The third contact CA3 may fill the inside of the third contact hole CA3H and may be connected to the second source/drain region SD2 .

An upper wiring structure 170 may be disposed on the buried insulating layer 160 . The upper wiring structure 170 may be formed in a stacked structure of a plurality of layers. The upper wiring structure 170 may include a wiring layer 172 and an insulating layer 174 surrounding the wiring layer 172 . The wiring layer 172 may include at least one of polysilicon doped or undoped with impurities, metal, metal silicide, metal nitride, or a metal-containing layer. For example, the wiring layer 172 may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, or the like. The insulating layer 174 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

A rear insulating layer 182 may be disposed on the second surface 110F2 of the semiconductor substrate 110 . The back insulating layer 182 may be disposed on substantially the entire area of the second surface 110F2 of the semiconductor substrate 110 , and the back insulating layer 182 may be disposed on the second surface 110F2 of the semiconductor substrate 110 . It may be in contact with the upper surface of the pixel device isolation layer 130 disposed at the same level as . In example embodiments, the back insulating layer 182 may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, or the like. In other embodiments, the back insulating layer 182 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a low-k material.

A passivation layer 184 may be disposed on the rear insulating layer 182 , and a color filter 186 and a microlens 188 may be disposed on the passivation layer 184 . Optionally, a support substrate (not shown) may be further disposed on the first surface 110F1 of the semiconductor substrate 110 .

In general, pixel circuits such as a reset gate RG, a selection gate SEL, and a source follower gate SF disposed in the pixel PX are horizontally spaced apart from each other in the pixel. As the degree of integration of the image sensor increases, the size of the unit pixel decreases and the size of each component of the pixel circuit also decreases, so that leakage current through the pixel circuit or read noise of the pixel circuit occurs, and thus the image sensor There is a problem that the quality of

However, according to example embodiments, the semiconductor pattern AP may extend in the vertical direction Z and the first gate electrode 150 may have a gate-all-around structure surrounding the sidewall of the semiconductor pattern AP. can Accordingly, leakage current of pixel circuits such as the reset gate RG, the selection gate SEL, and the source follower gate SF may be reduced, and the occurrence of read noise may be prevented. Accordingly, the image sensor 100 may have excellent image quality. In addition, as the semiconductor pattern AP and the first gate electrode 150 extend in the vertical direction Z, the area of a unit pixel may be reduced, and the image sensor 100 may be miniaturized.

6 is an equivalent circuit diagram of a pixel PX of the image sensor 100 according to example embodiments.

Referring to FIG. 6 , the plurality of pixels PX may be arranged in a matrix form. Each of the plurality of pixels PX may include a transfer transistor TX and logic transistors. Here, the logic transistors may include a reset transistor RX, a selection transistor SX, and a drive transistor DX (or a source follower transistor). The reset transistor RX includes a reset gate RG, the selection transistor SX includes a selection gate SEL, the drive transistor DX includes a source follower gate SF, and the transfer transistor TX ) may include a transfer gate TG.

Each of the plurality of pixels PX may further include a photoelectric conversion element PD and a floating diffusion region FD. The photoelectric conversion device PD may correspond to the photoelectric conversion region 120 described with reference to FIGS. 1 to 4 . The photoelectric conversion device PD may generate and accumulate photocharges in proportion to the amount of externally incident light, and may include a photodiode, a phototransistor, a photogate, and a pinned photodiode (PPD). and combinations thereof may be used.

The transfer gate TG may transfer charges generated by the photoelectric conversion element to the floating diffusion region FD. The floating diffusion region FD may receive and accumulate charges generated by the photoelectric conversion device PD. The drive transistor DX may be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset charges accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX is connected to the floating diffusion region FD, and the source electrode is connected to the power supply voltage V _DD1 . When the reset transistor RX is turned on, the power voltage V _DD1 connected to the source electrode of the reset transistor RX is transferred to the floating diffusion region FD. When the reset transistor RX is turned on, charges accumulated in the floating diffusion region FD may be discharged to reset the floating diffusion region FD.

The drive transistor DX is connected to a current source (not shown) positioned outside the plurality of pixels PX to function as a source follower buffer amplifier, and amplifies a change in potential in the floating diffusion region FD. and output it to the output line (V _OUT ).

The selection transistor SX may select the plurality of pixels PX in a row unit, and when the selection transistor SX is turned on, the power voltage V _DD2 may be transferred to the source electrode of the drive transistor DX. .

7 is a layout diagram illustrating an image sensor 100A according to example embodiments. In Fig. 7, the same reference numerals as in Figs. 1 to 6 mean the same components.

Referring to FIG. 7 , the image sensor 100A may include a transmission gate TG having a dual gate structure. In FIG. 7 , a pair of buried transfer gate electrodes 140A may be included instead of the buried transfer gate electrode 140 (refer to FIG. 2 ), and the pair of buried transfer gate electrodes 140A are spaced apart from each other by a predetermined distance. It may be disposed adjacent to the floating diffusion region FD.

8 is a layout diagram illustrating an image sensor 100B according to example embodiments, and FIG. 9 is a cross-sectional view taken along lines A1-A1' and A2-A2' of FIG. 8 . In FIGS. 8 and 9 , the same reference numerals as in FIGS. 1 to 7 mean the same components.

Referring to FIG. 8 , the image sensor 100B may include a transmission gate TG having a ring-shaped gate structure. The transfer gate trench 140TB is disposed to surround the floating diffusion region FD, and may have a ring shape in a plan view. The buried transfer gate electrode 140B may be disposed in the transfer gate trench 140TB and may be disposed to surround the floating diffusion region FD.

In example embodiments, the buried transfer gate electrode 140B may include a main electrode part 140MP and an extension part 140EX, and the main electrode part 140MP is disposed in the transfer gate trench 140TB and is a top view. may have a ring shape. The extension portion 140EX may extend from the main electrode portion 140MP onto the first surface 110F1 of the semiconductor substrate 110 . A contact 162 (eg, a second contact CA2 ) may be disposed on the extension 140EX, and an electrical signal may be applied to the buried transfer gate electrode 140B through the contact 162 . .

In the process for forming the contact 162 to the buried transfer gate electrode 140B as the buried transfer gate electrode 140B includes the extended portion 140EX having a flat top surface extending from the main electrode portion 140MP. Defects can be prevented. In example embodiments, the upper surface of the extension 140EX may be disposed at the same level as the upper surface of the extension EXP of the first gate electrode 150 , but is not limited thereto.

According to example embodiments, as the buried transfer gate electrode 140B is disposed to surround the floating diffusion region FD, a charge transfer path follows a direction perpendicular to the first surface 110F1 of the semiconductor substrate 110 . can be formed. Accordingly, the sensitivity of the low-illuminance characteristic that may be easily deteriorated according to the shape of the buried transfer gate electrode 140B may be improved, and the image sensor 100B may have excellent quality.

10 is a layout diagram illustrating an image sensor 100C according to example embodiments. In Fig. 10, the same reference numerals as in Figs. 1 to 9 mean the same components.

Referring to FIG. 10 , the image sensor 100C may include two semiconductor patterns AP spaced apart from each other in each pixel PX-1, PX-2, PX-3, and PX-4, respectively. A first gate electrode 150C1 and a second gate electrode 150C2 may be disposed on a sidewall of the semiconductor pattern AP. For example, each of the first gate electrode 150C1 and the second gate electrode 150C2 may include a main electrode part MP and an extension part EXP.

In some examples, the first gate electrode 150C1 may be a source follower gate SF (see FIG. 6 ), and the second gate electrode 150C2 may be a selection gate SEL (see FIG. 6 ). In other examples, the first gate electrode 150C1 may be a reset gate RG (refer to FIG. 6 ), and the second gate electrode 150C2 may be a selection gate SEL. In still other examples, the first gate electrode 150C1 may be a reset gate RG, and the second gate electrode 150C2 may be a source follower gate SF.

10 , it is exemplarily illustrated that all of the first to fourth pixels PX-1, PX-2, PX-3, and PX-4 include a first gate electrode 150C1 and a second gate electrode 150C2. Although illustrated, unlike this, at least one of the first gate electrode 150C1 and the second gate electrode 150C2 in at least one of the first to fourth pixels PX-1, PX-2, PX-3, and PX-4. may be omitted.

11 is a layout diagram illustrating an image sensor 200 according to example embodiments. In Fig. 11, the same reference numerals as in Figs. 1 to 10 mean the same components.

Referring to FIG. 11 , in a plan view, the pixel isolation layer 130A may not be disposed to completely surround each of the pixels PX-1, PX-2, PX-3, and PX-4. A portion of the semiconductor substrate 110 in which the pixel device isolation layer 130A does not surround the pixels PX-1, PX-2, PX-3, and PX-4 may be referred to as a shared region 130XE. A ground area GNDA may be disposed in the shared area 130XE. For example, the ground area GNDA is shared by the first pixel PX-1 and the second pixel PX-2, or It may be shared by the third pixel PX-3 and the fourth pixel PX-4.

11 shows a buried transfer gate electrode 140B having a ring-shaped horizontal cross section, but instead of the buried transfer gate electrode 140B, a buried transfer gate electrode 140 (refer to FIGS. 1 to 4 ) or a buried transfer gate An electrode 140A (see FIG. 7 ) may be provided.

12 is a layout diagram illustrating an image sensor 200A according to example embodiments. In Fig. 12, the same reference numerals as in Figs. 1 to 11 mean the same components.

Referring to FIG. 12 , in a plan view, the pixel isolation layer 130A may not be disposed to completely surround each of the pixels PX-1, PX-2, PX-3, and PX-4. A portion of the semiconductor substrate 110 in which the pixel device isolation layer 130A does not surround the pixels PX-1, PX-2, PX-3, and PX-4 may be referred to as a shared region 130XE. For example, each of the pixels PX-1, PX-2, PX-3, and PX-4 may be connected to two shared areas 130XE, and a ground area GNDA is provided in one shared area 130XE. A floating diffusion area FDA may be disposed in the other shared area 130XE.

For example, in the region of the semiconductor substrate 110 where the first pixel PX-1, the second pixel PX-2, the third pixel PX-3, and the fourth pixel PX-4 meet. A floating diffusion area FDA may be disposed, and floating in the first pixel PX-1, the second pixel PX-2, the third pixel PX-3, and the fourth pixel PX-4. A buried transfer gate electrode 140 may be disposed adjacent to the diffusion region FDA, respectively. The floating diffusion area FDA may be shared by the first pixel PX-1, the second pixel PX-2, the third pixel PX-3, and the fourth pixel PX-4.

13 is a layout diagram illustrating an image sensor 300 according to example embodiments, and FIG. 14 is a cross-sectional view taken along line A3-A3′ of FIG. 13 . 13 and 14, the same reference numerals as in FIGS. 1 to 11 mean the same components.

12 and 13 , the image sensor 300 may include pixels PX-1, PX-2, PX-3, and PX-4 for implementing an autofocus (AF) function. For example, the first to fourth pixels PX-1, PX-2, PX-3, and PX-4 may be covered by one microlens 188A.

The first to fourth pixels PX-1, PX-2, PX-3, and PX-4 may be phase detection pixels, and may generate phase signals used to calculate a phase difference between images. . The first to fourth pixels PX-1, PX-2, PX-3, and PX-4 may be used to focus on an object, and phase signals are positions of images formed on the image sensor 300 . may include information about , and the phase signals may be used to calculate phase differences between images. Based on the calculated phase differences, a focal position of a lens of the electronic device including the image sensor 300 may be calculated.

15 is a layout diagram illustrating an image sensor 300A according to example embodiments. In Fig. 15, the same reference numerals as in Figs. 1 to 14 mean the same components.

Referring to FIG. 15 , the image sensor 300A may include pixels PX-1 and PX-2 for implementing an autofocus (AF) function. The first pixel PX-1 may include a transfer gate TG and a reset gate RG, and the second pixel PX-2 may include a transfer gate TG and a selection gate SEL. In addition, the reset gate RG and the selection gate SEL may include the first gate electrode 150 . The first pixel PX-1 and the second pixel PX-2 may be covered by one microlens 188A.

In a plan view, in the pixel device isolation layer 130A, a shared area 130XE that does not completely surround the first pixel PX-1 and the second pixel PX-2 may be disposed, and the shared area 130XE is overlying in the shared area 130XE. A flow area 310 may be disposed. The overflow region 310 may be disposed in the semiconductor substrate 110 adjacent to the first surface 110F1 of the semiconductor substrate 110 , and among the first pixel PX-1 and the second pixel PX-2 . When the intensity of the photocharge incident on any one is relatively large, a path through which the photocharge may move to an adjacent pixel through the overflow region 310 may be provided.

16 is a cross-sectional view illustrating an image sensor 400 according to example embodiments. In Fig. 16, the same reference numerals as in Figs. 1 to 15 mean the same components.

Referring to FIG. 16 , the image sensor 400 includes a buried transfer gate electrode 440 , a first gate electrode 450A disposed on the sidewall of the semiconductor pattern AP and spaced apart from each other in the vertical direction (Z), and a second It may include a second gate electrode 450B and a third gate electrode 450C.

The transfer gate trench 440T may extend from the first surface 110F1 of the semiconductor substrate 110 into the semiconductor substrate 110 , and the buried transfer gate electrode 440 is disposed in the transfer gate trench 440T. can A transfer gate insulating layer 442 may be further disposed on the inner wall of the transfer gate trench 440T, and a buried transfer gate electrode 440 may fill the inside of the transfer gate trench 440T on the transfer gate insulating layer 442 . A floating diffusion region FD may be disposed in the semiconductor substrate 110 adjacent to the buried transfer gate electrode 440 .

The semiconductor pattern AP may be disposed to be spaced apart from the buried transfer gate electrode 440 in a horizontal direction (eg, an X direction). A first gate electrode 450A, a second gate electrode 450B, and a third gate electrode 450C may be sequentially disposed on the sidewall of the semiconductor pattern AP at different vertical levels. The first gate electrode 450A, the second gate electrode 450B, and the third gate electrode 450C may each have a ring-shaped horizontal cross section and may vertically overlap each other.

A first gate insulating layer 452A is disposed between the first gate electrode 450A and the semiconductor pattern AP, and a second gate insulating layer 452B is disposed between the second gate electrode 450B and the semiconductor pattern AP. is disposed and a third gate insulating layer 452C may be disposed between the third gate electrode 450C and the semiconductor pattern AP. In other embodiments, the first to third gate insulating layers 452A, 452B, and 452C may be connected to each other to completely cover the entire sidewall of the semiconductor pattern AP.

An upper wiring structure 470 covering the buried transfer gate electrode 440 and the semiconductor pattern AP, and the first to third gate electrodes 450A, 450B, and 450C on the first surface 110F1 of the semiconductor substrate 110 . This can be placed The upper wiring structure 470 may include a wiring layer 472 , an insulating layer 474 surrounding the wiring layer 472 , and a via contact 476 extending in the vertical direction Z through the insulating layer 474 . have.

The floating diffusion region FD and the second gate electrode 450B may be electrically connected to each other by a jumper structure FDJP. For example, the jumper structure FDJP may provide an electrical connection between the floating diffusion region FD and the second gate electrode 450B through the wiring layer 472 and the via contact 476 . Although not shown, an additional jumper structure FDJP electrically connects the first gate electrode 450A and the floating diffusion region FD, and/or connects the third gate electrode 450C and the floating diffusion region FD. It may be arranged to electrically connect.

In example embodiments, the first gate electrode 450A may be a reset gate RG, the second gate electrode 450B may be a source follower gate SF, and the third gate electrode 450C may be It may be a selection gate SEL. However, the first to third gate electrodes 450A, 450B, and 450C are not limited thereto.

In example embodiments, the contact 460 and the wiring layer 472 may be disposed on the upper surface and sidewalls of the semiconductor pattern AP to provide an electrical connection necessary for implementing the pixel circuit of the image sensor 400 . . For example, the first gate electrode 450A may be a reset gate RG, the second gate electrode 450B may be a source follower gate SF, and the third gate electrode 450C may be a select gate (RG). SEL), the output signal Vout may be provided to the source/drain region SD2 disposed above the semiconductor pattern AP, and a semiconductor between the source follower gate SF and the reset gate RG. The input signal Vpix may be provided to a portion of the pattern AP.

In example embodiments, the first to third gate electrodes 450A, 450B, and 450C are vertically spaced apart from each other on the sidewall of the semiconductor pattern AP extending in the vertical direction Z, and the first The to third gate electrodes 450A, 450B, and 450C may have a gate-all-around structure. Accordingly, leakage current of pixel circuits such as the reset gate RG, the selection gate SEL, and the source follower gate SF may be reduced, and the occurrence of read noise may be prevented. Accordingly, the image sensor 400 may have excellent image quality. In addition, since the pixel circuits may be stacked and disposed in the vertical direction Z, the area of a unit pixel may be reduced, and the image sensor 400 may be miniaturized.

17 is a cross-sectional view illustrating an image sensor 400A according to example embodiments. In FIG. 17, the same reference numerals as in FIGS. 1 to 16 mean the same components.

Referring to FIG. 17 , the transfer gate trench 440TA may extend from the first surface 110F1 of the semiconductor substrate 110 into the semiconductor substrate 110 , and a transfer gate electrode buried in the transfer gate trench 440TA. 440A may be disposed. The buried transfer gate electrode 440A may be disposed to cover a lower sidewall of the semiconductor pattern AP, and at least a portion of the buried transfer gate electrode 440A may be formed with the first to third gate electrodes 450A, 450B, and 450C. It may be arranged to vertically overlap. The buried transfer gate electrode 440A may have a horizontal cross-section such as a square, a rectangle, a circle, an ellipse, or the like.

17 , the floating diffusion region FD may be disposed within a portion of the semiconductor pattern AP, for example, at a lower vertical level than the bottom surface of the first gate electrode 450A and a buried transfer gate electrode. It may be placed at a higher vertical level than the top surface of 440A.

18 is a cross-sectional view illustrating an image sensor 400B according to example embodiments. In FIG. 18, the same reference numerals as in FIGS. 1 to 17 mean the same components.

Referring to FIG. 18 , the transfer gate trench 440TB may have a ring-shaped horizontal cross-section, and a lower sidewall of the semiconductor pattern AP may extend to an inner wall of the transfer gate trench 440TB. For example, the buried transfer gate electrode 440B may be disposed to cover the lower sidewall of the semiconductor pattern AP in the transfer gate trench 440TB. The buried transfer gate electrode 440A may be disposed to vertically overlap the first to third gate electrodes 450A, 450B, and 450C.

18 , the floating diffusion region FD may be disposed within a portion of the semiconductor pattern AP, for example, at a lower vertical level than the bottom surface of the first gate electrode 450A and a buried transfer gate electrode. It may be placed at a vertical level higher than the top surface of 440B.

19 is a schematic diagram illustrating an image sensor 500 according to example embodiments.

Referring to FIG. 19 , the image sensor 500 may be a stacked image sensor including a first chip C1 and a second chip C2 stacked in a vertical direction. The first chip C1 may include an active pixel region APR and a first pad region PDR1 , and the second chip C2 may include a peripheral circuit region PCR and a second pad region PDR2 . have.

The plurality of first pads PAD1 of the first pad region PDR1 may be configured to transmit and receive electrical signals to and from an external device. The peripheral circuit region PCR may include a logic circuit block LC and may include a plurality of CMOS transistors. The peripheral circuit region PCR may provide a constant signal to each active pixel PX of the active pixel region APR or control an output signal from each active pixel PX. The first pads PAD1 in the first pad region PDR1 may be electrically connected to the second pads PAD2 in the second pad region PDR2 by the via structure VS.

20 is a block diagram showing the configuration of an image sensor 1100 according to an exemplary embodiment.

Referring to FIG. 20 , the image sensor 1100 may include a pixel array 1110 , a controller 1130 , a row driver 1120 , and a pixel signal processor 1140 . The image sensor 1100 includes at least one of the image sensors 100 , 100A, 100B, 100C, 200, 200A, 300, 300A, 400, 400A, 400B, and 500 described with reference to FIGS. 1 to 19 .

The pixel array 1110 may include a plurality of two-dimensionally arranged unit pixels, and each unit pixel may include an organic photoelectric conversion element. The photoelectric conversion element may absorb light to generate electric charge, and an electric signal (output voltage) according to the generated electric charge may be provided to the pixel signal processor 1140 through a vertical signal line. The unit pixels included in the pixel array 1110 may provide an output voltage one at a time in a row unit, and accordingly, the unit pixels belonging to one row of the pixel array 1110 are output by the row driver 1120 . can be simultaneously activated by a selection signal. The unit pixels belonging to the selected row may provide an output voltage according to the absorbed light to an output line of a corresponding column.

The controller 1130 causes the pixel array 1110 to absorb light to accumulate charges, temporarily store the accumulated charges, and output an electrical signal according to the stored charges to the outside of the pixel array 1110; The row driver 1120 may be controlled. Also, the controller 1130 may control the pixel signal processor 1140 to measure an output voltage provided by the pixel array 1110 .

The pixel signal processing unit 1140 may include a correlated double sampler (CDS) 1142 , an analog-to-digital converter (ADC) 1144 , and a buffer 1146 . The correlated double sampler 1142 may sample and hold the output voltage provided by the pixel array 1110 . The correlated double sampler 1142 may double-sample a specific noise level and a level according to the generated output voltage, and output a level corresponding to the difference. Also, the correlated double sampler 1142 may receive the ramp signal generated by the ramp signal generator 1148, compare it with each other, and output a comparison result.

The analog-to-digital converter 1144 may convert an analog signal corresponding to a level received from the correlated double sampler 1142 into a digital signal. The buffer 1146 may latch a digital signal, and the latched signal may be sequentially output to the outside of the image sensor 1100 and transmitted to an image processor (not shown).

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical idea of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

100: image sensor AP: semiconductor pattern
120: photoelectric conversion region 130: pixel element isolation film
140: buried transfer gate electrode 150: first gate electrode
MP: Main electrode part EXP: Extension part

Claims (20)

a semiconductor substrate comprising a first surface and a second surface opposite to each other;
a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface;
a buried transfer gate electrode disposed in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate; and
and a first gate electrode surrounding a sidewall of the semiconductor pattern and having a ring-shaped horizontal cross-section. According to claim 1,
and the first gate electrode is spaced apart from the buried transfer gate electrode in a second direction parallel to the first surface. According to claim 1,
The first gate electrode is
a main electrode part extending in the first direction on the sidewall of the semiconductor pattern; and
and an extension portion disposed on the first surface of the semiconductor substrate and extending in a horizontal direction from the main electrode portion. 4. The method of claim 3,
a first source/drain region disposed inside the semiconductor substrate under the semiconductor pattern; and
The image sensor further comprising a second source/drain region disposed above the semiconductor pattern. 5. The method of claim 4,
a first contact disposed on the first surface of the semiconductor substrate and electrically connected to the first source/drain region;
a second contact disposed on the extension portion of the first gate electrode; and
and a third contact disposed on an upper surface of the semiconductor pattern and electrically connected to the second source/drain region. According to claim 1,
a floating diffusion region disposed adjacent to the transfer gate trench in the semiconductor substrate;
and the transmission gate trench has a ring-shaped horizontal cross-section and surrounds the floating diffusion region in a planar manner. According to claim 1,
and an upper surface of the semiconductor pattern is disposed at a level higher than an upper surface of the buried transfer gate electrode. According to claim 1,
and a second gate electrode surrounding the sidewall of the semiconductor pattern and spaced apart from the first gate electrode in the first direction. 9. The method of claim 8,
The first gate electrode and the second gate electrode have a ring-shaped horizontal cross section,
and the first gate electrode and the second gate electrode vertically overlap each other. 9. The method of claim 8,
The transmission gate trench has a ring-shaped horizontal cross-section,
A lower side of the sidewall of the semiconductor pattern extends to an inner wall of the transfer gate trench. 9. The method of claim 8,
and a floating diffusion region disposed inside the semiconductor pattern and disposed at a level lower than a bottom surface of the first gate electrode and higher than a top surface of the buried transfer gate electrode. a semiconductor substrate comprising a first surface and a second surface opposite to each other;
a buried transfer gate electrode disposed in a transfer gate trench extending from the first surface of the semiconductor substrate into the semiconductor substrate;
a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface; and
A first gate electrode disposed on a sidewall of the semiconductor pattern, the main electrode extending in the first direction and an extension connected to the main electrode and extending on the first surface of the semiconductor substrate; An image sensor comprising a first gate electrode. 13. The method of claim 12,
a first source/drain region disposed inside the semiconductor substrate under the semiconductor pattern;
a second source/drain region disposed above the semiconductor pattern;
a first contact disposed on the first surface of the semiconductor substrate and electrically connected to the first source/drain region;
a second contact disposed on the extension portion of the first gate electrode; and
and a third contact disposed on an upper surface of the semiconductor pattern and electrically connected to the second source/drain region. 13. The method of claim 12,
a floating diffusion region disposed adjacent to the transfer gate trench in the semiconductor substrate;
and the first gate electrode is spaced apart from the buried transfer gate electrode in a second direction parallel to the first surface. 15. The method of claim 14,
and the transmission gate trench has a ring-shaped horizontal cross-section and surrounds the floating diffusion region in a planar manner. 13. The method of claim 12,
a second gate electrode surrounding the sidewall of the semiconductor pattern and spaced apart from the first gate electrode in the first direction; and
and a third gate electrode surrounding the sidewall of the semiconductor pattern and spaced apart from the second gate electrode in the first direction. 17. The method of claim 16,
The second gate electrode and the third gate electrode have a ring-shaped horizontal cross section,
and the first gate electrode, the second gate electrode, and the third gate electrode vertically overlap each other. 13. The method of claim 12,
and a floating diffusion region disposed inside the semiconductor pattern and disposed at a level lower than a bottom surface of the first gate electrode and higher than a top surface of the buried transfer gate electrode. 13. The method of claim 12,
The transmission gate trench has a ring-shaped horizontal cross-section,
A lower side of the sidewall of the semiconductor pattern extends to an inner wall of the transfer gate trench. a semiconductor substrate comprising a first surface and a second surface opposite to each other;
a semiconductor pattern disposed on the first surface of the semiconductor substrate and extending in a first direction perpendicular to the first surface;
a device isolation layer provided on the first surface of the semiconductor substrate and defining an active region;
a buried transfer gate electrode spaced apart from the semiconductor pattern in a second direction parallel to the first surface of the semiconductor substrate and arranged in a transfer gate trench extending into the semiconductor substrate;
a first gate insulating layer surrounding a sidewall of the semiconductor pattern;
a first gate electrode surrounding the sidewall of the semiconductor pattern on the first gate insulating layer and including a main electrode part having a ring-shaped horizontal cross-section;
a first source/drain region disposed inside the semiconductor substrate under the semiconductor pattern; and
and a second source/drain region disposed above the semiconductor pattern.

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