KR20130027153A - Control method of nonvolitile memory device - Google Patents

Abstract

The present invention provides a control method of a nonvolatile memory device that accurately detects the degree of wear of a memory cell. The control method according to the present invention includes programming memory cells and detecting a wear index indicating a wear degree of the memory cells by referring to threshold voltage distributions of the programmed memory cells. In the detecting of the wear ring index, a maximum threshold voltage of the memory cells is read, and a wear ring index corresponding to the read voltage is detected.
According to the present invention, the degree of wear of a memory cell can be accurately detected. A control method for more efficiently managing a memory device with reference to the degree of wear is provided.

Description

CONTROL METHOD OF NONVOLITILE MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a control method of a nonvolatile memory device that effectively determines a wear state of a memory cell.

Semiconductor memory devices are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices have a fast read / write speed, but their contents are lost when the external power supply is interrupted. On the other hand, nonvolatile memory devices retain their contents even when the external power supply is interrupted. Therefore, a nonvolatile memory device is used to store contents that should be preserved regardless of whether power is supplied or not. In particular, the flash memory (Flash memory) of the non-volatile memory has a high degree of integration compared to the conventional EEPROM, it is very advantageous for the application to a large capacity auxiliary storage device.

In the flash memory, as the program erase cycle (hereinafter, referred to as P / E cycle) is repeated, the oxide film of the memory cell is degraded. This causes performance degradation and shortened life, including the retention characteristics of flash memory. To ensure the performance and lifetime of flash memory, various memory control methods, including wear leveling, are used.

An object of the present invention is to provide a control method of a nonvolatile memory device which accurately detects a wear degree of a memory cell.

Another object of the present invention is to provide a control method of a nonvolatile memory device that improves the performance and lifespan of the memory device.

In accordance with another aspect of the present disclosure, a method of controlling a nonvolatile memory device may include: programming memory cells; And detecting a wear index indicating a wear degree of the memory cells by referring to the threshold voltage distribution of the programmed memory cells.

In example embodiments, the wear ring index may be determined by a maximum threshold voltage among threshold voltages of the programmed or erased memory cells.

In an embodiment, the wear ring index may increase as the maximum threshold voltage increases.

The detecting of the wear index may include reading the memory cells by applying a read voltage to a word line; And detecting a wear index corresponding to the read voltage as a wear index of the memory cell.

The method may further include managing the nonvolatile memory device with reference to the wear ring index.

In an embodiment, the managing may include. The method may include an active performance control step or a wear leveling step of varying an incremental step pulse program (ISPP) voltage according to the wear ring index.

A control method of a nonvolatile memory device according to the present invention may include erasing memory cells; And detecting a wear index indicating a wear degree of the memory cells by referring to an erase verification result of the erased memory cells.

In example embodiments, the erasing may include erasing memory cells with a first erase voltage; Verifying whether the memory cells are erased; And erasing the memory cells with a second erase voltage having a voltage level higher than the first erase voltage according to the verified result.

In an embodiment, the wear index may increase according to the verification result.

The method may further include managing the nonvolatile memory device with reference to the wear ring index.

In an embodiment, the managing may include. The method may include an active performance control step or a wear leveling step of varying an incremental step pulse program (ISPP) voltage according to the wear ring index.

According to the present invention, the degree of wear of a memory cell is accurately detected.

In addition, by referring to the degree of wear of the memory cell, the memory device may be efficiently managed to improve performance and lifespan of the memory device.

1 is a block diagram illustrating a nonvolatile memory device.
2 is a cross-sectional view illustrating a general structure of a memory cell.
3 is a view for explaining a difference in the degree of wear according to the P / E cycle environment.
4 is a diagram illustrating the effect of the wear ring of a memory cell on the threshold voltage distribution in the program of the memory cell.
5 is a view for explaining a wear level detecting method according to a first embodiment of the present invention.
FIG. 6 is a diagram illustrating an effect of a wear ring of a memory cell on a threshold voltage distribution in erasing the memory cell.
7 is a view for explaining a wear level detecting method according to a second embodiment of the present invention.
8 is a flowchart illustrating a control method of a nonvolatile memory device according to a first embodiment of the present invention.
9 is a flowchart illustrating a control method of a nonvolatile memory device according to a second embodiment of the present invention.
10 is a block diagram illustrating a user device including a solid state disk (hereinafter, referred to as an SSD) according to an embodiment of the present invention.
11 is a block diagram schematically illustrating a memory system according to the present invention.
12 is a block diagram illustrating a data storage device in accordance with another embodiment of the inventive concept.
13 is a schematic diagram of a computing system including a flash memory device.

The foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed invention. Therefore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when it is mentioned that a certain element includes an element, it means that it may further include other elements. In addition, each embodiment described and illustrated herein includes its complementary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a nonvolatile memory device. Referring to FIG. 1, the nonvolatile memory device 10 includes a cell array 11, an address decoder 12, a page buffer 13, and a control logic 14.

The cell array 11 may include a plurality of memory blocks. In FIG. 1, a cell array 11 including one memory block is illustrated for convenience of description. Each of the memory blocks may be composed of a plurality of pages. Each page may be composed of a plurality of memory cells. In the nonvolatile memory device 10, an erase operation may be performed in units of memory blocks, and a write or read operation may be performed in units of pages.

The cell array 11 may include a plurality of memory cells. The memory cells have a cell string structure. One cell string includes a string selection transistor SST connected to a string selection line SSL, a plurality of memory cells connected to a plurality of word lines WL0 to WLn-1, and a ground selection line GSL. It includes a ground selection transistor (GST) connected to the ground selection line. The string select transistor SST is connected to the bit line BL, and the ground select transistor GST is connected to the common source line CSL.

Here, the memory cells constituting the cell array 11 may be implemented as a memory cell having a charge storage layer such as a floating gate or a charge trap layer or a memory cell having a variable resistance element. The memory cell array 11 may be a single-layer array structure (or referred to as a two-dimensional array structure) or a multi-layer array structure (or a vertical or stacked three-dimensional array structure). It can be implemented to have a.

The address decoder 12 is connected to the cell array 11 through the selection lines SSL and GSL or the word lines WL0 to WLn-1. In the program or read operation, the address decoder 12 receives an address and selects one word line (eg, WL1). On the other hand, the address decoder 12 transmits a voltage required for a program or read operation to a selected word line or an unselected word line.

The page buffer 13 operates as a write driver or as a sense amplifier. The page buffer 13 may temporarily store data to be programmed in selected memory cells or data read from the selected memory cells. The page buffer 13 is connected to the cell array 11 through bit lines BL0 to BLm-1. In the program operation, the page buffer 13 receives data and delivers the data to the memory cells of the selected page. The page buffer 13 reads data from memory cells of a selected page in a read operation and outputs data to the outside.

The control logic 14 may control operations such as programming, reading, and erasing the nonvolatile memory device 10 according to an external command CMD or control. For example, during a program operation, the control logic 14 may control the address decoder 12 to provide a program voltage to a selected word line. The control logic 14 may control the page buffer 13 to provide program data to the selected page.

2 is a cross-sectional view illustrating a general structure of a memory cell. Referring to FIG. 2, impurities are formed in the semiconductor substrate 21 of the memory cell 20 with the first impurity region 21a and the second impurity region 21b. A channel region is generally formed in a portion of the semiconductor substrate 21 located between the first and second impurity regions 21a and 21b. The gate structure is formed on the semiconductor substrate 21 in contact with the first and second impurity regions 21a and 21b. In the gate structure, the tunneling oxide layer 22, the charge storage layer 23, the blocking oxide layer 24, and the gate electrode layer 25 are sequentially formed. The gate electrode layer 25 is made of a conductive material.

The tunneling oxide layer 22 is in contact with the first and second impurity regions 21a and 21b. In the program operation, charges traveling through the semiconductor substrate 11 are trapped in the charge storage layer 23 through the tunneling oxide layer 22. In the erase operation, charge trapped in the charge storage layer 23 is released to the semiconductor substrate 11 by F-N tunneling. The amount of charge trapped in the charge storage layer 23 affects the threshold voltage change of the memory cell 20. By this mechanism of changing the threshold voltage, the memory cell 20 can store data.

On the other hand, as the memory cell 20 repeats program and erase (as the number of P / E cycles increases), the tunneling oxide layer 22 deteriorates, and a leakage path is formed in the tunneling oxide layer 22. As a result, since the charge stored in the charge storage layer 23 is released through the leakage path, the data retention characteristic of the memory cell 20 is degraded.

Various management methods are used to minimize the performance degradation of the memory cell 20 and the decrease in the lifetime according to the increase in the number of P / E cycles. For example, when programming new data, you may preferentially program memory blocks with low P / E cycles. Then, the number of P / E cycles of each memory block can be managed evenly. This is called wear leveling.

As another example of the management method, an incremental step pulse program (ISPP) voltage may be reduced when a memory block having a high number of P / E cycles is programmed. This densifies the threshold voltage distribution of the memory cell and ensures a greater Data Retention Margin. This is called dynamic performance control.

However, since these methods are usually performed only by referring to the number of P / E cycles, there is a problem in that they do not accurately reflect the wear degree of the memory cell. That is, these management methods determine the wear level of the memory cell. As a reference, the number of P / E cycles is used. However, the number of P / E cycles has a certain limit in indicating the degree of wear of a memory cell.

The degree of wear of a memory cell according to one P / E cycle is performed may vary depending on the environment at the time of programming or erasing. Environmental variables that affect the degree of wear of a memory cell may include temperature and operating periods of P / E cycles.

For example, when the temperature at the time of programming or erasing is high, the degree of wear of the memory cell is lower than at normal temperature. Also, even if the same number of P / E cycles are performed, what is performed over a long period of time (eg, 30 times for 30 days) is performed over a short period of time (eg, 30 times for 1 day). Less wear on memory cells than on

3 is a view for explaining a difference in the degree of wear according to the P / E cycle environment. Referring to FIG. 3, the X axis represents the number of P / E cycles performed, and the Y axis represents a wearing index of the memory cell. Here, the wear ring index is a value obtained by quantifying the wear degree of the memory cell. A reference curve is a curve indicating a wear ring index considering only the number of P / E cycles. The real curve is a curve representing the wear ring index of the real memory cell, and has a relatively high temperature and a long P / E cycle environment.

When comparing the actual curve with the reference curve, when the number of P / E cycles is N, the wear index according to the reference curve becomes A. For the same number of P / E cycles, the wear ring index according to the actual curve is A '. That is, an error of A-A 'exists between the wear ring index according to the reference curve and the wear ring index of the actual memory cell. Thus, according to the reference curve, the memory cell is considered to have a larger wear ring index than the actual wear ring index.

On the other hand, in the reference curve, the wear ring indexes A and A 'correspond to N and N' of the number of P / E cycles, respectively. Therefore, the wearing index error of A-A 'size is equal to the P / E cycle error of N-N' times. In this case, an inefficiency may occur in which a management operation (ie, a wear leveling operation or an active performance control operation) for maintaining the function of the memory device is not optimally performed. Accordingly, there is a need for a wear degree detecting method for minimizing an error with an actual wear degree (or wear ring index).

4 to 7 are diagrams for describing a method of controlling a nonvolatile memory device according to the present invention. Specifically, FIGS. 4 to 7 provide a method of detecting a wear level of a memory cell.

4 is a diagram illustrating the effect of the wear ring of a memory cell on the threshold voltage distribution in the program of the memory cell. Referring to FIG. 4, an initial threshold voltage distribution 410 represents a threshold voltage distribution of erased memory cells. The low threshold voltage distribution 420 represents a threshold voltage distribution in which memory cells having a low degree of wear are programmed. The high threshold voltage distribution 430 represents a threshold voltage distribution in which memory cells having a high degree of wear are programmed.

As the degree of wear of a memory cell increases (ie, P / E cycles increase), the program speed of the memory cell also increases. This is because the tunneling oxide layer 22 (see Fig. 2) is deteriorated by repetition of the P / E cycle. In addition, as the tunneling oxide layer 22 deteriorates, the width at which the threshold voltage of the memory cell is increased by the same program voltage also increases. For example, when the memory cells having a low wear level apply a program voltage, the threshold voltage distribution is changed from the initial threshold voltage distribution 410 to the low threshold voltage distribution 420. On the other hand, when memory cells with a high degree of wear are applied to the program voltage, the threshold voltage distribution changes from the initial threshold voltage distribution 410 to the high threshold voltage distribution 430.

Therefore, the threshold voltage distribution 430 that programs the memory cells having a high wear ring degree is more deviated in the positive direction of the X axis than the threshold voltage distribution 420 that programmed the memory cells having a low wear rate. The maximum threshold voltage V _{upper of the} cells having a low wear ring is lower than the maximum threshold voltage V ′ _{upper of the} cells having a high wear ring.

5 is a view for explaining a wear level detecting method according to a first embodiment of the present invention. A first embodiment of the present invention is implemented using a program of a memory cell. Referring to FIG. 5, an initial threshold voltage distribution 510 represents a threshold voltage distribution of erased memory cells. The first threshold voltage distribution 520 represents a threshold voltage distribution in which the first memory cells are programmed. The second threshold voltage distribution 530 represents a threshold voltage distribution in which the second memory cells are programmed. The third threshold voltage distribution 540 represents a threshold voltage distribution in which the third memory cells are programmed.

In this embodiment, the wear degree of the first memory cells is lower than the wear degree of the second memory cells. The wear degree of the second memory cells is lower than that of the third memory cells. As described above, the increase of the threshold voltage by the same program voltage increases as the wear rate of the memory cell increases. Therefore, when memory cells in the erased state are programmed by the same program voltage, memory cells having a high degree of wear have high threshold voltages. In addition, memory cells having a low degree of wear have low threshold voltages.

The first, second and third memory cells are programmed with the same program voltage to detect the degree of wear of the memory cells. Accordingly, the threshold voltage distributions of the first, second and third memory cells rise from the initial threshold voltage distribution 510 to the first, second and third threshold voltage distributions 520, 530, and 540, respectively. In order to detect the degree of wear of the first, second and third memory cells, the maximum threshold voltage of each of the memory cells is detected. The maximum threshold voltage is detected through a read operation on each of the programmed memory cells.

According to an embodiment, a read operation may be performed by the plurality of read voltages V1, V2, V3, and V4 that increase the voltage level constantly. When all of the memory cells are turned on for each read voltage, a wear ring index corresponding to the read voltage is allocated to the memory cells. The wear index is defined as an index indicating a wear degree of each memory cell.

For the read voltage V1, all of the first memory cells are turned on. Accordingly, the first wear ring index is allocated to the first memory cells. The second and third memory cells include memory cells that are not turned on. Thus, for the read voltage V1, the second and third memory cells are not assigned a wear index.

For the second and third memory cells to which the wear ring index is not allocated, a read operation by the read voltage V2 is performed. For the read voltage V2, the second memory cells are all turned on. Thus, a second wear index is allocated to the second memory cells. The third memory cells include memory cells that are not turned on. Accordingly, a wear ring index is not allocated to the third memory cells, and a read operation is performed by an increased read voltage.

For the read voltage V3, the third memory cells include memory cells that are not turned on. Accordingly, a wear ring index is not allocated to the third memory cells, and a read operation is performed by the increased read voltage.

For the read voltage V4, all of the third memory cells are turned on. Thus, a third wear index is allocated to the third memory cells.

Each wear ring index is a numerical value of the wear rate of a memory cell. The wear ring index assigned by a low read voltage indicates a lower wear rate. For example, the wear indexes corresponding to the read voltages V1, V2, V3, and V4 are defined as 1, 2, 3, and 4, respectively. According to him, the wear indexes of the first, second and third memory cells are 1, 2, and 4, respectively. The second memory cells have a wear degree higher than that of the first memory cells. The third memory cells have a wear degree higher than that of the first and second memory cells by 3 and 2, respectively.

As described above, in the present invention, the wear ring index is detected using the magnitude of the threshold voltage which is changed by the program voltage. Accordingly, the wear ring index may accurately reflect the degree of actual deterioration of the tunneling oxide layer 22 (see FIG. 2). That is, up to P / E cycle environment (eg, temperature or P / E cycle operating period) is considered. As a result, more accurate wear ring detection is possible than the method of referring only to the number of P / E cycles.

FIG. 6 is a diagram illustrating an effect of a wear ring of a memory cell on a threshold voltage distribution in erasing the memory cell. Referring to FIG. 6, the threshold voltage distribution 610 represents a threshold voltage distribution of programmed memory cells. The threshold voltage distribution 620 represents a threshold voltage distribution in which memory cells having a low degree of wear are erased. The erase voltage distribution 630 represents a threshold voltage distribution obtained by erasing memory cells having a high degree of wear.

As the degree of wear of the memory cell increases (ie, as the P / E cycle increases), the number of electrons trapped in the tunneling oxide layer 22 (see FIG. 2) increases. In addition, the more electrons trapped in the tunneling oxide layer 22, the stronger the interference of F-N tunneling (Fowler-Nordheim Tunneling). As a result, as the wear degree of the memory cell increases, the erase speed of the memory cell decreases. When the memory cell is erased with the same erase voltage, the change in the threshold voltage is smaller for the memory cell having a greater degree of wear ring.

For example, when an erase operation is performed on memory cells programmed to have the same threshold voltage distribution 610, the threshold voltage variation of memory cells having a high wear level is smaller than that of a memory cell having a low wear level. Accordingly, the threshold voltage distribution 630 of erasing the memory cells having a high wear level is more deviated in the positive direction of the X axis than the threshold voltage distribution 620 of the memory cells having a low wear level.

Therefore, as an embodiment, similar to the first embodiment, the wear ring index may be detected by reading the maximum threshold voltages of the erased memory cells. That is, the erased memory cells are read with a plurality of read voltages with a constant increase in voltage level. When the memory cells are all turned on with respect to the read voltage, the wear ring index corresponding to the read voltage is allocated to the memory cells. If a memory cell is not turned on with respect to the read voltage, the read operation is performed again with respect to the memory cells as the increased read voltage. At this time, the specific wear ring index detection method is the same as described in the first embodiment.

7 is a view for explaining a wear level detecting method according to a second embodiment of the present invention. A second embodiment of the present invention is implemented using the erase of memory cells. Referring to FIG. 7, an initial voltage distribution 710 represents a threshold voltage distribution of programmed memory cells. In this embodiment, the erase operation is performed using an incrementally increasing erase voltage (ISPE: Incremental Step Pulse Erase).

As described above, the threshold voltage distribution of erasing the memory cells varies according to the degree of wear of the memory cells. Therefore, when erasing memory cells by incremental pulse erasure (ISPE), the wear index of the memory cells may be detected by the number of times the erase operation is performed.

For example, referring to FIG. 7, the leftmost threshold voltage distribution N = 3 (solid line) represents the threshold voltage distribution in a completely erased state. In the present exemplary embodiment, the programmed memory cells are erased using the first stage erase voltage (first stage erase). The threshold voltage distribution of the erased memory cell changes from the initial voltage distribution 710 to the one-step threshold voltage distribution (N = 1). The first stage threshold voltage distribution (N = 1) is not a threshold voltage distribution of a complete erase state.

Accordingly, the memory cells are erased again by using the two-step erase voltage that is increased from the one-step erase voltage (second erase). By the second stage erase, the threshold voltage distribution of the memory cells is changed from the first stage threshold voltage distribution N = 1 to the second stage threshold voltage distribution N = 2. The two-stage threshold voltage distribution (N = 2) is also not a threshold voltage distribution in a completely erased state.

Therefore, the memory cells are again erased (third stage erase) with the third stage erase voltage increased from the second stage erase voltage. By the third stage erase, the threshold voltage distribution of the memory cells is changed from the second stage threshold voltage distribution N = 2 to the three stage threshold voltage distribution N = 3. The three-stage threshold voltage distribution (N = 3) is a threshold voltage distribution in a completely erased state. Thus, the erase operation is terminated, and the number of erase operations (ie, 3) performed is detected as the wear index of the memory cells.

Similarly, if any memory cells have a threshold voltage distribution of a complete erase state by two erase operations, the wear index of the memory cells becomes two. The greater the degree of wear of the memory cells, the smaller the change in the threshold voltage due to the same erase voltage. Therefore, as the degree of wear of memory cells increases, the wear ring index will increase.

Meanwhile, in the present embodiment, the magnitude of the erase voltage that is increased for each repeated erase operation may be set differently according to the accuracy of the wear index. As the magnitude of the increasing erase voltage decreases, the accuracy of the wear ring index will increase.

As described above, according to the second exemplary embodiment, the wear ring index may be detected from the threshold voltage distribution of the erased memory cell. Accordingly, the wear ring index may accurately reflect the degree of actual deterioration of the tunneling oxide layer 22 (see FIG. 2). That is, up to P / E cycle environment (eg, temperature or P / E cycle operating period) is considered. As a result, more accurate wear ring detection is possible than the method of referring only to the number of P / E cycles.

8 is a flowchart illustrating a control method of a nonvolatile memory device according to a first embodiment of the present invention. Referring to FIG. 8, a method of controlling a nonvolatile memory device may include steps S810 to S840.

In operation S810, memory cells for detecting a wear index are programmed. The wear ring index is an index indicating a wear degree of a memory cell. The program of the memory cells is performed by applying a predetermined program voltage. Since a specific method of programming a memory cell is well known in the art, a description thereof will be omitted.

In operation S820, threshold voltages of programmed memory cells are read. In this case, in order to detect the maximum threshold voltage of each memory cell, a minimum read voltage at which all memory cells are turned on is applied. Meanwhile, since a specific method of reading a memory cell by applying a read voltage is well known in the art, a description thereof will be omitted.

Specifically, a read operation is performed with the first read voltage. If the first read voltage is greater than the maximum threshold voltage of the memory cells, the first read voltage turns on all the memory cells. Therefore, the first wear ring index corresponding to the first read voltage is set as the wear ring index of the memory cells.

On the other hand, if the first read voltage is less than the maximum threshold voltage, the first read voltage does not turn on some memory cells. Therefore, the read operation is performed again with the second read voltage increased from the first read voltage. If the second read voltage is greater than the maximum threshold voltage of the memory cells, the second read voltage turns on all the memory cells. Therefore, the second wear ring index corresponding to the second read voltage is set as the wear ring index of the memory cells.

On the other hand, if the second read voltage is less than the maximum threshold voltage, the second read voltage does not turn on some memory cells. Therefore, the read operation is performed again with the third read voltage increased from the second read voltage. If the third read voltage is greater than the maximum threshold voltage of the memory cells, the third read voltage turns on all the memory cells. Therefore, the third wear ring index corresponding to the third read voltage is set as the wear ring index of the memory cells.

As such, the read operation is performed while increasing the read voltage until all the memory cells are turned on. When all memory cells are turned on, the wear ring index corresponding to the read voltage at that time is set as the wear ring index of the memory cell.

In operation S830, the wear index of the memory cells is detected. Since the memory cell with a higher degree of wear has a larger threshold voltage change due to the program voltage, the read voltage for turning on the memory cell also increases. In operation S820, a high wear ring index corresponds to the high read voltage. Therefore, the higher the wear ring index will be detected in a memory cell having a higher wear ring degree.

In operation S840, the process of managing the nonvolatile memory device is performed by referring to the wear ring index. At this time, the management process includes general management processes for improving the performance and life reduction of the memory device as the P / E cycle increases.

In an embodiment, the management process may be wear leveling. Wear leveling is a memory management method in which write data is preferentially written to memory cells having a low wear ring index (that is, memory cells having a low wear degree) when new write data is input. That is, through wear leveling, less memory cells with a higher wear index are written and more memory cells with a lower wear index are used. Thus, the wear index of the entire memory cells can be maintained relatively evenly.

Meanwhile, as an embodiment, the management process may be dynamic performance control. As the wear ring index of the memory cell increases (that is, the wear degree of the memory cell increases), the data retention performance decreases. Therefore, the higher the wear ring index of the memory cell being programmed, the smaller the incremental pulse program (ISPP) voltage. As a result, the threshold voltage distribution of the programmed memory cell is narrowed, and a larger margin for data retention is secured. This memory control method is called active performance control.

8 illustrates a method of detecting a wear index by using a program of a memory cell. However, the same detection method can be performed using erasing of memory cells. The method of detecting the wear index by erasing the memory cell is the same as described above with reference to FIG. 6.

According to an embodiment of the present invention, a means for more accurately detecting a wear level of a memory cell is provided. Thus, the performance of control methods for improving the performance and lifespan of the nonvolatile memory device can be improved.

9 is a flowchart illustrating a control method of a nonvolatile memory device according to a second embodiment of the present invention. 9, a method of controlling a nonvolatile memory device includes steps S910 to S970.

In operation S910, an erase voltage is applied to erase memory cells for detecting a wear index. The wear ring index is an index indicating a wear degree of a memory cell. Since the method of erasing the memory cells is well known in the art, a description thereof will be omitted.

In step S920 to step S930, whether the memory cells are erased is verified. If some of the memory cells have not been erased, the process proceeds to step S940 to step S950 for re-erasing. If all the memory cells have been erased and passed, the process proceeds to step S960 to detect the wear index. Since the erase verification method of the memory cell is widely known in the art, a detailed description thereof will be omitted.

In steps S940 to S950, since a part of the memory cells is not erased, the value of the wear ring index is increased by one (S940). In an embodiment, the value of the initial wear index may be 1. In addition, the erase voltage is increased to erase the memory cell (S950). In order to erase the memory cell with the increased erase voltage, the process proceeds to step S910. In operation S940 to operation S950, whenever the erase of the memory cell is failed, the wear ring index and the erase voltage are increased. Therefore, as the erase operation is repeated, the wear index of the memory cell continuously increases.

In operation S960, since the memory cells are all erased and passed, the wear index value of the memory cells is detected. The wear ring index value is determined by the number of times that the loop of steps S910 to S950 is repeatedly performed.

Specifically, when the process proceeds to step S960 without performing steps S940 to S950, the wear ring index value of the memory cell becomes an initial setting value (for example, 1). On the other hand, when the loop of steps S910 to S950 is performed, the wear ring index value of the memory cell is added as many times as the loop is performed. For example, if a memory cell has a threshold voltage distribution of a complete erase state by three erase operations, the memory cell goes through two loops. Thus, the detected wear ring index value of the memory cell is three.

On the other hand, the higher the wear ring, the smaller the change in the threshold voltage due to the erase voltage. Thus, the number of erase operations required to reach a complete erase state also increases. As the number of erase operations increases, a higher wear ring index corresponds, so that a higher wear ring index may be detected in a memory cell having a higher wear level.

In operation S970, the process of managing the nonvolatile memory device is performed by referring to the wear ring index. At this time, the management process includes general management processes for improving the performance and life reduction of the memory device as the P / E cycle increases.

In an embodiment, the management process may be wear leveling. Wear leveling is a memory management method in which write data is preferentially written to memory cells having a low wear ring index (that is, memory cells having a low wear degree) when new write data is input. That is, through wear leveling, less memory cells with a higher wear index are written and more memory cells with a lower wear index are used. Thus, the wear index of the entire memory cells can be maintained relatively evenly.

Meanwhile, as an embodiment, the management process may be dynamic performance control. As the wear ring index of the memory cell increases (that is, the wear degree of the memory cell increases), the data retention performance decreases. Therefore, the higher the wear ring index of the memory cell being programmed, the smaller the incremental pulse program (ISPP) voltage. As a result, the threshold voltage distribution of the programmed memory cell is narrowed, and a larger margin for data retention is secured. This memory control method is called active performance control.

According to an embodiment of the present invention, a means for accurately detecting a degree of wear of a memory cell is provided. Thus, the performance of control methods for improving the performance and lifespan of the nonvolatile memory device can be improved.

10 is a block diagram illustrating a user device including a solid state disk (hereinafter, referred to as an SSD) according to an embodiment of the present invention. Referring to FIG. 10, the user device 1000 includes a host 1100 and an SSD 1200. The SSD 1200 includes an SSD controller 1210, a buffer memory 1220, and a nonvolatile memory device 1230.

The SSD controller 1210 provides a physical connection between the host 1100 and the SSD 1200. That is, the SSD controller 1210 provides interfacing with the SSD 1200 in response to the bus format of the host 1100. In particular, the SSD controller 1210 decodes the instruction provided from the host 1100. [ Depending on the decoded result, the SSD controller 1210 accesses the non-volatile memory device 1230. The bus format of the host 1100 is Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI express, ATA, Parallel ATA (PATA), Serial ATA (SATA), and Serial Attached SCSI (SAS). Etc. may be included.

The SSD controller 1210 detects a wear ring index of the memory block. The wear index is detected during a program or erase operation of the memory block. The method of detecting the wear index is the same as described in the first and second embodiments.

The detected wear ring index is stored in a portion of the nonvolatile memory device 1230. When writing data to be written from the host 1100, the stored wear ring index is referred to. At this time, according to the wear ring index, the SSD controller 1210 performs wear leveling and active performance control.

In this case, the wear variation of the memory blocks is reduced, and the data retention margin is improved. Thus, the performance and life of the memory device is improved.

In the buffer memory 1220, write data provided from the host 1100 or data read from the nonvolatile memory device 1230 may be temporarily stored. When data present in the nonvolatile memory device 1230 is cached at the read request of the host 1100, the buffer memory 1220 supports a cache function of directly providing the cached data to the host 1100. . In general, the data transfer rate by the bus format (eg, SATA or SAS) of the host 1100 is much faster than the transfer rate of the memory channel of the SSD 1200. That is, when the interface speed of the host 1100 is much higher, performance degradation caused by speed difference can be minimized by providing a buffer memory 1220 of a large capacity.

The buffer memory 1220 may be provided to a synchronous DRAM (DRAM) to provide sufficient buffering in the SSD 1200 used as a large capacity auxiliary storage device. However, it will be apparent to those skilled in the art that the buffer memory 1220 is not limited to the disclosure herein.

The nonvolatile memory device 1230 is provided as a storage medium of the SSD 1200. For example, the non-volatile memory device 1230 may be provided as a NAND-type Flash memory having a large storage capacity. The nonvolatile memory device 1230 may be composed of a plurality of memory devices. In this case, each of the memory devices is connected to the SSD controller 1210 on a channel basis. Although the nonvolatile memory device 1230 has been described as an NAND flash memory as an example of the storage medium, the nonvolatile memory device 1230 may be configured with other nonvolatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory and the like may be used as the storage medium, and a memory system in which heterogeneous memory devices are mixed may be applied. A volatile memory device (for example, DRAM) may be included as the storage medium.

11 is a block diagram schematically illustrating a memory system 2000 according to the present invention. Referring to FIG. 11, a memory system 2000 according to the present invention includes a nonvolatile memory device 2200 and a memory controller 2100.

The memory controller 2100 may be configured to control the nonvolatile memory device 2200. The nonvolatile memory device 2200 and the memory controller 2100 may be provided as a memory card. The SRAM 2110 is used as an operating memory of the processing unit 2120. The host interface 2130 has a data exchange protocol of the host connected to the memory system 2000. The error correction block 2140 detects and corrects an error included in data read from the nonvolatile memory device 2200. The memory interface 2150 interfaces with the nonvolatile memory device 2200 of the present invention. The processing unit 2120 performs various control operations for exchanging data of the memory controller 2100. Although not shown in the drawings, the memory system 2000 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host. Self-explanatory to those who have learned.

The memory controller 2100 detects a wear index of the memory block. The wear index is detected during a program or erase operation of the memory block. The method of detecting the wear index is the same as described in the first and second embodiments.

The detected wear ring index is stored in a portion of the nonvolatile memory device 2200. When a write request occurs, the memory controller 2100 performs wear leveling and dynamic performance control by referring to the wear ring index of the included memory block.

In this case, the wear variation of the memory blocks is reduced, and the data retention margin is improved. Thus, the performance and life of the memory device is improved.

The non-volatile memory device 2200 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 2000 of the present invention may be provided as a highly reliable storage medium having a low probability of error occurrence. In this case, the memory controller 2100 communicates with an external (eg, host) via one of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE. Will be constructed.

12 is a block diagram illustrating a data storage device 3000 according to another exemplary embodiment. Referring to FIG. 12, the data storage device 3000 according to the present invention may include a flash memory 3100 and a flash controller 3200. The flash controller 3200 can control the flash memory 3100 based on control signals received from outside the data storage device 3000. [

The flash controller 3200 detects a wear index of the memory block. The wear index is detected during a program or erase operation of the memory block. The method of detecting the wear index is the same as described in the first and second embodiments.

The detected wear ring index is stored in a part of the flash memory 3100. When a write request occurs, the flash controller 3200 performs wear leveling and active performance control by referring to the wear ring index of the included memory block.

In this case, the wear variation of the memory blocks is reduced, and the data retention margin is improved. Thus, the performance and life of the memory device is improved.

The data storage device 3000 of the present invention may constitute a memory card device, an SSD device, a multimedia card device, an SD device, a memory stick device, a hard disk drive device, a hybrid drive device, or a general-purpose serial bus flash device. For example, the data storage device 3000 of the present invention can configure a card that meets industry standards for using a user device such as a digital camera, a personal computer, and the like.

13 schematically illustrates a computing system 4000 including a flash memory device 4120. Computing system 4000 according to the present invention includes a microprocessor 4200, a RAM 4300, a user interface 4400, a modem 4500 such as a baseband chipset, electrically connected to the system bus 4600, and the like. Memory system 4100. The memory system 4100 may be configured substantially the same as the SSD of FIG. 10 or the memory system of FIG. 11 and the memory card of FIG. 12.

When the computing system 4000 according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system 4000 will be further provided. Although not shown in the drawings, the computing system 4000 according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. It is self-evident to those who have acquired common knowledge. The memory system 4100 may, for example, configure a solid state drive / disk (SSD) that uses a nonvolatile memory to store data. Alternatively, the memory system 4100 may be provided as a fusion flash memory (eg, one NAND flash memory).

The memory controller 4110 detects a wear index of the memory block. The wear index is detected during a program or erase operation of the memory block. The method of detecting the wear index is the same as described in the first and second embodiments.

The detected wear ring index is stored in a part of the flash memory device 4120. When a write request is generated from the microprocessor 4200, the memory controller 4110 performs wear leveling and active performance control by referring to the wear ring index of the included memory block.

In this case, the wear variation of the memory blocks is reduced, and the data retention margin is improved. Thus, the performance and life of the memory device is improved.

The nonvolatile memory device and / or memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP), or the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, although specific terms are used herein, they are used for the purpose of describing the present invention only and are not used to limit the scope of the present invention described in the claims or the claims. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

Claims (11)

In the control method of a nonvolatile memory device,
Programming memory cells; And
And detecting a wear index indicating a wear level of the memory cells by referring to threshold voltage distributions of the programmed memory cells. The method of claim 1,
The wear index is determined by a maximum threshold voltage among threshold voltages of the programmed or erased memory cells. The method of claim 2,
And the wear ring index increases as the maximum threshold voltage increases. The method of claim 1,
Detecting the wear ring index,
Reading the memory cells by applying different levels of read voltages to a word line; And
And selecting a wear ring index corresponding to a minimum read voltage at which the memory cells are detected as on-cell among the read voltages as the wear ring index of the memory cells. The method of claim 4, wherein
And managing the nonvolatile memory device with reference to the wear ring index. The method of claim 5, wherein
Wherein the managing comprises:
And a dynamic performance control step or a wear leveling step of varying an incremental step pulse program (ISPP) voltage according to the wear ring index. In the control method of a nonvolatile memory device,
Erasing the memory cells; And
And detecting a wear index indicating a wear degree of the memory cells by referring to an erase verification result of the erased memory cells. The method of claim 7, wherein
The erasing step,
Erasing the memory cells with the first erase voltage;
Verifying whether the memory cells are erased; And
And erasing the memory cells with a second erase voltage having a voltage level higher than the first erase voltage in accordance with the verified result. The method of claim 8,
And the wear ring index increases as the number of times of erase voltage is applied. The method of claim 9,
And managing the nonvolatile memory device with reference to the wear ring index. 11. The method of claim 10,
Wherein the managing comprises:
And a dynamic performance control step or a wear leveling step of varying an incremental step pulse program (ISPP) voltage according to the wear ring index.

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