KR20100111798A - Method for word line double patterning process and nand flash memory array fabricated by the same - Google Patents

Abstract

PURPOSE: A method for word-line double patterning process and a NAND flash memory array fabricated by the same are provided to increase bit density by double patterning word-lines. CONSTITUTION: A dielectric layer(30) is formed on a substrate(10). A first conductive material is stacked on the dielectric layer. A first word-line(42) is formed by etching the first conductive material. An isolating oxide film is formed on the first word-line. A second conductive material is stacked on the substrate. A second word-line(44) is formed by etching the second conductive material.

Description

TECHNICAL FOR WORD LINE DOUBLE PATTERNING PROCESS AND NAND FLASH MEMORY ARRAY FABRICATED BY THE SAME}

The present invention relates to a method of processing a semiconductor memory array, and more particularly, to a word line double patterning process method capable of significantly increasing the degree of integration and a NAND flash memory array implemented thereby.

Currently, in the case of NAND flash memory, the focus has been on increasing the density rather than the operation speed, and the improvement of the density has been mainly studied in the direction of scaling down the memory cells.

However, with traditional optical lithography, there is a certain limit to scaling down memory cells, which will no longer be cost effective in the near future, and the cost of manufacturing per unit bit will increase gradually. It is becoming.

In addition, according to ITRS 2007 (latest version), there is a situation in which no lithography method capable of processing below 32 nm has yet been proposed.

Existing double exposure processes can be used to overcome the above technical limitations, but there are still many problems to be solved in an economical way.

Accordingly, the present invention is to provide a new word line double patterning process method that can meet the rapid scaling requirements of the NAND flash memory and can be reduced in cost.

In addition, by reducing the word line spacing to 50 nm or less by the word line double patterning process method, an inversion type source / drain structure for electrically forming a source / drain into a fringing field of a neighboring word line is provided. It is an object to provide a NAND flash memory array having.

In order to achieve the above object, the word line double patterning process according to the present invention comprises a first step of defining a bit line as an insulating film on a semiconductor substrate; Stacking two or more dielectric layers including a charge storage layer on a substrate on which the bit lines are defined; Stacking and etching a first conductive material on the dielectric layer to form a first word line; Forming a separation oxide film on the first word line; And forming a second word line by laminating and etching a second conductive material on the substrate.

In addition, the NAND flash memory array manufactured according to the word line double patterning process of the present invention is characterized in that two word lines are formed at one pitch.

By double patterning the word lines according to the process method of the present invention, there is an effect that can double the bit density from 1bit / 4F ² to 1bit / 2F ² .

In addition, the NAND flash memory array having an inversion type source / drain structure according to the present invention can significantly reduce the short channel effect because the junction depth of the source / drain is not defined by the conventional ion implantation and activation. There is.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 to 4 are process perspective views showing a first embodiment of a word line double patterning process method according to the present invention, and FIG. 5 shows an example of a NAND flash memory array manufactured according to the first embodiment.

6 to 8 are process perspective views showing a second embodiment of a word line double patterning process method according to the present invention, and FIG. 9 shows an example of a NAND flash memory array manufactured according to the second embodiment.

10 to 12 are process perspective views showing a third embodiment of a word line double patterning process method according to the present invention, and FIG. 13 shows an example of a NAND flash memory array manufactured according to the third embodiment.

[First Embodiment of Processing Method and NAND Array Structure thereby]

First, in the word line double patterning process method, as shown in FIG. 1, the bit line 12 is defined as the insulating film 20 on the semiconductor substrate 10 (first step).

The process of forming the insulating film 20 defining the bit line 12 may be performed by a known STI process or a field oxide film forming process.

Next, as shown in FIG. 2, two or more dielectric layers 30 including a charge storage layer are stacked on the substrate on which the bit lines 12 are defined (second step), and then a first layer is formed on the dielectric layer 30. The conductive material is stacked and etched to form a first word line 40 (third step).

Here, the at least two dielectric layers 30 including the charge storage layer are preferably an ONO layer laminated with a blocking oxide film 36, a nitride film 34, and a tunneling oxide film 32. In this case, the charge storage layer becomes the nitride film 34.

Of course, the charge storage layer 34 may be formed of a floating gate structure by replacing the nitride layer with a conductive material. However, when forming a memory cell with a floating gate structure, a separate process for cutting the conductive material used as the charge storage layer for electrical independence from neighboring cells should be further performed.

In addition, the first conductive material is preferably doped polysilicon.

Next, as shown in FIG. 3, a separation oxide film 50 is formed on the first word line 40 (fourth step).

Here, the separation oxide film 50 is formed by a thermal oxidation process, but may be by a known CVD process. In the thermal oxidation process, as shown in FIG. 3, the first word line made of polysilicon is encroached (42), and a separation oxide film 50 is formed.

The separation oxide film 50 is preferably adjusted to a predetermined thickness to have a thickness of 2 to 50 nm, in particular, without processing an ion implantation process for forming a separate source / drain. This is to form an inversion type source / drain which electrically forms a source / drain in a fringing field. That is, when the thickness is 50 nm or more, the spacing between neighboring word lines becomes wider, and thus it is difficult to form an inversion type source / drain with a fringing field. However, the thickness of the isolation oxide layer 50 may be differently determined according to the operating voltage applied to the word line and the dielectric constant of the insulating material filled between the word lines.

Subsequently, as illustrated in FIG. 4, a second word line 44 is formed by stacking and etching a second conductive material on the substrate (fifth step).

Here, the second conductive material is preferably polysilicon doped in the same manner as the first conductive material, the etching of the second conductive material is a known CMP process or the like, as shown in Figure 4, the first word line It is preferable to flatten so that (42) is revealed.

As shown in FIG. 4, when the upper portion of the substrate is planarized by etching the second conductive material, the separation oxide layer 52 remains between the first word line 42 and the second word line 44. An inversion that electrically forms a source / drain to a fringing field 62 of a neighboring word line by applying a predetermined voltage V _PASS or more to the first word line 42 and the second word line 44. Since the source / drain of the type is formed, there is an advantage that no ion implantation process for forming a separate source / drain is required.

Through the above process, a NAND flash memory array having a structure as shown in FIG. 5 can be manufactured.

The feature of the array is that two word lines are formed in one pitch, thereby increasing the bit density ^twice from 1 bit / 4F ² to 1 bit / 2F ² than in the prior art.

Here, Pitch = L1 + L2 + 2Wox = 2F (F: minimum feature size), and between the first word line and the second word line to form a source / drain with a fringing field 62. The interval is preferably smaller than the line width of the first word line or the second word line, that is, the minimum line width F, more preferably 2 to 50 nm.

The line widths of the first word line 42 and the second word line 44 are equal to each other within the error range by the interval between the first word line and the second word line (that is, the first and second lines). It is desirable to reduce the drive deviation between the memory cells so that the line width difference of the word lines is not larger than these intervals.

[Second embodiment of process method and NAND array structure thereby]

In this first embodiment, as shown in FIG. 4, the first word line 42 is exposed to the second conductive material etch of the fifth step. As shown in FIG. 6, the first word line 42 is exposed. And the blocking oxide film 36 / nitride film 34 / tunneling oxide film 32 between the isolation oxide film 52 and the ONO layer 30 interposed between the second word line 44 and the second word line 44 as an etching mask. As shown in FIG. 7, the source / drain 60 is formed using the grooves exposed by the removal of the separation oxide film 52 and the blocking oxide film 36 / nitride film 34 / tunneling oxide film 32. A seventh step of proceeding with the ion implantation process for, and as shown in Figure 8, the eighth step of filling the insulating film having a high dielectric constant in the groove further proceeds.

The process according to the second embodiment may be useful when the thickness of the isolation oxide layer 50 is too thick in the fourth step or when it is necessary to lower the operating voltage V _PASS applied to the word line. Thus, the NAND flash memory array having the structure as shown in FIG. 9 can be manufactured.

The second has the advantage of features also the two word lines are formed in a pitch (pitch) can be increased two times the bit density than the conventional by 1bit / 2F ² in 1bit / 4F ² of the array according to the second embodiment.

Here, Pitch = L1 + L2 + 2Wox = 2F (F: minimum feature size), and the line widths of the first word line 42 and the second word line 44 are the first word line and the second word. It is desirable to reduce the drive deviation between the memory cells by making them equal within the error range by the line spacing (i.e., so that the line width difference of the first and second word lines is not larger than these spacings).

[Third Embodiment Regarding Process Method and NAND Array Structure]

As shown in FIG. 10, when the etching mask used to form the first word line 40 is removed in the third step, the blocking oxide layer 36 may be selectively removed to form the nitride layer 34 at the bottom of the trench 37. Next, as shown in FIG. 11, the separation oxide film 38 of the fourth step is formed.

Here, the separation oxide film 38 is formed by a known CVD process, but may also be performed by a thermal oxidation process. In the CVD process, as illustrated in FIG. 11, a separation oxide 38 having a predetermined thickness may be formed on the bottom of the trench 37 without encroaching on the first word line 40. As a result, the width of the trench 37 is narrowed so that the width of the second word line is relatively small. In order to prevent this, the thermal oxidation process and the etching process are performed first to increase the width of the first word line 40. After reducing, it is preferable to form a separate oxide film 38 by the CVD process.

After the separation oxide layer 38 is formed, a second word line 41 is formed by stacking and etching a second conductive material on the substrate as shown in FIG. 12 as in the first embodiment. An ONO layer 31 is formed at the bottom of the second word line 41 by a separation oxide film 38, a nitride film 34, and a tunneling oxide film 32.

In order to form the source / drain electrically in the fringing field 62 of the neighboring word line by adjusting the process conditions when forming the separated oxide layer 38 to have a predetermined thickness, in particular, having a thickness of 2 to 50 nm. The same as in the first embodiment.

Through the process according to the third embodiment, a NAND flash memory array having a structure as shown in FIG. 13 can be manufactured.

The second has the advantage of features of the array can also have two word lines are formed in a pitch (pitch) increases twice the bit density than the conventional by 1bit / 2F ² in 1bit / 4F ² according to the third embodiment.

Here, Pitch = L3 + L4 + 2Wox = 2F (F: minimum feature size), and between the first word line and the second word line to form a source / drain with a fringing field 62. The interval is preferably smaller than the line width of the first word line or the second word line, that is, the minimum line width F, more preferably 2 to 50 nm.

The line widths of the first word line 40 and the second word line 41 are equal to each other within the error range by the interval between the first word line and the second word line (ie, the first and second lines). It is desirable to reduce the drive deviation between the memory cells so that the line width difference of the word lines is not larger than these intervals.

Although the preferred embodiments of the present invention have been described above, the technical idea described in the following claims is not limited to the above embodiments, and can be carried out by replacing various equivalents based on the embodiments. Description is omitted.

1 to 4 are process perspective views showing a first embodiment of a word line double patterning process method according to the present invention.

FIG. 5 is a structural perspective view illustrating an example of a NAND flash memory array manufactured according to the first embodiment.

6 to 8 are process perspective views showing a second embodiment of a word line double patterning process method according to the present invention.

9 is a structural perspective view showing an example of a NAND flash memory array manufactured by the second embodiment.

10 to 12 are process perspective views showing a third embodiment of a word line double patterning process method according to the present invention.

FIG. 13 is a structural perspective view illustrating an example of a NAND flash memory array manufactured according to the third embodiment.

<Description of the symbols for the main parts of the drawings>

10: semiconductor substrate 12: bit line

20: insulating film 30, 31: ONO layer

40, 42: first word line 44: second word line

50: separation oxide film 60: source / drain

Claims (8)

Defining a bit line with an insulating film on the semiconductor substrate; Stacking two or more dielectric layers including a charge storage layer on a substrate on which the bit lines are defined; Stacking and etching a first conductive material on the dielectric layer to form a first word line; Forming a separation oxide film on the first word line; And forming a second word line by laminating and etching a second conductive material on the substrate. The method of claim 1, The fourth step is a word line double patterning process characterized in that to form a separated oxide film to a predetermined thickness on the first word line by a thermal oxidation process or a CVD process. The method of claim 2, The thickness of the separated oxide film is a word line double patterning process characterized in that 2 to 50 nm. 4. The method according to any one of claims 1 to 3, At least two dielectric layers including the charge storage layer are ONO layers stacked with a blocking oxide film, nitride film, and tunneling oxide film. And forming the separated oxide film in the fourth step after selectively removing the blocking oxide film. The method of claim 4, wherein The etching of the second conductive material of the fifth step causes the first wordline to be exposed, A sixth step of sequentially removing the isolation oxide film and the nitride film / tunneling oxide film of the ONO layer between the first word line and the second word line as an etch mask; And a seventh step of performing an ion implantation process for source / drain formation using the grooves exposed by the removal of the isolation oxide film and the tunneling oxide film. A NAND flash memory array manufactured by claim 4, NAND flash memory array, characterized in that two word lines are formed in one pitch. The method of claim 6, NAND flash memory array, characterized in that the spacing between the first word line and the second word line forming a source / drain region is less than the line width of the first word line or the second word line. The method of claim 7, wherein Line widths of the first word line and the second word line are equal to each other within an error range by an interval between the first word line and the second word line. And a distance between the first word line and the second word line is 2 to 50 nm.

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