KR20060072833A - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

Forming a gate wiring, a gate electrode, and an upper gate oxide film on the semiconductor substrate, implanting impurity ions using the gate electrode and the gate upper oxide film as a mask to form a low concentration junction region, and forming a sidewall on the sidewall of the gate electrode Forming a transistor including a heavily doped junction region formed by implanting impurity ions using a gate electrode and a sidewall as a mask, forming an epitaxial layer in the heavily doped junction region, removing an oxide layer on the gate, and a gate electrode Forming a salicide on the exposed portion and the epitaxial layer, forming a pre-wiring insulating film on the entire upper structure of the semiconductor substrate, and etching a pre-wiring insulating film to form a source contact hole exposing a portion of the source region. Step, part of the drain region by etching the insulating film before wiring Forming a drain contact hole that exposes, and a method of producing a semiconductor device including forming a gate contact hole which exposes a portion of the gate regions by etching the insulating film around the wiring.

Transistors, contacts

Description

Method for manufacturing a semiconductor device {METHOD OF MANUFACTURGING SEMICONDUCTOR DEVICE}

1 to 5 are cross-sectional views showing step-by-step manufacturing processes of a semiconductor device according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole of a transistor.

In general, a semiconductor device includes and includes a transistor having a gate, a source, and a drain in an element region by a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) device isolation method.

In the manufacturing process of the semiconductor device, the operation speed of the device is a very important factor, and the lower the resistance, the faster the resistance is applied silicide (silicide) to reduce the resistance. Here, the silicide is deposited on the entire surface of the semiconductor device upper structure formed on the semiconductor substrate, and then heat-treated to a predetermined temperature to form the metal silicide.

A method of manufacturing a transistor of such a semiconductor element will be described.

First, a gate insulating film is formed on a semiconductor substrate on which shallow trench isolation (STI) is formed, and a polysilicon layer is deposited thereon. Here, the STI prevents malfunction between the devices by electrically isolating the devices formed on the semiconductor substrate.

Subsequently, the gate insulating layer and the polysilicon layer are etched to form a gate electrode. At this time, the gate electrode is formed on the semiconductor substrate on which the STI is not formed.

Subsequently, a low concentration of impurity ions are implanted onto the semiconductor substrate using the gate electrode as a mask to form a shallow junction region in the active region of the semiconductor substrate exposed to both sides of the gate electrode. The nitride film is formed sequentially.

The oxide film and the nitride film are then etched to form sidewalls. Subsequently, impurities are implanted at a high concentration using the gate electrode and the sidewall as a mask to form source and drain regions.

Next, a metal layer made of cobalt (Co), tantalum (Ta), nickel (Ni), or the like is deposited on the semiconductor substrate and the gate electrode, and then a heat treatment process is performed to form salicide to complete the transistor.

Meanwhile, a metal wiring for connecting such elements, such as a transistor, should be formed in the semiconductor substrate. Before forming the metal wiring to insulate the metal wiring from the semiconductor substrate or the gate electrode, a pre-metal dielectric (PMD) ).

The pre-wiring insulating film includes a PSG (phosphorous silicate glass) film and USG (Un-doped silicate glass), SiN or SiO 2. This is to prevent alkali ions (Na +, K +) or boron ions from penetrating into the channel portion between the source and drain regions.

In addition, since the transistor has a concave-convex structure, the insulating film before wiring must be flattened to form metal wiring thereon. To this end, the insulating film before wiring is laminated, the structure is dense through a heat treatment process, and then the surface is flattened by a chemical-mechanical polishing (CMP) process.

Then, contact holes are formed to expose portions of the gate, source, and drain regions, respectively, for electrical connection with the metal lines formed through subsequent processes.

As semiconductor devices have been highly integrated, transistor devices have been miniaturized. As a result, it is difficult to form a contact hole on the transistor having an uneven structure.

Accordingly, the technical problem of the present invention is to form contact holes in highly integrated semiconductor devices.

The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a gate insulating film, a gate electrode, and an upper gate oxide film on a semiconductor substrate, and implanting impurity ions using the gate electrode and the gate upper oxide film as a mask to form a low concentration junction region; Forming a sidewall on the sidewall of the gate electrode, forming a transistor including a high concentration junction region formed by implanting impurity ions using the gate electrode and the sidewall as a mask, and the high concentration junction region Forming an epitaxial layer on the epitaxial layer, removing the upper oxide layer from the gate, forming a salicide on the exposed portion of the gate electrode and the epitaxial layer, and forming a pre-wiring insulating layer on the entire upper structure of the semiconductor substrate. In the step, the insulating film before wiring Forming a source contact hole for exposing a portion of the source region, etching the insulating film before wiring to form a drain contact hole for exposing a portion of the drain region, and etching the insulating film before wiring Forming a gate contact to expose the gate.

The epi layer is preferably grown along the crystal axis of the semiconductor substrate using TCS (SiHCl 3), DCS (SiH 2 Cl 2), and SiH gas.

It is preferable that the thickness of the said epi layer is 2000-3000 Pa.

The epi layer is preferably formed to a thickness of about 50 to 90% of the gate electrode.

It is preferable that the epi layer is formed at 700 to 1200 ° C.

When the n-type impurity ions are implanted in the low concentration junction region, it is preferable to add PH3 or AsH3 impurities during formation of the epitaxial layer.

When the p-type impurity ions are implanted in the low concentration junction region, it is preferable to add a B2H6 impurity at the time of forming the epi layer.

The sally side is preferably made of cobalt, tantalum or nickel.

A low concentration junction formed in a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate electrode on the semiconductor substrate, and a region below the sidewall. A source and drain junction region formed on a side of the low concentration junction region except for a region below the gate electrode, an epitaxial layer formed on the sidewall side and the source and drain junction region, the exposed gate electrode, and The salicide is formed on the epitaxial layer, and is formed on the entire upper structure of the semiconductor substrate and includes a gate, a source, and a drain contact hole.

It is preferable that the said side wall consists of an oxide film and a nitride film.

It is preferable that the said epi layer contains PH3, AsH3, or B2H6 impurity.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5 are cross-sectional views showing step-by-step manufacturing process of forming a salicide of a semiconductor device according to an embodiment of the present invention.

As shown in Fig. 1, a lower oxide film is formed on a semiconductor substrate 1 on which shallow trench isolation (STI) 2 is formed, and a polysilicon layer and an upper oxide film are formed thereon. Here, the STI 2 prevents malfunction by electrically isolating the elements formed on the semiconductor substrate 1.

Subsequently, the lower oxide film, the polysilicon layer, and the upper oxide film layer are photo-etched to form the gate insulating film 3, the gate electrode 4, and the gate upper oxide film 20. At this time, the gate electrode 4 is formed on the semiconductor substrate 1 without the STI 2.

Next, using the gate electrode 4 as a mask, impurity ions are implanted at a low concentration onto the semiconductor substrate 1 so that the junction region 6a, which is shallow in the active region of the semiconductor substrate 1, is exposed to both sides of the gate electrode 4. 6b), and an oxide film and a nitride film are sequentially formed on the semiconductor substrate 1 and the gate electrode 4.

Then, the oxide film and the nitride film are photo-etched to form the sidewalls 5. Subsequently, impurities are implanted at a high concentration using the gate electrode 4 and the side wall 5 as a mask to form the source 7a and the drain region 7b in the high concentration junction regions 7a and 7b.

Next, as shown in FIG. 2, epitaxial layers 8a and 8b are formed by depositing gaseous semiconductor crystals on the high concentration junction regions 7a and 7b to grow crystals along the crystal axis of the semiconductor substrate. Here, the gas uses TCS (SiHCl 3), DCS (SiH 2 Cl 2), and SiH.

When the epitaxial layers 8a and 8b are grown, a dopant material is injected according to the characteristics of the channel of the transistor.

In the case of an n-channel metal oxide semiconductor (NMOS), the dopant uses PH3 or AsH3, and in the case of a p-channel metal oxide semiconductor (PMOS), the dopant uses B2H6. At this time, the temperature is maintained at about 700 ~ 1200 ℃, the pressure uses a pressure of 760torr or 20torr or more at atmospheric pressure.

The epi layers 8a and 8b are formed at 50 to 90% of the thickness of the gate electrode 4. As an example, when the thickness of the gate electrode 4 is 2000 kPa, the epi layers 8a and 8b are formed to have a thickness of 1000 to 2000 kPa. This is to electrically separate the gate 4, source 7a and drain 7b regions when forming the silicides 9a, 9b, 9c through subsequent processes.

Accordingly, the step difference between the gate electrode 4 and the regions of the source 7a and drain 7b can be reduced. This can prevent the semiconductor device from shorting due to the slight distortion of the arrangement of the contact holes formed in the subsequent process.

In the next step, as shown in FIG. 3, the upper gate oxide layer 20 is removed, and then a metal layer made of cobalt (Co), tantalum (Ta), tungsten (w), or the like is deposited on the entire upper structure of the semiconductor substrate 1. After that, heat treatment is performed to form salicides 9a, 9b, and 9c on the epitaxial layers 8a and 8b and the gate electrode 4.

Then, as shown in FIG. 4, the pre-wiring insulating film 10 is formed on the entire surface of the upper structure of the semiconductor substrate 1 by APCVD and SACVD methods. Subsequently, the pre-wiring insulating film 10 is planarized through chemical mechanical polishing (CMP).

The pre-wiring insulating film includes a PSG (phosphorous silicate glass) film and USG (Un-doped silicate glass), SiN or SiO 2. This is to prevent alkali ions (Na +, K +) or boron ions from penetrating into the channel portion between the source and drain regions.

Next, as shown in FIG. 5, contact holes S, G, and D are formed to expose portions of the gate, source, and drain regions for electrical connection with the metal lines formed in subsequent processes. Here, the contact holes S, G, and D are composed of a source contact hole S, a gate contact hole G, and a drain contact hole D.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

According to the present invention, by shortening the step between the gate electrode and the source and drain regions, the semiconductor device may be prevented from being shorted due to the slight distortion of the contact hole arrangement.

As a result, a fine transistor according to high integration of the semiconductor device can be formed, thereby improving performance of the semiconductor device.

Claims (11)

Forming a gate wiring, a gate electrode, and a gate upper oxide layer on the semiconductor substrate; Implanting impurity ions using the gate electrode and the gate upper oxide film as a mask to form a low concentration junction region; Forming sidewalls on sidewalls of the gate electrodes; Forming a transistor including a high concentration junction region formed by implanting impurity ions using the gate electrode and the sidewall as a mask, Forming an epitaxial layer on the high concentration bonding region, Removing the gate upper oxide layer; Forming a salicide on the exposed portion of the gate electrode and the epi layer; Forming an insulating film before wiring on the entire upper structure of the semiconductor substrate; Etching the insulating film before wiring to form a source contact hole exposing a portion of the source region; Etching the insulating film before wiring to form a drain contact hole exposing a portion of the drain region; and Etching the insulating film before wiring to form a gate contact hole exposing a portion of the gate region; Method for manufacturing a semiconductor device comprising a. In claim 1, The epi layer is a semiconductor device manufacturing method of growing along the crystal axis of the semiconductor substrate using TCS (SiHCl 3), DCS (SiH 2 Cl 2) and SiH gas. In claim 2, The thickness of the said epi layer is a manufacturing method of the semiconductor element formed in 2000-3000 GPa. In claim 3, The epi layer is a method of manufacturing a semiconductor device to form a thickness of about 50 to 90% of the gate electrode. In claim 3, The epi layer is a manufacturing method of a semiconductor device formed at 700 ~ 1200 ℃ The method of claim 3 or 4, And n-type impurity ions are implanted in the low-concentration junction region to add PH3 or AsH3 impurities during formation of the epitaxial layer. The method of claim 3 or 4, And a p-type impurity ion is implanted in the low concentration junction region, wherein the B2H6 impurity is added during formation of the epitaxial layer. In claim 1, The sally side is a method of manufacturing a semiconductor device consisting of cobalt, tantalum or nickel. Semiconductor substrate, A gate insulating film formed on the semiconductor substrate, A gate electrode formed on the gate insulating film, Sidewalls formed on both sides of the gate electrode on the semiconductor substrate, A low concentration junction region formed in the region below the sidewall, Source and drain junction regions respectively formed on the side of the low concentration junction region except for the lower portion of the gate electrode; An epitaxial layer formed on the sidewall side and on the source and drain junction regions, A salicide formed on the exposed gate electrode and the epi layer, and A pre-wiring insulating layer formed on the entire upper structure of the semiconductor substrate and including a gate, a source, and a drain contact hole. Semiconductor device comprising a. In claim 8, The sidewall is a semiconductor device composed of an oxide film and a nitride film. In claim 8, The epi layer is a semiconductor device containing PH3, AsH3 or B2H6 impurities.

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