KR20040054414A - A dual clock generator and a method thereof - Google Patents

Abstract

PURPOSE: An apparatus and a method for dualizing clocks are provided to enhance the reliability by outputting selectively a normal signal without failure from dual clock signals. CONSTITUTION: An apparatus for dualizing clocks includes a first and a second delay unit, a first and a second detection unit, a controller, and a supply unit. The first and the second delay units(120,130) delays the first and the second clock signals as much as a period of inverse numbers of corresponding frequencies. The first and the second detection units(140,150) receive the first and the second clock signals and detect failure states by using internal clocks. The controller(160) receives output signals of the first and the second detection units and outputs a control signal to select the clock signals without failures. The supply unit(180) outputs selectively one of the output signals of the first and the second delay units.

Description

Clock redundancy apparatus and method {A DUAL CLOCK GENERATOR AND A METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock duplication apparatus, and more particularly, to an apparatus and a method for detecting an error of each clock that has been duplexed and selectively outputting an inverse value delayed normal clock signal.

In the processing of digital signals, the clock signal is very important for the safety and stability of the signal to be processed, and in particular, the digital data processed by each functional unit when composed of a plurality of functional units. It must be compatible so that the signals can be interchanged, and use the clock signal that is the reference of the above compatibility, and provide a clock device of dual configuration for precise, safe and stable supply of the clock signal as described above. use.

Generally, a clock / frequency generator generates a clock signal within an error range allowed by a digital circuit designer by using a self-oscillating circuit or receiving reference time information or frequency information from a global positioning system (GPS).

The clock signal generator as described above is redundant in the event of an error or a failure due to a component error, a change in ambient environment, and a temperature change or a clock is blocked due to a failure, and there is an error between the duplicated devices. In this case, it was necessary to develop a technology that solves the problem that TIME JUMP issues.

Hereinafter, a clock duplication apparatus according to the prior art will be described with reference to the accompanying drawings.

Attached to explain the prior art, FIG. 1 is a functional diagram of a clock redundancy apparatus according to the prior art, and FIG. 2 is a state diagram of a clock output according to the prior art.

Referring to FIG. 1, the reference clock / frequency signal is received from the GPS, a crystal oscillation circuit having a high stability, or a predetermined clock signal with a high stability using a phase control circuit PLL or the like. First and second clock units (10, 20) for generating and outputting the;

And a summer 30 that adds the clock 1 signal and the clock 2 signal output from the first and second clock units 10 and 20 as one clock signal.

Hereinafter, a clock duplication apparatus according to the related art having the above configuration will be described in detail with reference to FIGS. 1 and 2.

The first clock unit 10 outputs a clock 1 signal having a high stability by itself, and the second clock unit 20 also outputs a clock 2 signal having a high stability by itself.

The summer 30 receives the clock signal from the first clock unit 10 and the second clock unit 20 as described above, and outputs the sum of the clock 1 signal and the clock 2 signal as one signal. Even when a fault is issued to either one of the first clock unit 10 and the second clock unit 20, the clock signal is outputted normally.

However, the prior art as described above, the difference in the characteristics of the components constituting the first clock unit 10 or the second clock unit 20, the difference in the phase or frequency of the clock signal generated by changes in the ambient environment or temperature, etc. Alternatively, an error is generated, and the error generated as described above is output in a state added by the adder, so that a time jump (TIME JUMP) is issued.

In FIG. 2, a clock 1 signal generated by the first clock unit 10 and a clock 2 signal generated by the second clock unit 20 are illustrated. For example, a fault may be caused by the summer 30. ), Or the clock 1 signal having an error due to the fault (FAULT) and the normal clock 2 are added together, thereby showing an output clock signal having a time jump (TIME JUMP).

When the clock signal having the error and the normal clock signal are combined and supplied as described above, each functional unit to which the clock signal is applied may be abnormally operated to reduce the reliability of the processed data signal.

It is an object of the present invention to provide an apparatus and an operation method for delaying a signal of a duplicated clock generator by an inverse value of a corresponding clock signal and monitoring a non-delayed clock signal to output a normal signal without a failure.

In order to achieve the above object, the present invention includes: first and second delay units for delaying and outputting first and second clock signals by a corresponding frequency reciprocal time of the clock signal, respectively; First and second detectors receiving the first and second clock signals, respectively, and detecting a failure state by an internal clock; A controller which receives and analyzes the signals of the first and second detectors and outputs a control signal for selecting a clock signal in which a failure does not occur; The control unit may include a supply unit which selects and outputs one of the signals from the first delay unit and the second delay unit according to a control signal of the controller.

In addition, the present invention devised to achieve the above object, when the clock phase of the duplicated clock generator is coincident, detecting a fault for the input clock signals, the clock signal is not delayed; According to the fault detection, a delayed clock signal of the input clock signal is selected and output.

1 is a functional block diagram of a clock redundancy device according to the prior art,

2 is a state diagram of a clock output according to the prior art,

3 is a functional block diagram of the clock redundancy apparatus according to the present invention;

4 is a clock redundancy clock timing diagram according to the present invention;

5 is a flowchart illustrating a method for operating a clock redundancy device according to the present invention.

** Explanation of symbols on the main parts of the drawing **

10,100: first clock unit 20,110: second clock unit

30: summer 120: first delay unit

130: second delay unit 140: first detection unit

150: second detection unit 160: control unit

170: internal clock portion 180: supply portion

Hereinafter, a clock duplication apparatus according to the present invention will be described with reference to the accompanying drawings.

3 is a functional diagram of a clock duplication apparatus according to the present invention, FIG. 4 is a clock timing diagram of a clock duplication apparatus according to the present invention, and FIG. 5 is a clock duplication apparatus according to the present invention. How It Works

Referring to FIG. 3, the clock redundancy apparatus according to the present invention uses, for example, a reference signal generated by a high precision GPS reception signal or a phase control circuit PLL or a crystal oscillator X-OSC. First and second clock units 100 and 110 for outputting a high stability clock signal;

First and second delay units (120 and 130) for receiving the signals of the first and second clock units (100 and 110), respectively, and delaying and outputting the signals by the inverse of the corresponding frequency signals;

First and second detectors 140 and 150 that receive the signals of the first and second clock units 100 and 110, respectively, and detect a failure state by an internal clock signal of the internal clock unit 170, which will be described later;

A controller 160 which receives and analyzes the signals of the first and second detectors 140 and 150 and outputs a control signal for selecting a clock signal in which a failure does not occur;

For the operation of the first and second detectors 140 and 150 and the controller 160, an internal clock of several times higher than the clock frequencies of the first and second clock units 100 and 110, for example, 10 times higher. An internal clock unit 170 for supplying a signal;

The supply unit 180 selects and outputs one of the signals of the first delay unit 120 and the second delay unit 130 according to the control signal of the controller 160.

In addition, referring to the accompanying FIG. 5, in the method for operating a clock redundancy apparatus according to the present invention, the clock signals output from the first and second clock units 100 and 110 having independent configurations are respectively received and input as a redundant clock signal. Process (S10),

Delaying (delaying) the clock signal redundantly inputted by the first and second clock units 100 and 110 of the step S10 by an inverse value of the corresponding clock signal and outputting the delayed signal (S20);

Detecting the redundant clock signal that is not delayed to determine whether a failure has occurred, the first and second clock unit (100, 110) of the state before being delayed by the reciprocal value, the first and second detection unit (140,150) ), Respectively, and are applied from the internal clock unit 170, and are several times higher than the frequencies of the clock 1 and clock 2 signals output from the first and second clock units 100 and 110, for example, 10 times higher. Determining an error occurrence state using an internal clock signal (S30);

If it is determined that the failure has occurred in the determination process (S30), the step (S40) of selectively outputting the delay signal of the normal operation clock unit (100, 110) that the failure does not occur by the supply unit 180,

If it is determined that there is no obstacle in the determination process (S30), the supply unit 180 selects and outputs a delay signal of the first clock unit 100 as a default (DEFAULT) (S50),

If it is determined whether or not to repeat all the above process, the process consists of a process of returning to the redundant clock signal input process (S10) and ending the process.

Hereinafter, the present invention having the above configuration will be described in detail with reference to FIGS. 3 to 5.

The first clock unit 100 and the second clock unit 110 may include a reference clock received from a high-precision crystal source (X-TAL OSC), a phase control loop (PLL), or a GPS. Using the signal, each of predetermined frequencies set to high STABILITY is output.

The first clock unit 100 and the second clock unit 110 as described above have independent structures, respectively, and output separate clock signals, which are divided into clock signals having the same frequency, as the clock 1 and the clock 2, respectively.

The clock 1 signal and the clock 2 signal output as described above are applied to the first delay unit 120, the second delay unit 130, the first detector 140, and the second detector 150, respectively.

The first and second delay units 120 and 130 delay and output a time value corresponding to the inverse of the clock frequency. For example, when the signals of the clocks 1 and 2 are 10 MHz, 0.1 micro (μ) Output the delayed time.

The internal clock unit 170 generates a clock signal that is a multiple of a frequency output from the first and second clock units 100 and 10 to the first and second detectors 140 and 150 and the controller 160. For example, when the signals of the clocks 1 and 2 are 10 MHz, an internal clock signal of 100 MHz, which is a multiple of 10, is generated and output.

The first and second detectors 140 and 150 determine whether the first and second clock units 100 output a normal clock signal based on a clock signal applied from the internal clock unit 170.

For example, when the clock signal is 10 MHz and the internal clock signal is 100 MHz as described above, when the signal of the clock 1 is not obstructed, the first detector 140 transmits the clock 1 signal 10 times by the internal clock. Since the result is shown as 1111100000 or 0111110000 or 0011111000, or 0001111100 or 0000111110 or 0000011111, it should be detected as one of the above results.

In the above, 1 represents a high state of the internal clock, and 0 represents a low state.

That is, when the signal of clock 1 is not disturbed, the number of detections of 1 and 0 must be the same by the internal clock.

If the number of times 1 and 0 is not equally detected by half, it is determined that a failure has occurred in the clock 1, and the first detection unit 140 detects that a failure has occurred in the first clock unit 100. Outputs

According to the experiment of the present invention, a slight margin occurs when the internal clock signal output from the internal clock unit 170 and the clock signals output from the first and second clock units 100 and 110 are not synchronized. Therefore, even when the failure does not occur, there is a problem that the ratio of 1 and 0 is detected as 4 to 6 or 6 to 4, but such a problem is easy by increasing the generation frequency of the internal clock unit 170 to a multiple of the clock 1 or 2. Is solved.

As described above, the fault detection signals 1 and 2 detected by the first and second detection units 140 and 150 are respectively applied to the control unit 160, and the control unit 160 analyzes the input signal and operates the corresponding control signal normally. The control signal outputs to the supply unit 180 and selects the clock 1 signal of the first clock unit 100 as a default DEFAULT when a failure does not occur in the first and second clock units 100 and 110. Outputs

The supply unit 180 is delayed and outputted by the reciprocal of the clock frequency from the first or second delay units 120 and 130 by a corresponding control signal applied from the controller 160 as described above. By selecting 1 or 2 and outputting it to the output clock, a normal clock signal is selected and output immediately at the time of failure, and the above operation is output in the state of one clock delay by the first and second delay units 120 and 130. .

A timing diagram of signals output from the clock duplexing apparatus according to the present invention having the above-described configuration is shown in FIG.

Referring to FIG. 4, when the clock 1 and the clock 2 are normally output without failure, the delay clocks 1 and 2 are also normally output. For example, when a failure is detected in the clock 1, the delay is delayed by one clock. Although clock 1 outputs a fault. Since the fault is detected by using the clock signal before the delay is detected by the first detector 140, the control signal is applied to the supply unit 180 to select a signal that is delayed and output from the second clock unit 110. The clock signal that is finally output shows that it is normally output.

Referring to FIG. 5, in the method of operating a clock redundancy device, a redundant clock signal clock 1 and a clock 2 are inputted through the first and second clock units 100 and 110 (S10), and the first and second devices. Delay unit (120, 130) is delayed by the reciprocal value of the frequency (S20), the signal before the delay of the input signal is input from the first and second detection unit (140, 150) and from the internal clock unit 170 It is determined whether a fault clock is detected using the applied clock signal several times higher (S30).

When a failure is detected in the determination (S30), the corresponding failure detection signal 1 or 2 is output to the control unit 160 to be analyzed. The control unit 160 supplies the input unit 180 by the input failure detection signal 1 or 2. The control unit outputs a control signal for selecting a normal delay clock signal by controlling the control unit, and the supply unit 180 selects and outputs a normal delay clock signal according to a control signal input from the control unit 160 (S40).

If the failure is not detected in the determination S30, the controller 160 determines that the clock 1 of the first clock unit 100 selected as the default DEFAULT is the reciprocal value time by the first delay unit 120. The control signal to select the delay clock 1 delayed by the output to the supply unit 180, the delay clock 1 signal selected by the supply unit 180 is output to the output clock (S50).

It is determined whether all the above processes are repeated repeatedly (S60), and if continuing, the process returns to the redundant clock input process (S10).

Therefore, the above-described invention has an advantage in that when a clock fails in a clock duplication apparatus, a clock that operates normally is selected and outputted, and a time jump does not occur.

The present invention having the above configuration has an industrial use effect of stably outputting a clock signal without obstacles by selecting and outputting a clock signal that operates normally among the redundant clock signals.

In addition, since a stable normal clock signal is output, there is a convenient effect of increasing the reliability of the digital signal to be processed.

Claims (4)

First and second delay units for delaying and outputting first and second clock signals by a corresponding frequency reciprocal time of the clock signal, respectively; First and second detectors receiving the first and second clock signals, respectively, and detecting a failure state by an internal clock; A controller which receives and analyzes the signals of the first and second detectors and outputs a control signal for selecting a clock signal in which a failure does not occur; And a supply unit which selects and outputs one of the signals from the first delay unit and the second delay unit according to a control signal of the controller. The method of claim 1, wherein the internal clock, A clock redundancy apparatus, characterized in that for outputting a clock signal of a frequency several times higher than the frequency of the first and second clock portion signal. When the clock phases of the redundant clock generators coincide, A fault is detected for clock signals that are not delayed among the input clock signals. And selecting from among delayed clock signals of the input clock signal according to the fault detection. According to claim 3, The fault detection process, And determining whether the fault occurs by using a first clock signal and a second clock signal and an internal clock signal several times higher than a frequency of the clock signal.