KR20040008504A - Method for manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to maintain constantly the density of elements of a semiconductor substrate and reduce the non-uniformity of critical dimension due to a loading effect by forming a dummy gate electrode pattern between gate electrodes of a low-density gate electrode pattern region. CONSTITUTION: A dummy gate electrode pattern is formed on a semiconductor substrate(110) including a high-density gate electrode pattern region and a low-density gate electrode pattern region in order to form constantly the density of patterns of a gate electrode(160). The dummy gate electrode pattern is formed between the gate electrodes(160) of the low-density gate electrode pattern region. The width of a dummy gate electrode is 0.2 to 2.5 times of the width of the gate electrode.

Description

Method for manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, a dummy gate is formed during fabrication of a giga-class DRAM and a transistor having a thickness of 0.1 μm or less, thereby improving the device characteristics, improving process capability, and manufacturing a semiconductor device. It is about a method.

Problems in the fabrication of high-density dynamic random access memory (DRAM) and ultra-large scale integration (ULSI) using short channel metal oxide semiconductor FETs (MOSFETs) are, first of all, in terms of device characteristics. In other words, the short-circuit effect (Short Channel Effect) in the off state of the transistor increases the leakage current and the contact area due to the decrease in the active area. In addition, from the process point of view, the process is unbalanced due to the density difference of the elements.

The semiconductor device region is largely divided into a cell region in which a memory cell is formed and a peripheral circuit region in which circuit elements for driving the memory cell are formed. In the conventional semiconductor device, the pattern density difference between the devices formed in the cell region and the peripheral circuit region is large. The difference in pattern density refers to the area ratio of patterns formed per unit area, and even if the pattern density is the same within a predetermined area, process imbalance occurs unless the density is uniformly distributed.

Loading effect throughout semiconductor manufacturing process such as photolithography process, etching process, chemical mechanical polishing (CMP) process, deposition process or cleaning process by device density difference between cell region and peripheral circuit region Differences in the loading effects can occur, resulting in process inhomogeneities. In particular, it is difficult to secure a uniform critical dimension (CD) between devices due to the difference in loading effects between the photolithography process and the etching process. In general, the etching of the peripheral circuit area may be larger than the target.

This problem is getting worse due to the miniaturization and densification of semiconductor devices. In order to solve this problem, the manufacturing cost is significantly increased by introducing complicated processes and equipment.

Accordingly, in order to solve the above problem, the present invention forms a dummy gate pattern between gate electrodes of a region having a low density (ie, a peripheral circuit region) of a device, thereby reducing a difference in loading effect generated during a semiconductor manufacturing process. It is an object of the present invention to provide a method for manufacturing a device.

1A through 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

1B and 1C are cross-sectional views illustrating a part of region B of FIG. 1A to explain a split type gate electrode in which the gate electrode and the dummy gate are connected to the metal pad in a subsequent process.

2A is a cross-sectional view illustrating an ion implantation process in a semiconductor manufacturing process according to the present invention, and FIG. 2B is an enlarged view of region F of FIG. 2A and illustrates a concept for controlling a doping profile according to the present invention.

<Explanation of symbols for the main parts of the drawings>

110 semiconductor substrate 120 device isolation film

130: gate oxide film 140: conductive film

150: hard mask layer 160: gate electrode

170: spacer 180: interlayer insulating film

190: Landing plug contact hole 192: Source contact hole

194: drain contact hole 196: gate contact hole

In order to achieve the above technical problem, the present invention provides a gate electrode having a small pattern density of a gate electrode in order to make the pattern density of the gate electrode constant on a semiconductor substrate divided into a dense region and a small region of the gate electrode. A method of manufacturing a semiconductor device is provided, wherein a dummy gate electrode pattern is formed therebetween.

The method may further include forming an isolation layer on a semiconductor substrate divided into a cell region and a peripheral circuit region, depositing a gate oxide layer, a conductive layer, and a hard mask layer over the entire structure, and performing a patterning process. Forming a gate electrode in the peripheral circuit region, and forming a dummy gate electrode between the gate electrode and the gate electrode in the peripheral circuit region, performing a first ion implantation process, and forming sidewalls of the gate electrode and the dummy gate electrode sidewall. Forming a spacer, performing a second ion implantation process, depositing an interlayer insulating film over the entire structure, and removing a portion of the interlayer insulating film to form contact holes in the cell region and the peripheral circuit region. It provides a method for manufacturing a semiconductor device comprising the step of.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1A through 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, an isolation layer 120 is formed on a semiconductor substrate 110 in which a region A of which the pattern density of the gate electrode 160 is dense and a region B of which the pattern density of the gate electrode 160 is small is defined. Form. In the present embodiment, the region A where the pattern density of the gate electrode 160 is dense is defined as the cell region A, and the region B where the pattern density of the gate electrode 160 is limited is defined as the peripheral circuit region B. FIG. I will explain. The pattern density of the gate electrode refers to the area ratio of the gate electrode 160 patterns formed per unit area. The semiconductor substrate 110 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, or a silicon on insulator (SOI) structure substrate, and is not particularly limited. All substrates from which semiconductor devices can be manufactured are included.

An isolation layer 120 is formed on the semiconductor substrate 110 to separate the semiconductor substrate 110 into an active region and a field region. After depositing the gate oxide layer 130, the conductive layer 140, and the hard mask layer 150 on the entire structure, the gate electrode 160 is patterned in the cell region A, and the gate electrode in the peripheral circuit region B. 160 and a dummy gate electrode (DG) are patterned. The conductive layer 140 may include any one or more of polycrystalline Si (poly-Si), amorphous silicon (A-Si), and metal, but is not particularly limited. Means the substance. The gate electrode 160 is formed of one gate having a target gate width (ie, channel length; X), or a split shape in which a sum of a plurality of gate widths forms a target gate width. It can be formed as a gate electrode (see Fig. 1b).

Conventionally, where the pattern density of the gate electrode is dense (i.e., the cell region) and the pattern density of the gate electrode is small (i.e., the peripheral circuit region) appear on the semiconductor substrate by patterning. However, in the present invention, the dummy gate electrode DG pattern is formed between the gate electrodes 160 in the region B of which the pattern density of the gate electrode 160 is small, so that the device density of the semiconductor substrate 110 can be maintained uniformly. have.

Specifically, the dummy gate electrode DG pattern may be formed in any region between the gate electrodes 160 formed in the peripheral circuit region B. That is, it is formed only on the active region between the gate electrodes 160, only on the field region between the gate electrodes 160, or on the active region and the field region between the gate electrodes 160. The gate width of the dummy gate electrode DG pattern formed in the peripheral circuit region B, the number of dummy gate electrodes DG, and the distance between the gate electrode 160 and the dummy gate electrode DG are the density of the device (the pattern of the gate electrode). Density). In the present exemplary embodiment, one to four dummy gate electrodes DG having a width of 0.2 to 1.5 times the width of the gate electrode 160 are formed on the active region and the field region between the gate electrodes 160.

Since the above-described dummy gate electrode DG is formed to maintain a constant pattern density of the gate electrode 160 appearing on the semiconductor substrate 110, it is not necessary to perform a process for electrical connection. In addition, the junction region may not be formed on both sides of the dummy gate electrode DG. Alternatively, the gate electrode may be formed as a split gate electrode, which will be described later, and electrically connected to the gate electrode 160.

1B and 1C are cross-sectional views illustrating a part of region B of FIG. 1A to explain a split type gate electrode in which the gate electrode and the dummy gate are connected to the metal pad in a subsequent process.

Referring to FIG. 1B, a junction region (not shown) is formed on both sides of the dummy gate electrode DG, and the gate electrode 160 and the dummy gate electrode DG formed on both sides thereof are electrically connected to each other to form a split gate. Form an electrode. In order to form the above-described split gate electrode SG, in this embodiment, the gate electrode 160 and the dummy gate electrode DG are formed, and then the two (gate electrodes) are formed by a metal pad (not shown) in a subsequent process. 160 and the dummy gate electrode DG) or one gate electrode is comb-shaped to form a comb-shaped separated gate electrode. At this time, the sum of the widths of the respective gate electrodes is made to match the width (ie, the channel length) of the target gate electrode.

for example. It is assumed that the split gate electrode SG includes one gate electrode 160 and two dummy gate electrodes DG, and the width (ie, channel length) of the target gate electrode is X, and the gate electrode 160 ) Is the width of L1 and the width of the dummy gate electrode DG is L2 and L3, respectively, and the sum L1 + L2 + L3 of the gate electrode 160 and the dummy gate electrode DG is the width of the target gate electrode. Same as (X). If this is expressed as an expression, it is as follows.

X = L1 + L2 + L3

In detail, the widths (ie, L1 to L3) of the gate electrode 160 and the dummy gate electrode DG constituting the split gate electrode SG may be formed to be different from each other or have the same width, respectively ( 1a and 1b). In this embodiment, each electrode width (that is, each channel length) constituting the split gate electrode SG is formed to have a size 1/3 of the channel length.

Referring to FIG. 1C, as described above, the gate electrode 160 formed on the active region and the dummy gate electrode DG formed on both sides of the gate electrode 160 are electrically connected, and the dummy gate formed on the field region. The electrode DG may not maximize the effect of the present invention by not forming an electrical connection.

2A is a cross-sectional view illustrating an ion implantation process in a semiconductor manufacturing process according to the present invention, and FIG. 2B is an enlarged view of region F of FIG. 2A and illustrates a concept for controlling a doping profile according to the present invention. to be.

2A and 2B, lightly doped drain (LDD) or hollow ion implantation (that is, predetermined predetermined) is applied to the semiconductor substrate 110 on which the gate electrode 160 and the dummy gate electrode DG are patterned. Ion implantation with an incident angle). In this case, the doping profile may be controlled by adjusting the distance between the gate electrode 160 and the dummy gate electrode DG in the peripheral circuit region B and the height of the dummy gate electrode DG.

For example, to form a doping profile located between X1 and X2 spaced apart by a positive distance (ie, located on the right side) from the left wall X0 of the gate electrode 160 by ion implantation in a solid line direction, X1 and X2 can be calculated by. In addition, in order to create a doping profile located at X3 away by a negative distance (that is, located on the left side) from the left wall of the gate electrode 160 by ion implantation in the dotted line direction, X3 may be calculated by the following equation. (See Figure 3b).

In the above formula, d is the distance between the gate electrode 160 and the dummy gate electrode (DG), h is the height of the dummy gate electrode (DG) relative to the semiconductor substrate 110, θ is the ion implantation angle and Rp is The projection range, which is a depth injected by ion implantation energy, is shown. Looking at the constants described above, θ (ie, ion implantation angle) and Rp (ie, projection range) are constants controlled by ion implantation equipment, and d (ie, between gate electrode 160 and dummy gate electrode DG). Distance) and h (that is, the height of the dummy gate electrode DG based on the semiconductor substrate 110) are constants controlled by the dummy gate electrode DG pattern. Therefore, according to the above equation, the positions of X1 and X3 that influence the doping profile are not only controlled by the ion implantation equipment but also by the dummy gate electrode DG pattern.

Referring to FIG. 3, a nitride layer for a spacer is deposited on the entire structure, and an etching process is performed to form a spacer 170 on sidewalls of the gate electrode 160 and the dummy gate electrode DG. High concentration ion implantation is performed on the entire structure to form the junction region of the LDD structure.

Referring to FIG. 4, the landing plug contact exposing the junction region J of the LDD structure by depositing an interlayer insulating layer 180 over the entire structure and then removing a portion of the interlayer insulating layer 180 of the cell region A. Referring to FIG. Forming a hole (Landing Plug Contact Hole) 190, and at the same time removing a part of the interlayer insulating layer 180 of the peripheral circuit region (B) source contact hole 192, drain contact hole 194 and gate contact hole 196 ). In the peripheral circuit area of the related art, it is difficult to secure a margin due to misalignment, and thus an interlayer insulating layer cannot be removed by using a self-aligned contact (SAC) method. However, in the peripheral circuit region B in which the dummy gate electrode DG pattern of the present invention is formed, as the misalignment margin is secured by the dummy gate electrode DG, the interlayer insulating layer 180 may be removed using a self-aligned contact method. have.

As described above, according to the present invention, by forming a dummy gate electrode pattern between the gate electrodes where the pattern density of the gate electrode is small, the device density of the semiconductor substrate can be kept uniform, and the nonuniformity of the critical dimension due to the difference in loading effect can be achieved. Can be effectively reduced.

In addition, the doping profile may be controlled by adjusting the distance between the gate electrode and the dummy gate electrode and the height of the dummy gate electrode.

In addition, the source contact hole, the drain contact hole, and the gate contact hole are formed by applying a self-aligned contact process, thereby simplifying the process and reducing the cost.

Claims (9)

In order to make the pattern density of the gate electrode constant on the semiconductor substrate divided into a dense region and a small region of the pattern density of the gate electrode, a dummy gate electrode pattern is formed between the gate electrodes of the region of the pattern density of the gate electrode. The manufacturing method of the semiconductor element made into. The method of claim 1, The width of the dummy gate electrode is 0.2 to 1.5 times the width of the gate electrode, the number of the dummy gate electrode formed between the gate electrode is 1 to 4, characterized in that the manufacturing method. The method of claim 1, And forming a gate electrode with a split gate by electrically connecting the dummy gate electrode to the gate electrode. Forming an isolation layer on a semiconductor substrate divided into a cell region and a peripheral circuit region; Depositing a gate oxide film, a conductive film, and a hard mask layer on the entire structure; Performing a patterning process to form a gate electrode in the cell region, and forming a dummy gate electrode in the peripheral circuit region between the gate electrode and the gate electrode; Performing a first ion implantation process; Forming a spacer on sidewalls of the gate electrode and the dummy gate electrode; Performing a second ion implantation process; Depositing an interlayer insulating film on the entire structure; And Removing a portion of the insulating interlayer to form contact holes in the cell region and the peripheral circuit region. The method of claim 4, wherein The width of the dummy gate electrode is 0.2 to 1.5 times the width of the gate electrode, the number of the dummy gate electrode formed between the gate electrode is 1 to 4, characterized in that the manufacturing method. The method of claim 4, wherein And forming a gate electrode with a split gate by electrically connecting the dummy gate electrode to the gate electrode. The method of claim 4, wherein The first ion implantation process is a manufacturing method of a semiconductor device, characterized in that the LDD and hollow ion implantation. The method according to claim 4 or 7, And controlling the profile of the first ion implantation by the height and width of the dummy gate electrode. The method of claim 4, wherein The interlayer insulating film is removed by performing a self-aligned contact process.