KR20030056118A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20030056118A KR20030056118A KR1020010086279A KR20010086279A KR20030056118A KR 20030056118 A KR20030056118 A KR 20030056118A KR 1020010086279 A KR1020010086279 A KR 1020010086279A KR 20010086279 A KR20010086279 A KR 20010086279A KR 20030056118 A KR20030056118 A KR 20030056118A
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- hard mask
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
- H10P14/69398—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides the material having a perovskite structure, e.g. BaTiO3
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 후속 금속배선 공정에 따른 캐패시터 플라즈마 데미지를 방지할 수 있는 반도체 소자 제조방법을 제공하기 위한 것으로, 이를 위해 본 발명의 일측면에 따르면, 기판 상에 하부전극/유전체 박막/상부전극이 적층된 구조의 캐패시터를 형성하는 단계; 상기 캐패시터가 형성된 기판 전체 구조 상부에 평탄화된 절연막을 형성하는 단계; 금속배선 콘택홀 형성 영역의 상기 절연막을 선택적으로 건식식각하여 콘택홀을 형성하는 단계; 상기 콘택홀이 형성된 전체구조 상부에 금속막을 형성하여 콘택홀이 매립되도록 하는 단계; 상기 금속막 상부에 하드마스크 절연막을 형성하는 단계; 상기 하드마스크 절연막 상부에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 이용하여 상기 하드마스크 절연막을 패터닝하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 패터닝된 하드마스크 절연막을 이용하여 상기 금속막을 패터닝하는 단계; 및 상기 하드마스크 절연막을 습식으로 제거하는 단계를 포함하는 반도체 제조방법이 제공된다.The present invention is to provide a method for manufacturing a semiconductor device that can prevent the capacitor plasma damage caused by the subsequent metallization process, according to one aspect of the present invention, the lower electrode / dielectric thin film / upper electrode is laminated on the substrate Forming a capacitor having a structure; Forming a planarized insulating layer on the entire structure of the substrate on which the capacitor is formed; Selectively dry etching the insulating layer in the metal wiring contact hole forming region to form a contact hole; Forming a metal film on the entire structure of the contact hole so that the contact hole is buried; Forming a hard mask insulating layer on the metal layer; Forming a photoresist pattern on the hard mask insulating film; Patterning the hard mask insulating layer using the photoresist pattern; Removing the photoresist pattern; Patterning the metal film using the patterned hard mask insulating film; And wet removing the hard mask insulating layer.
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 반도체 소자의 제조공정중 캐패시터 및 금속배선 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a capacitor and a metal wiring process in a semiconductor device manufacturing process.
일반적으로 반도체 소자를 제조할 때에 캐패시터를 형성하고 나서 상부전극과 금속배선을 연결하는 공정을 진행하게 되는데, 금속배선을 패터닝하는 공정에서 금속배선이 플라즈마에 노출되면 이로 인해 캐패시터에 데미지를 입게 되어 문제가 생긴다.Generally, when manufacturing a semiconductor device, a capacitor is formed, and then a process of connecting the upper electrode and the metal wiring is performed. When the metal wiring is exposed to the plasma in the process of patterning the metal wiring, the capacitor is damaged due to this. Occurs.
도1a 내지 도1d는 종래기술에 의한 반도체 소자의 캐패시터 제조공정도이다.1A to 1D are diagrams illustrating a capacitor manufacturing process of a semiconductor device according to the prior art.
도1a에 도시된 바와 같이, 종래기술에 따른 캐패시터 제조 공정은 기판(10) 상에 제1 층간절연막(11)을 형성한 다음, 제1 층간절연막(11) 상에 하부전극(12), 유전체 박막(13), 상부전극(14)를 형성해서 캐패시터를 완성한다. 이어서 캐패시터가 형성된 기판전면에 제2 층간절연막(15)를 형성하고 상부전극(14)에 금속배선을 연결하기 위해 콘택홀을 형성한다.As shown in FIG. 1A, a capacitor manufacturing process according to the related art forms a first interlayer insulating film 11 on a substrate 10 and then a lower electrode 12 and a dielectric on the first interlayer insulating film 11. The thin film 13 and the upper electrode 14 are formed to complete a capacitor. Subsequently, a second interlayer insulating film 15 is formed on the entire surface of the substrate on which the capacitor is formed, and a contact hole is formed to connect the metal wiring to the upper electrode 14.
여기서 유전체 박막(13)으로 강유전체를 사용할 때에는 PZT, SBT, PZLT 또는 BLT를 이용하고, 고유전체를 사용할 때에는 BST, STO를 사용한다. 또한, 강유전체 또는 고유전체를 캐패시터의 유전체박막으로 사용할 때는 하부전극(12) 또는 상부전극(14)으로 노블금속 또는 이들의 화합물 (예컨대 Pt, Ir, Ru, RuO2, IrO2)등을 사용한다.Here, PZT, SBT, PZLT or BLT is used when the ferroelectric is used for the dielectric thin film 13, and BST and STO are used when the high dielectric is used. When the ferroelectric or the high dielectric material is used as the dielectric thin film of the capacitor, a noble metal or a compound thereof (for example, Pt, Ir, Ru, RuO 2 , IrO 2 ) or the like is used as the lower electrode 12 or the upper electrode 14. .
이어서, 도1b에 도시된 바와 같이, 후속 금속배선과 캐패시터의 상부전극을 연결하기 위해, 콘택홀이 채워지도록 금속막(16)을 증착한다. 이어서 금속막(16)을 패터닝하기 위해 금속막(16) 상부에 포토레지스터를 패턴(17)을 형성한다.Subsequently, as shown in FIG. 1B, a metal film 16 is deposited to fill the contact hole to connect the subsequent metal wiring and the upper electrode of the capacitor. Next, in order to pattern the metal film 16, a photoresist pattern 17 is formed on the metal film 16.
이어서, 도1c에 도시된 바와 같이, 포토레지스터 패턴(17)을 식각마스크로 사용하여 금속막(16)을 건식식각한다.Subsequently, as illustrated in FIG. 1C, the metal film 16 is dry-etched using the photoresist pattern 17 as an etching mask.
이어서, 도1d에 도시된 바와 같이, 금속막(16)의 식각 공정이 진행된 후에 포토레지스터 패턴(17)을 제거한다. 이 때에 금속막(16)이 노출된 상태에서 플라즈마(Plasma)에 금속막(16)에 노출되는 문제점이 생긴다.Subsequently, as shown in FIG. 1D, the photoresist pattern 17 is removed after the etching process of the metal film 16 is performed. At this time, there is a problem in that the metal film 16 is exposed to the plasma in a state where the metal film 16 is exposed.
따라서 플라즈마에 의한 데미지(damage)가 금속배선을 따라 캐패시터에 누적되고, 이것은 반도체 소자의 동작시 히스테리시스(hysterisis) 루프(loop)의 이동과 같은 커패티서 특성 열화로 이어진다.Thus, damage due to plasma accumulates in the capacitor along the metallization, which leads to deterioration of capacitor characteristics such as movement of a hysteresis loop during operation of the semiconductor device.
본 발명은 후속 금속배선 공정에 따른 캐패시터 플라즈마 데미지를 방지할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing capacitor plasma damage caused by a subsequent metallization process.
도1a 내지 도1d는 종래기술에 따른 반도체 소자의 캐패시터 제조방법을 나타내는 도면.1A to 1D illustrate a method of manufacturing a capacitor of a semiconductor device according to the prior art.
도2a 내지 도2e는 본 발명의 바람직한 실시예에 따른 반도체 소자의 캐패시터 제조방법을 나타내는 도면.2A to 2E illustrate a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판20: substrate
21 : 제1 층간절연막21: first interlayer insulating film
22 : 하부전극22: lower electrode
23 : 유전체박막23: dielectric thin film
24 : 상부전극24: upper electrode
25 : 제2 층간절연막25: second interlayer insulating film
상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 기판 상에 하부전극/유전체 박막/상부전극이 적층된 구조의 캐패시터를 형성하는 단계; 상기 캐패시터가 형성된 기판 전체 구조 상부에 평탄화된 절연막을 형성하는 단계; 금속배선콘택홀 형성 영역의 상기 절연막을 선택적으로 건식식각하여 콘택홀을 형성하는 단계; 상기 콘택홀이 형성된 전체구조 상부에 금속막을 형성하여 콘택홀이 매립되도록 하는 단계; 상기 금속막 상부에 하드마스크 절연막을 형성하는 단계; 상기 하드마스크 절연막 상부에 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 이용하여 상기 하드마스크 절연막을 패터닝하는 단계; 상기 포토레지스트 패턴을 제거하는 단계; 상기 패터닝된 하드마스크 절연막을 이용하여 상기 금속막을 패터닝하는 단계; 및 상기 하드마스크 절연막을 습식으로 제거하는 단계를 포함하는 반도체 제조방법이 제공된다.According to an aspect of the present invention for achieving the above object, forming a capacitor having a structure in which a lower electrode / dielectric thin film / upper electrode is stacked on a substrate; Forming a planarized insulating layer on the entire structure of the substrate on which the capacitor is formed; Selectively dry etching the insulating film in the metal wiring contact hole forming region to form a contact hole; Forming a metal film on the entire structure of the contact hole so that the contact hole is buried; Forming a hard mask insulating layer on the metal layer; Forming a photoresist pattern on the hard mask insulating film; Patterning the hard mask insulating layer using the photoresist pattern; Removing the photoresist pattern; Patterning the metal film using the patterned hard mask insulating film; And wet removing the hard mask insulating layer.
본 발명은 반도체 소자의 캐패시터를 형성한 후 전극과 금속배선을 연결 공정시에 캐패시터에 가해지는 데미지를 최소화 하고자 한 것이다. 이를 위해 금속배선을 위해 금속막을 형성하고 패터닝할 때에 실리콘 산화막 또는 실리콘 질화막으로 하드마스크 패턴을 형성해서 사용하여, 후속 포토레지스터 제거시 금속이 직접 플라즈마에 노출되지 않도록 하고, 하드마스크 절연막은 습식식각을 통해 제거한다.The present invention is to minimize the damage to the capacitor during the process of connecting the electrode and the metal wiring after forming the capacitor of the semiconductor device. To this end, when forming and patterning a metal film for metal wiring, a hard mask pattern is formed of a silicon oxide film or a silicon nitride film so that the metal is not directly exposed to the plasma upon subsequent photoresist removal, and the hard mask insulating film is wet-etched. Remove through.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2e는 본 발명에 의한 바람직한 실시예에 따른 반도체 소자 제조방법을 나타내는 도면이다.2A to 2E are diagrams illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.
본실시예에 따른 반도체 소자 제조방법은 우선, 도2a에 도시된 바와 같이, 반도체 기판(20) 상에 제1 층간절연막(21)을 형성한 다음, 제1 층간절연막(21) 상에 하부전극(22), 유전체 박막(23), 상부전극(24)를 형성하여 캐패시터를 완성한다. 이어서 캐패시터가 형성된 기판전면에 제2 층간절연막(25)를 형성하고 상부전극(24)에 금속배선을 연결하기 위해 콘택홀을 형성한다. 여기서 제2 층간절연막으로 BPSG(Boro-Phospho-Silicate-Glass)를 사용하고, BPSG 플로우(Flow)를 통해 평탄화시킨다.In the method of manufacturing a semiconductor device according to the present embodiment, first, as shown in FIG. 2A, a first interlayer insulating film 21 is formed on a semiconductor substrate 20, and then a lower electrode is formed on a first interlayer insulating film 21. (22), the dielectric thin film 23 and the upper electrode 24 are formed to complete the capacitor. Subsequently, a second interlayer insulating layer 25 is formed on the entire surface of the substrate on which the capacitor is formed, and contact holes are formed to connect metal wirings to the upper electrode 24. Here, BPSG (Boro-Phospho-Silicate-Glass) is used as the second interlayer insulating film and planarized through BPSG flow.
또한, 여기서 유전체 박막(23)으로 강유전체를 사용할 때에는 PZT, SBT, 또는 BLT를 이용하고, 고유전체를 사용할 때에는 BST, STO를 사용한다. 한편, 하부전극(22) 또는 상부전극(24)으로는 노블금속 또는 이들의 화합물 (예컨대 Pt, Ir, Ru, RuO2, IrO2)등을 사용한다.In this case, PZT, SBT, or BLT is used when the ferroelectric is used for the dielectric thin film 23, and BST and STO are used when the high dielectric is used. As the lower electrode 22 or the upper electrode 24, a noble metal or a compound thereof (for example, Pt, Ir, Ru, RuO 2 , IrO 2 ), or the like is used.
계속해서 도2b에 도시된 바와 같이, 콘택홀이 채워지도록 금속막(26)을 증착하고 이어서 금속막(26) 상부에 하드마스크층(27)을 형성하고, 금속배선을 위해 포토레지스트 패턴(28)을 하드마스크층(27) 상부에 형성한다. 이 때 하드마스크층(27)으로는 이후 습식제거가 용이한 실리콘 산화막이나 실리콘 질화막또는 티타늄나이트라이드막을 사용한다.Subsequently, as shown in FIG. 2B, the metal layer 26 is deposited to fill the contact hole, and then the hard mask layer 27 is formed on the metal layer 26, and the photoresist pattern 28 is formed for the metal wiring. ) Is formed on the hard mask layer 27. In this case, the hard mask layer 27 may be a silicon oxide film, a silicon nitride film, or a titanium nitride film that is easily wet-removed thereafter.
이어서, 도2c에 되시된 바와 같이, 포토레지스트 패턴(28)을 식각마스크로 사용하여 하드마스크층(27)을 식각한다.Subsequently, as shown in FIG. 2C, the hard mask layer 27 is etched using the photoresist pattern 28 as an etching mask.
이어서, 도2d에 도시된 바와 같이 패터닝된 하드마스크(27)을 이용하여 금속막(26)을 식각한다.Subsequently, the metal film 26 is etched using the hard mask 27 patterned as shown in FIG. 2D.
이어서 도2e에 도시된 바와 같이, 포토레지스트 패턴(28) 스트립을 진행한다.이 때에는 하드마스크층(27)이 금속막(26)을 캡핑하고 있기 때문에 포토레지스트 패턴(28) 스트립시 금속배선 및 캐패시터에 가해지는 플라즈마 데미지를 방지할 수 있다.Subsequently, as shown in FIG. 2E, the photoresist pattern 28 is stripped. In this case, since the hard mask layer 27 caps the metal layer 26, the metal wiring and the strips of the photoresist pattern 28 are stripped. Plasma damage to the capacitor can be prevented.
이후, 잔류하는 하드마스크층(28)을 습식제거한다. 이때, 하드마스크층(27)으로 실리콘산화막을 사용하는 겨우에는 9:1 BOE나 100:1 BOE를 사용하는 것이 바람직하며, 실리콘질화막을 사용하는 경우에는 인산용액을 사용하는 것이 바람직하다. 이처럼 하드마스크층(27)의 제거를 위해 습식식각을 수행하는 것도 건식식각시 플라즈마 데미지를 최소화 하기 위한 것이다.Thereafter, the remaining hard mask layer 28 is wet removed. In this case, when the silicon oxide film is used as the hard mask layer 27, it is preferable to use 9: 1 BOE or 100: 1 BOE, and when using the silicon nitride film, it is preferable to use a phosphoric acid solution. As such, performing wet etching to remove the hard mask layer 27 is to minimize plasma damage during dry etching.
한편, 하드마스크층으로 사용된 실리콘산화막이나 실리콘질화막은 두께의 제어를 통해 반사방지막(ARC)의 역할을 수행하므로 금속배선 공정시 통상적으로 행해지는 반사방지막(예컨대 TiN)의 증착공정을 생략할 수 있게 된다.On the other hand, the silicon oxide film or silicon nitride film used as the hard mask layer serves as the anti-reflection film (ARC) by controlling the thickness, so that the deposition process of the anti-reflection film (for example, TiN) that is usually performed in the metal wiring process can be omitted. Will be.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 따라 반도체 소자를 제조하면 캐패시터에 가해지는 플라즈마 데미지를 줄여 반도체 소자의 신뢰도를 향상시킬 수 있다.Manufacturing the semiconductor device according to the present invention can improve the reliability of the semiconductor device by reducing the plasma damage to the capacitor.
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