KR20010035577A - a color filter panel for a liquid crystal display - Google Patents

Abstract

A black matrix and red, green, and blue color filters are arranged on the insulating substrate, and a common electrode made of a material such as ITO is separated from the upper surface of the insulating substrate. The separated common electrode is connected by a short point. These short points may be patterned at the same time when forming the common electrode to be formed of ITO material, or may be formed of silver after the common electrode is formed. Each separated common electrode is provided with a plurality of contact points. The common voltage is differentially applied to each contact point according to the delay level of the gate signal to compensate for the pixel voltage.

Description

Color filter substrate for a liquid crystal display device {a color filter panel for a liquid crystal display}

The present invention relates to a liquid crystal display device.

Liquid crystal display is one of the most widely used flat panel display, which consists of two substrates on which electrodes are formed, liquid crystal between two substrates, and two polarizers attached to the outer surface of each substrate to polarize light. The display device controls the amount of light transmitted by rearranging the liquid crystal molecules in the liquid crystal by applying a voltage to the electrode.

In this case, a gate line receiving a gate signal (or scan signal) applied from the outside and a data line, gate line and data line receiving the red, green, and blue data signals (or image signals) applied from the outside intersect one substrate. The thin film transistor and the pixel electrode formed in the part are formed, and this is called a thin film transistor substrate. On the other substrate, the color filter of red, green, and blue, and the common electrode are integrally formed on the front surface, which is called a color filter substrate.

In such a liquid crystal display, the thin film transistor is turned on / off according to a gate signal input through a gate line from the outside, and the red, green, and blue data signals input from the external data line are driven by the thin film transistor. Transferred to the pixel electrode. In this case, an image is displayed by changing the transmittance of light by rearranging the liquid crystal using an electric field formed between the pixel voltage transferred to the pixel electrode and the common voltage transferred to the common electrode of the upper panel.

However, although the pixel voltage actually delivered to the pixel electrode should be the same as the data signal, the pixel voltage is typically reduced and smaller than the data signal, which is due to the parasitic capacitance formed between the gate electrode and the drain electrode of the thin film transistor. This is because the phenomenon that the pixel voltage decreases when is applied. In this case, the reduced voltage is referred to as the kickback voltage, and the kickback voltage causes the flickering of the screen to flicker.

In order to solve this problem, a method of compensating pixel voltage by changing a common voltage has been proposed.

However, this method does not solve the problem that the kickback voltage is irregular because the gate signal on / off voltage difference is changed due to the delay of the signal when the gate signal is transferred along the gate wiring.

In addition, as the size of the panel of the liquid crystal display increases and the size of the common electrode increases, the gate signal delay occurs more and more, thereby compensating the kickback voltage.

An object of the present invention is to minimize the generation of flicker in the liquid crystal display device.

1 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display device;

2 is an equivalent circuit diagram of a unit pixel of a liquid crystal display;

3 is a layout view illustrating a color filter substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line IV-IV of FIG. 3,

5 and 6 illustrate waveforms of a gate signal, a data signal, a pixel voltage, and a common voltage applied to the liquid crystal display.

In order to achieve the above object, in the present invention, at least two contact points are formed by separating the common electrodes and transmitting a common voltage to each of the separated common electrodes.

In this case, a common voltage is differently applied to each contact point in order to compensate for a different pixel voltage partially due to a change in kickback voltage due to signal delay.

Here, the separated common electrodes are connected to each other through a short point, and the middle point of the common voltage transferred to two adjacent common electrodes is applied to the short point.

In the color filter substrate for liquid crystal display devices according to the present invention, a black matrix is formed on the insulating substrate, and red, green, and blue color filters are formed between the black matrices. The upper surface of the substrate is covered with a black matrix and a color filter, and a common electrode made of a transparent conductive material such as ITO is formed separately. Each of the separated common electrodes is formed with at least two or more contact points through which different common voltages are transmitted, and the separated common electrodes are connected by a plurality of short circuit points.

Here, the short point is formed of ITO, which is the same material as the common electrode, and may be formed of a material such as silver.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the same.

First, the driving principle of the liquid crystal display will be described in detail with reference to FIGS. 1 to 4. 1 is a cross-sectional view of a thin film transistor substrate showing only a unit pixel in a liquid crystal display, and FIG. 2 is an equivalent circuit diagram of a unit pixel in a liquid crystal display. 3 is a layout view illustrating a color filter substrate facing the thin film transistor substrate of FIG. 1, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3.

First, as shown in FIGS. 1 and 2, a thin film transistor substrate, which is a lower plate of a liquid crystal display, includes a gate electrode 21 connected to a gate line (not shown) formed in a horizontal direction on the lower insulating substrate 10. Independent wirings 22 separated from the gate lines are formed. The gate insulating film 30 is formed on the gate wirings 21 and 22 including the gate line, and the semiconductor pattern 40 and the ohmic contact layer patterns 51 and 52 are formed on the gate insulating film 30. . A source electrode 61 and a drain electrode 62 are formed on the ohmic contact layer patterns 51 and 52, respectively, and the data line 60 connected to the source electrode 61 intersects with the gate line 20. Unit pixels are defined and formed in the vertical direction. Here, the gate electrode 21, the semiconductor pattern 40, the source electrode 61, and the drain electrode 62 form a thin film transistor TFT. The passivation layer 70 is formed on the semiconductor wiring 40 and the gate insulating film 30 that are not covered by the data wirings 60, 61, 62, and the data wirings 60, 61, 62. The pixel electrode p connected to the drain electrode 62 is formed on the passivation layer 70 through the contact hole 71 of the passivation layer 70.

Meanwhile, as shown in FIGS. 3 and 4, in the color filter substrate, a black matrix 25 has an opening in the pixel and is formed in a mesh shape on the upper insulating substrate 11 facing the lower insulating substrate 10. A plurality of red, green, and blue color filters R, G, and B are formed in the opening of the black matrix 25. A plurality of common electrodes 41, 42, and 43 are separated and formed on the front surface of the black matrix 25 and the color filters R, G, and B of red, green, and blue. Here, the common electrodes 41, 42, and 43 are made of a transparent conductive material such as ITO, and the boundary of each of the separated common electrodes 41, 42, and 43 is formed to be located above the black matrix 25. . The separated common electrodes 41, 42, and 43 are connected to each other through a short point 45, and the short points 45 may be formed together with the ITO material when the common electrodes 41, 42, and 43 are patterned. It may be formed of a conductive material such as silver. Here, the red, green, and blue color filters R, G, and B are disposed at positions corresponding to the pixel electrodes p of the lower insulating substrate 10.

In the liquid crystal display according to the present invention, a liquid crystal capacitor Clc is formed in each pixel between the common electrode co and the pixel electrode p through the liquid crystal layer, and the gate insulating layer 30 and the passivation layer 70 are formed. The storage capacitor Cst is formed between the independent wiring and the pixel electrode p via. In addition, a parasitic capacitance Cgd is formed between the gate electrode 21 and the drain electrode 62.

Meanwhile, in FIG. 3, a plurality of contact points c1, c2, c3, c4, c5, c6, and c7 are displayed on each of the common electrodes 41, 42, and 43, respectively. It is shown. When the gate signal is applied, the degree of signal delay occurs differently depending on the position, and thus the kickback voltage changes irregularly. Accordingly, to compensate the changing pixel voltage uniformly, a plurality of contact points (c1, c2, c3, c4) are used. , c5, c6, and c7) apply a plurality of different common voltages.

This will be described in detail.

First, the relationship between the data signal and the pixel voltage transmitted to the pixel electrode will be described with reference to FIG. 5.

5 illustrates a gate signal VG, a data signal VD, a common voltage Vcom, and a pixel voltage Vp.

Due to the general physical properties of the liquid crystal, as shown in FIG. 5, the liquid crystal molecules are driven by sequentially applying an inverted voltage. In this case, the voltage actually applied to the liquid crystal may be represented by the area between the pixel voltage Vp and the common voltage Vcom. However, while the gate signal VG is turned ON and the gate signal VG is turned OFF, the pixel voltage Vp is always applied to the data signal VD regardless of the polarity of the data signal VD. Lower by kickback voltage (Vk). Therefore, the area formed between the common voltage Vcom and the pixel voltage Vp is different, whereby the voltage applied to the liquid crystal becomes irregular and flicker occurs even when an image is displayed. Therefore, in order to minimize flicker, the pixel voltage Vp, which is asymmetrical with respect to the common voltage Vcom due to the kickback voltage Vk, must be compensated. As shown in FIG. 5, the common voltage Vcom is as low as Vcom1. May be applied.

This kickback voltage (Vk) is expressed as a formula as follows. Here, DELTA Vg is a gate signal on / off difference, and Cgd is a parasitic capacitance generated between the gate electrode and the drain electrode.

As can be seen from Equation 1, the kickback voltage Vk is closely related to the gate on / off voltage. That is, since the kickback voltage Vk is affected by the on / off difference ΔVg of the gate signal, the magnitude of the kickback voltage Vk also changes when the gate signal VG is delayed. Therefore, since the magnitude of the kickback voltage Vk changes according to the delay of the gate signal, the common voltage Vcom should be applied differently in consideration of the signal delay. This will be described with reference to FIG. 6.

FIG. 6 is a diagram illustrating waveforms of a gate signal VG, a data signal VD, a pixel voltage Vp, and a common voltage Vcom applied when a gate signal is delayed.

As shown in FIG. 6, when the gate signal VG is delayed, the gate signal VG is different from the first input signal, and thus the signal waveform does not fall vertically but falls in a curved shape.

In addition, if a delay of the signal occurs while the gate signal VG is transmitted, the gate on voltage becomes small and the difference ΔVg of the gate on / off signal becomes small. Therefore, the kickback voltage Vk1 becomes smaller than the kickback voltage Vk at the portion where there is no signal delay. Due to the kickback voltage Vk1, Vcom2 is higher than Vcom1 applied when there is no signal delay based on the common voltage Vcom to compensate for the asymmetry of the pixel voltage Vp around the common voltage Vcom. Must be authorized.

As shown in FIGS. 5 and 6, the kickback voltage Vk when the signal delay does not occur is greater than the kickback voltage Vk1 when the gate signal VG delay occurs, and is referred to the common voltage Vcom. As a result, the asymmetry of the pixel voltage Vp waveform is different when the gate signal VG delay occurs and when the signal delay does not occur. Therefore, the common voltage Vcom applied where there is no signal delay is lowered to Vcom1 and the common voltage Vcom applied where there is a signal delay applies Vcom2 higher than Vcom1 to minimize flicker generation.

In FIG. 3, when the input terminal of the signal having almost no gate signal delay is assumed to be the left part of the substrate, the signal delay increases toward the right side. A common voltage is applied to the contact point c1 formed near the input terminal of the gate signal to compensate for the asymmetry of the pixel voltage, and a common voltage is applied slightly higher than c1 to the contact point c2 close to the contact point c1, and then in the order of c3 and c4. By applying a high common voltage, the highest common voltage is applied to the contact point c4 having the largest delay. In a similar manner, a common voltage is applied to the contact point c5 located at the bottom of the substrate, and then a high common voltage is applied in the order of c6 and c7. That is, the common voltage is applied higher to the contact point formed at the right side where the gate signal delay is greater than the contact point formed at the left side where there is little gate signal delay.

In this way, even if the pixel voltage is different due to the kickback voltage where the gate signal is not delayed and where the signal is delayed, the common voltage is applied differently to compensate for the asymmetry of the pixel voltage to minimize flicker generation. have.

Here, although the delay degree of the gate signal is similar at the boundary of the separated common electrode, the magnitudes of two adjacent common voltages are different, and thus it is difficult to compensate the kickback voltage even if either of the two common voltages is affected. Accordingly, the kickback voltage is compensated by connecting the separated common electrode with a short point and applying an intermediate value of two adjacent common voltages.

As described above, in the present invention, the common electrode may be separated, and the common voltage may be differentially applied through the contact points formed on the common electrodes, thereby minimizing the flicker caused by the gate signal delay.

Claims (3)

A black matrix having an opening formed on an insulating substrate, Red, green, and blue color filters formed in the openings of the black matrix, A plurality of common electrodes covering the black matrix and the color filters of red, green, and blue and formed separately on the front surface of the substrate; At least two formed on each of the separated common electrodes, the color filter substrate for a liquid crystal display device including a contact point to which different common voltages are transmitted. In claim 1, And a plurality of short circuit points connecting the separated common electrodes to each other, wherein the short circuit points are formed of ITO or silver. In claim 1, The common electrode is a color filter substrate for a liquid crystal display device formed of ITO.