KR102933104B1 - Circuit board and package substrate having the same - Google Patents

Abstract

A circuit board according to an embodiment comprises: a first substrate layer including a cavity; a bridge substrate disposed within the cavity of the first substrate layer; and a second substrate layer disposed on the first substrate layer and the bridge substrate, wherein the first substrate layer comprises: a first insulating layer including the cavity; a first circuit pattern disposed within the first insulating layer; and a first via penetrating the first insulating layer and connected to the first circuit pattern; and wherein the second substrate layer comprises: a second insulating layer disposed on the first insulating layer; a second circuit pattern disposed within the second insulating layer; and a second via penetrating the second insulating layer and connected to the second circuit pattern, wherein the first insulating layer comprises glass fiber, and the second insulating layer does not comprise glass fiber, and the second insulating layer is disposed within the cavity of the first insulating layer to mold the bridge substrate.

Description

Circuit board and package substrate including the same {CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME}

The embodiment relates to a circuit board and a package board including the same.

As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

A typical package substrate consists of a processor package containing a processor chip and a memory package containing memory chips, all connected together. This packaging substrate integrates the processor and memory chips into a single package, reducing chip mounting area and enabling high-speed signal transmission through short paths.

Due to these advantages, the above package substrate is widely used in mobile devices, etc.

Meanwhile, with the recent advancements in electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), package sizes are increasing, and package substrates including interposers are primarily used. In this case, the interposer is composed of a silicon substrate.

However, in the case of interposers such as silicon substrates, there is a problem that not only is the material cost for manufacturing the interposer high, but also the formation of TSV (Through Silicon Via) is complex and expensive.

Furthermore, substrates containing silicon-based interconnect bridges have been conventionally used as package substrates. However, silicon-based interconnect bridges have reliability issues due to CTE (Coefficient of Thermal Expansion) mismatches between the silicon material of the bridge and the organic material of the substrate, and there is a problem of deteriorated power integrity characteristics.

In an embodiment, a circuit board having a novel structure and a package board including the same can be provided.

In addition, the embodiment provides a circuit board on which a plurality of processor chips can be mounted side-by-side and a package board including the same.

In addition, the embodiment provides a circuit board on which a plurality of processor chips and a memory chip can be mounted in parallel, and a package board including the circuit board.

The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

A circuit board according to an embodiment comprises: a first substrate layer including a cavity; a bridge substrate disposed within the cavity of the first substrate layer; and a second substrate layer disposed on the first substrate layer and the bridge substrate, wherein the first substrate layer comprises: a first insulating layer including the cavity; a first circuit pattern disposed within the first insulating layer; and a first via penetrating the first insulating layer and connected to the first circuit pattern; and wherein the second substrate layer comprises: a second insulating layer disposed on the first insulating layer; a second circuit pattern disposed within the second insulating layer; and a second via penetrating the second insulating layer and connected to the second circuit pattern, wherein the first insulating layer comprises glass fiber, and the second insulating layer does not comprise glass fiber, and the second insulating layer is disposed within the cavity of the first insulating layer to mold the bridge substrate.

Additionally, the first insulating layer includes a prepreg, and the second insulating layer includes an Aginomoto Build-up Film (ABF) or a Photoimageable dielectics (PID).

In addition, the first insulating layer includes a 1-1 insulating layer including the cavity, and a 1-2 insulating layer disposed on a lower surface of the 1-1 insulating layer, and the first circuit pattern includes a 1-1 circuit pattern disposed on an upper surface of the 1-1 insulating layer, and a 1-2 circuit pattern disposed between the lower surface of the 1-1 insulating layer and the upper surface of the 1-2 insulating layer, and the 1-2 circuit pattern includes a pad portion exposed through the cavity.

In addition, the 1-1 circuit pattern is a circuit pattern arranged on the first outermost side of the first substrate layer and has an ETS (Embedded Trace Substrate) structure embedded in the upper surface of the 1-1 insulating layer.

In addition, the bridge substrate includes a base layer, a redistribution layer disposed on an upper surface of the base layer, and an adhesive layer disposed on a lower surface of the base layer, and the adhesive layer of the bridge substrate is disposed on an upper surface of the pad portion of the first-second circuit pattern.

In addition, the upper surface of the pad portion of the 1-2 circuit pattern includes a first portion on which the 1-1 insulating layer is disposed, and a second portion exposed through the cavity, and the second portion includes a 2-1 portion on which the adhesive layer of the bridge substrate is disposed, and a 2-2 portion on which the second insulating layer filling the cavity is disposed.

Additionally, the base layer includes polyimide.

In addition, the rewiring layer includes at least one bridge insulating layer disposed on an upper surface of the base layer, a circuit layer disposed on the at least one bridge insulating layer, a via layer penetrating the at least one bridge insulating layer, and a pad layer disposed on an upper surface of the bridge insulating layer disposed on the uppermost side among the at least one bridge insulating layer.

In addition, the second insulating layer includes a 2-1 insulating layer that fills the cavity and is disposed on an upper surface of the 1-1 insulating layer, and a 2-2 insulating layer that is disposed on an upper surface of the 2-1 insulating layer, the second circuit pattern includes a 2-1 circuit pattern that is disposed on an upper surface of the 2-1 insulating layer, and a 2-2 circuit pattern that is disposed on an upper surface of the 2-2 insulating layer, and the second via includes a 2-1 via that penetrates the 2-1 insulating layer, and a 2-2 via that penetrates the 2-2 insulating layer and has a different width from the 2-1 via.

In addition, the 2-1 via includes a first sub-2-1 via that penetrates the 2-1 insulating layer and has a lower surface directly connected to the 1-1 circuit pattern, and a second sub-2-1 via that penetrates the 2-1 insulating layer and has a lower surface directly connected to the pad layer of the bridge substrate.

Additionally, the width of the first sub-2-1 via is greater than the width of the second sub-2-1 via.

Additionally, the lower surface of the first sub-2-1 via is located on a different plane from the lower surface of the second sub-2-1 via.

In addition, the upper surface of the pad layer of the bridge substrate and the upper surface of the 1-1 circuit pattern have a first height difference, and the first height difference is smaller than the thickness difference between the 1-1 insulating layer and the 2-1 insulating layer.

Additionally, the first height difference is less than 25 μm.

Meanwhile, a package substrate according to an embodiment includes a circuit board including a first substrate layer including a first insulating layer including a cavity, a first circuit pattern disposed on the first insulating layer, and a first via penetrating the first insulating layer; a bridge substrate disposed within the cavity of the first insulating layer; a second insulating layer filling the cavity and disposed on an upper surface of the first insulating layer and an upper surface of the bridge substrate, a second substrate layer including a second circuit pattern disposed on the second insulating layer, and a second via penetrating the second insulating layer; first and second adhesive portions disposed spaced apart from each other on the outermost second circuit pattern among the second circuit patterns; a first chip and a second chip disposed on the first and second adhesive portions, respectively; a molding layer disposed on the second insulating layer and molding the first chip and the second chip; And a third adhesive portion disposed on the lower surface of the first circuit pattern disposed at the lowermost side among the first circuit patterns, wherein the first insulating layer includes a prepreg, the second insulating layer includes at least one of ABF and PID, and the bridge substrate includes a redistribution layer including a base layer including polyimide and a pad layer disposed on the base layer and directly connected to the second via of the second substrate layer.

Additionally, the first chip corresponds to a central processor (CPU), and the second chip corresponds to a graphics processor (GPU).

Additionally, the package substrate further includes a memory chip disposed on the outermost side of the second substrate layer and connected to the first chip or the second chip.

Additionally, the gap width between the first chip and the second chip satisfies a range of 60 μm to 150 μm.
Meanwhile, a circuit board according to an embodiment includes a first substrate layer including a cavity; a bridge substrate disposed within the cavity of the first substrate layer; and a second substrate layer disposed on the first substrate layer and the bridge substrate, wherein the first substrate layer includes a plurality of first insulating layers stacked along a vertical direction, a plurality of first circuit patterns respectively disposed within the plurality of first insulating layers, and a plurality of first vias disposed between the plurality of first circuit patterns, and wherein the second substrate layer includes a plurality of second insulating layers stacked along the vertical direction on the first substrate layer, a plurality of second circuit patterns respectively disposed within the plurality of second insulating layers, and a plurality of second vias disposed between the plurality of second circuit patterns, wherein the cavity is provided in an upper insulating layer among the plurality of first insulating layers that is closest to the second substrate layer, and the plurality of first vias includes an upper via that overlaps the cavity along a horizontal direction, and a side surface of the upper via and an inner wall of the cavity have inclinations that are inclined in opposite directions.
Additionally, the first insulating layer comprises glass fibers, and the second insulating layer does not comprise glass fibers.
Additionally, the upper via has a slope that decreases in width in the horizontal direction toward the second substrate layer.
Additionally, the plurality of first vias of the first substrate layer have the same slope.
Additionally, the inner wall of the cavity has a slope such that the width of the cavity in the horizontal direction increases toward the second substrate layer.
Additionally, each of the plurality of second vias has a slope that decreases in width in the horizontal direction toward the first substrate layer.
Additionally, the plurality of second insulating layers include a lower insulating layer disposed closest to the first substrate layer, and the lower insulating layer surrounds a side of the bridge substrate and is disposed within the cavity.
Additionally, the horizontal width of each of the plurality of second circuit patterns is smaller than the horizontal width of each of the plurality of first circuit patterns.
Additionally, the horizontal width of each of the plurality of second vias is smaller than the horizontal width of each of the plurality of first vias.
In addition, each of the plurality of second vias has a different width in the horizontal direction, and the width in the horizontal direction of the second via that is arranged closest to the first substrate layer among the plurality of second vias is the largest, and the width in the horizontal direction of the second via that is arranged farthest from the first substrate layer among the plurality of second vias is the smallest.

A circuit board according to an embodiment includes a first substrate layer and a second substrate layer. The first substrate layer includes a prepreg, thereby maintaining rigidity of the circuit board to improve warpage characteristics and enhance product reliability. Furthermore, the first substrate layer is connected to a main board of an electronic device, and thus includes a first circuit pattern and first vias having specifications corresponding to connection pads of the electronic device. Furthermore, the second substrate layer includes an ABF or a PID, thereby improving connection reliability with a plurality of processor chips. Furthermore, the second substrate layer can provide a second circuit pattern or a second via, which have improved connection reliability with the first circuit pattern or the first via of the first substrate layer.

Furthermore, the second circuit pattern and the second via disposed on the second substrate layer may have a width that gradually increases as they approach the first substrate layer. Accordingly, in the embodiment, signal transmission loss between the first substrate layer and the second substrate layer can be minimized, and further, communication performance can be improved.

In addition, in the embodiment, a bridge substrate is inserted into the first substrate layer, so that the pad layer of the bridge substrate and the second via of the second substrate layer are directly connected to each other. Accordingly, in the embodiment, the signal transmission distance can be minimized, and further, signal transmission loss can be minimized.

In addition, the base layer of the bridge substrate has flexible properties. For example, the base layer of the bridge substrate may include polyimide (PI). Accordingly, in the embodiment, the material of the base layer of the bridge substrate can be changed to polyimide, which is cheaper than a conventional silicon substrate, thereby reducing the cost of the bridge substrate.

In addition, in the embodiment, a circuit layer and a pad layer are formed on the bridge substrate. At this time, the pad layer must be connected to the circuit layer and the second sub-2-1 via of the second via of the second substrate layer. Accordingly, the alignment state of the pad layer and the second sub-2-1 via has a great influence on the product reliability of the circuit substrate and the package substrate. At this time, in the embodiment, the circuit layer and the pad layer are formed using transparent polyimide as a base layer, and thus, the alignment of the circuit layer and the pad layer can be easily effected. In addition, in the embodiment, the accuracy of the formation position of the pad layer is improved, and further, the alignment between the pad layer and the second sub-2-1 via is improved, thereby improving product reliability.

In addition, in the embodiment, by forming the base layer with polyimide, the bridge substrate can be stably protected when the first substrate layer and the second substrate layer are thermally deformed. That is, in the past, the base layer of the bridge substrate was formed with a silicon substrate. At this time, the silicon substrate has a rigid characteristic. Accordingly, in the past, when the first substrate layer or the second substrate layer is thermally deformed, the silicon substrate does not flow together with the bridge substrate, and thus reliability problems such as breakage of the bridge substrate occur.

In contrast, in the embodiment, the base layer of the bridge substrate has a flexible characteristic including polyimide. Accordingly, in the embodiment, when the first substrate layer or the second substrate layer is thermally deformed, the bridge substrate is allowed to flow, thereby resolving reliability issues such as breakage of the bridge substrate.

In addition, in the embodiment, by including the base layer as polyimide, the thickness of the bridge substrate can be easily controlled. For example, in the past, a process of polishing the silicon substrate was required to control the thickness of the bridge substrate including a silicon substrate, and due to the difficulty of the process resulting from this, it was difficult to control the thickness of the bridge substrate to a desired thickness.

In contrast, in the embodiment, due to the characteristics of the polyimide constituting the base layer, its thickness can be easily adjusted, and accordingly, the overall thickness of the bridge substrate can be easily controlled in response to the height of the cavity. Accordingly, in the embodiment, the surface alignment of the pad layer of the bridge substrate and the 1-1 circuit pattern can be facilitated. Accordingly, in the embodiment, the thickness or height deviation of the first sub-2-1 via connected to the 1-1 circuit pattern and the second sub-2-1 via connected to the bridge substrate can be minimized, and thus, product reliability can be improved.

Fig. 1 is a cross-sectional view showing a package substrate according to a comparative example.
Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.
Figure 3 is an enlarged view of the first substrate layer of Figure 2.
FIG. 4 is a drawing specifically showing the layer structure of the first circuit pattern constituting the first substrate layer of FIG. 3.
Figure 5 is an enlarged view of the second substrate layer of Figure 2.
Fig. 6 is a drawing specifically showing the layer structure of the second circuit pattern constituting the second substrate layer of Fig. 5.
Fig. 7 is a drawing showing the bridge substrate of Fig. 2.
Fig. 8 is a drawing for explaining the layer structure of the redistribution layer of the bridge substrate of Fig. 7.
FIG. 9 is a drawing for explaining the height difference between the pad layer and the 1-1 circuit pattern according to the first embodiment, and FIG. 10 is a drawing for explaining the height difference between the pad layer and the 1-1 circuit pattern according to the second embodiment.
Figures 11 to 28 are drawings for explaining the circuit board of Figure 2 in process order.
Fig. 29 is a drawing showing a package substrate according to the first embodiment.
Fig. 30 is a drawing showing a circuit board according to the second embodiment.
Fig. 31 is a drawing showing a package substrate according to the second embodiment.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and/or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of not only the upward direction but also the downward direction based on one component.

-Comparison Example-

Fig. 1 is a cross-sectional view showing a package substrate according to a comparative example.

Referring to Figure 1, in the comparative example, at least two packages are required to transmit signals to the main board of the electronic device.

The package substrate included in the electronic device in the comparative example may be a combination of at least two packages.

The package substrate according to the comparative example includes a first package (10) and a second package (20).

The first package (10) is a processor package in which a processor chip (12) is mounted. And, the second package (20) is a memory package in which a memory chip (23) is mounted.

A first package (10) includes a first substrate (11) on which a processor chip (12) is mounted. The first substrate (11) has a multilayer structure and includes one side on which the processor chip (12) is placed and the other side on which a first adhesive ball (16) is placed. The first package (10) has a fan-out structure and is attached to a main board (not shown) of an electronic device using the first adhesive ball (16) placed on the other side.

A processor chip (12) is mounted on the first substrate (11). The processor chip (12) is an integrated processor chip that integrates various functions. Accordingly, the size of the processor chip (12) increases in proportion to the number of functions it provides. That is, the first substrate (11) has the processor chip (12) mounted on it and has the function of connecting the processor chip (12) and the main mode of the electronic device.

Meanwhile, the first package (10) of the comparative example further includes a second substrate (15). The second substrate (15) is an interposer that interconnects the first package (10) and the second package (20).

That is, the package substrate in the comparative example essentially includes an interposer, such as the second substrate (15). Furthermore, the package substrate in the comparative example has a problem in that its overall volume increases in proportion to the thickness of the interposer. Accordingly, the package substrate in the comparative example increases the thickness of the electronic device, and thus limits its slimming potential.

In addition, the package substrate in the comparative example has a problem in that the length of the signal transmission line increases as the first package (10) and the second package (20) are interconnected using the second substrate (15). That is, in the package substrate in the comparative example, in order to mutually transmit the signal of the processor chip (12) and the signal of the memory chip (23), at least the second substrate (15) must be passed through, and accordingly, the signal transmission distance between the processor chip (12) and the memory chip (23) increases corresponding to the length of the signal transmission line in the second substrate (15). Accordingly, in the comparative example, there is a problem in that high-speed communication between the processor chip (12) and the memory chip (23) is difficult due to the second substrate (15). Furthermore, in the comparative example, as the signal transmission distance due to the second substrate (15) increases, there is a problem in that it is vulnerable to noise, and thus communication performance decreases.

Meanwhile, the first package (10) of the comparative example includes a second adhesive ball (13) disposed on a first substrate (11), and a first molding layer (14) that molds the second adhesive ball (13) and the processor chip (12). At this time, the first molding layer (14) protects the processor chip (12) and the second adhesive ball (13). Accordingly, the thickness of the first molding layer (14) is determined by the height of the processor chip (12) and the second adhesive ball (13). However, in the comparative example, the second substrate (15) is additionally disposed on the first molding layer (14), and accordingly, the thickness of the first molding layer (14) must also take into account the influence of the second substrate (15), which causes a problem in that the thickness increases.

Additionally, the second package (20) of the comparative example includes a third substrate (22), a memory chip (23) placed on the third substrate (22), and a second molding layer (24).

As described above, in the comparative example, at least three substrates are required to electrically connect the processor chip (12) and the memory chip (23) to each other. Furthermore, the comparative example requires a process for bonding at least three substrates to each other, which leads to problems such as an increase in the number of manufacturing processes and a decrease in yield due to complexity. Specifically, in the comparative example, at least three substrates are required because of the difficulty of the process of placing different chips on a single substrate.

Additionally, in the comparative example, at least two adhesive balls are required to bond at least three substrates together.

That is, in the comparative example, a second adhesive ball (13) for connecting the first substrate (11) and the second substrate (15) and a third adhesive ball (21) for connecting the second substrate (15) and the third substrate (22) are required. Accordingly, the package substrate according to the comparative example requires at least two or more adhesive balls for mutual bonding of a plurality of substrates, and therefore has a problem that the reliability of the package substrate may be reduced due to poor connection of the adhesive balls. In addition, it has a structure in which the two or more adhesive balls are arranged in the thickness direction, and has a problem that the thickness of the package substrate and, further, the thickness of the electronic device increases by the thickness of the adhesive balls.

Specifically, the first substrate (11) has a first thickness (t1) of 120 μm to 150 μm. The second thickness (t2) including the first molding layer (14), the processor chip (12), and the second adhesive ball (13) is 145 μm to 160 μm. In addition, the third thickness (t3) of the second substrate (15) is 90 μm to 110 μm. In addition, the fourth thickness (t4) of the first adhesive ball (16) is 130 μm to 150 μm.

Accordingly, the total thickness (t8) of the first package (10) including the first to fourth thicknesses (t1, t2, t3, t4) is 480 µm to 550 µm.

In addition, the fifth thickness (t5) of the third adhesive ball (21) is 145 µm to 180 µm. In addition, the sixth thickness (t6) of the third substrate (22) is 90 µm to 110 µm. In addition, the seventh thickness (t7) including the memory chip (23) and the second molding layer (24) is 370 µm to 400 µm. Accordingly, the total thickness (t9) of the second package (20) including the fifth to seventh thicknesses (t5, t6, t7) is 610 µm to 700 µm. Therefore, the total thickness of the package substrate of the comparative example is 1100 µm or more.

Meanwhile, due to the recent trend of slimming down of electronic devices, the required thickness of the package substrate is 1100㎛ or less. In addition, the type of electronic device recently is mainly foldable products, and due to the nature of the foldable product, while there are few restrictions in the length direction, there are large restrictions in the thickness direction. However, the package substrate of the comparative example has a problem in that it does not satisfy the specifications required for electronic devices because it has a structure in which multiple substrates are mutually bonded by multiple adhesive balls in the thickness direction.

In addition, as the performance of electrical/electronic products has been advanced recently, technologies for attaching a larger number of packages to a limited-sized substrate are being studied, and accordingly, miniaturization of circuit patterns is required. However, in the case of the package substrate of the comparative example, there is a limit to miniaturization of the circuit pattern. The circuit pattern included in the package substrate of the comparative example has a line width of at least 10㎛ or more and a gap of at least 10㎛. In addition, as the functions processed in the application processor (AP) have increased recently, it has become difficult to implement them in a single chip. However, in the case of the circuit pattern provided in the comparative example, it is difficult to mount two application processors (APs) performing different functions on a single first substrate (11).

The embodiment is intended to solve the problems of these comparative examples, and provides a circuit board having a novel structure capable of mounting multiple application processor chips on a single board, and a package board including the same.

Furthermore, in order to solve the problems of the comparative examples, the embodiment provides a circuit board having a new structure capable of mounting an application processor chip and a memory chip side by side, and a package board including the same.

-Electronic devices-

Before describing the embodiment, an electronic device including a package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and/or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly speaking, the package substrate may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

And, in an embodiment, a package substrate capable of mounting at least two different types of chips on one substrate while reducing the thickness of the package substrate connected to the main board of the electronic device is provided.

At this time, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited thereto, and it is obvious that the electronic device may be any other electronic device that processes data.

Example

Hereinafter, a circuit board according to an embodiment and a package board including the circuit board will be specifically described.

FIG. 2 is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 3 is an enlarged view of the first substrate layer of FIG. 2, FIG. 4 is a drawing specifically showing the layer structure of the first circuit pattern constituting the first substrate layer of FIG. 3, FIG. 5 is an enlarged view of the second substrate layer of FIG. 2, FIG. 6 is a drawing specifically showing the layer structure of the second circuit pattern constituting the second substrate layer of FIG. 5, FIG. 7 is a drawing showing the bridge substrate of FIG. 2, and FIG. 8 is a drawing for explaining the layer structure of the redistribution layer of the bridge substrate of FIG. 7.

Hereinafter, with reference to FIGS. 2 to 8, the schematic features of a circuit board (400) according to an embodiment will be described.

Referring to FIGS. 2 to 8, the circuit board (400) includes a plurality of substrate layers. Here, the plurality of substrate layers do not refer to a structure in which the plurality of substrate layers are manufactured separately from each other and then bonded to each other via a bonding layer, but rather refers to a single substrate manufactured through a general laminated manufacturing process for circuit boards.

The circuit board (400) in the first embodiment allows at least two different chips to be mounted. For example, the circuit board (400) in the first embodiment may include multiple chip mounting areas in which at least two processor chips can be mounted. Alternatively, the circuit board (400) in the first embodiment may include multiple chip mounting areas in which one processor chip and one memory chip can be mounted. Hereinafter, the circuit board (400) in the first embodiment will be described as including multiple chip mounting areas in which two different processor chips can be mounted. However, the embodiment is not limited thereto, and one processor chip and one memory chip may also be mounted on the circuit board (400).

The circuit board (400) includes a first substrate layer (100), a second substrate layer (200), and a bridge substrate (300).

The first substrate layer (100) may have a multi-layer structure. For example, the first substrate layer (100) may have at least a two-layer structure. For example, the first substrate layer (100) may include at least two insulating layers. The first substrate layer (100) may be a portion of a circuit board that is connected to a main board of an electronic device.

The second substrate layer (200) is disposed on the first surface of the first substrate layer (100). For example, the first substrate layer (100) includes a first surface and a second surface opposite the first surface. In addition, the second surface of the first substrate layer (100) may be a portion where an adhesive ball (to be described later) for bonding with an electronic device is disposed. In addition, the first surface of the first substrate layer (100) may be a surface opposite to the surface where the adhesive ball is disposed.

The second substrate layer (200) may have a multi-layer structure. For example, the second substrate layer (200) may have a structure of at least two layers. For example, the second substrate layer (200) may include at least two insulating layers. The second substrate layer (200) may be a portion of a circuit board where a plurality of chips are mounted. For example, the second substrate layer (200) includes a first surface and a second surface. In addition, the first surface of the second substrate layer (200) may be a portion where two different chips are mounted. In addition, the second surface of the second substrate layer (200) may be a surface facing the first surface of the first substrate layer (100). That is, the second surface of the second substrate layer (200) may be a surface that directly contacts the first surface of the first substrate layer (100). For example, the first surface of each of the first substrate layer (100) and the second substrate layer (200) may refer to the upper surface, and the second surface may refer to the lower surface, but the present invention is not limited thereto. For example, each of the first surfaces may refer to the lower surface, and the second surface may refer to the upper surface.

The bridge substrate (300) is disposed within the first substrate layer (100) and can be electrically connected to the second substrate layer (200). For example, the first substrate layer (100) includes a cavity (111a). And, the bridge substrate (300) can be inserted and mounted within the cavity (111a) of the first substrate layer (100). In addition, the bridge substrate (300) is electrically connected to circuit wirings constituting the second substrate layer (200), and thus, can electrically connect a plurality of chips mounted on the second substrate layer (200).

The above first substrate layer (100) may include a plurality of first insulating layers (110).

For example, the first substrate layer (100) may include a first-first insulating layer (111), a first-second insulating layer (112), and a first-third insulating layer (113). At this time, in the drawing, the first substrate layer (100) is illustrated as having a three-layer structure based on the number of insulating layers, but the embodiment is not limited thereto. For example, the first substrate layer (100) may include two insulating layers, or alternatively, may include four or more insulating layers.

The above-mentioned first insulation layer (111), first-second insulation layer (112), and first-third insulation layer (113) may include the same insulating material. For example, the first insulation layer (111), first-second insulation layer (112), and first-third insulation layer (113) may include the first insulating material. For example, the first insulation layer (111), first-second insulation layer (112), and first-third insulation layer (113) may be formed of a prepreg. The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet, such as a glass fabric woven with glass fiber yarn, with an epoxy resin or the like, and then performing thermal compression. However, the embodiment is not limited thereto, and the prepreg constituting the 1-1 insulating layer (111), the 1-2 insulating layer (112), and the 1-3 insulating layer (113) may include a fiber layer in the form of a fabric sheet woven with carbon fiber yarn.

For example, the first-first insulating layer (111), the first-second insulating layer (112), and the first-third insulating layer (113) may each include a resin and reinforcing fibers disposed within the resin. The resin may be an epoxy resin, but is not limited thereto. The resin is not particularly limited to an epoxy resin, and for example, may include at least one epoxy group in the molecule, or alternatively, may include at least two epoxy groups, or alternatively, may include at least four epoxy groups. In addition, the resin (110) may include a naphthalene group, and may be, for example, an aromatic amine type, but is not limited thereto. For example, the resin may include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, phenol novolac type epoxy resin, alkylphenol novolac type epoxy resin, biphenyl type epoxy resin, aralkyl type epoxy resin, dicyclopentadiene type epoxy resin, naphthalene type epoxy resin, naphthol type epoxy resin, epoxy resin of a condensation product of phenols and aromatic aldehydes having a phenolic hydroxyl group, biphenyl aralkyl type epoxy resin, fluorene type epoxy resin, xanthene type epoxy resin, triglycidyl isocyanurate, rubber-modified epoxy resin, and phosphorous epoxy resin, and may include naphthalene type epoxy resin, bisphenol A type epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin, rubber-modified epoxy resin, and phosphorous epoxy resin. In addition, the reinforcing fibers may be glass fibers, carbon fibers, aramid fibers (e.g., organic materials of the aramid series), nylon, inorganic materials of the silica series, or inorganic materials of the titania series. The reinforcing fibers may be arranged in a form that intersects each other in a planar direction within the resin.

Meanwhile, the above glass fiber, carbon fiber, aramid fiber (e.g., an organic material of the aramid series), nylon, an inorganic material of the silica series, or an inorganic material of the titania series can be used.

Meanwhile, the 1-1 insulating layer (111) may be the 1-1 outermost insulating layer disposed at the first outermost side among the first substrate layer (100). In addition, the 1-3 insulating layer (113) may be the 1-2 outermost insulating layer disposed at the second outermost side opposite the first outermost side among the first substrate layer (100). In addition, the 1-2 insulating layer (112) may be the first inner insulating layer disposed at the inner side among the first substrate layer (100). In addition, when the first substrate layer (100) has a layer structure of four or more layers, the first inner insulating layer may be composed of a plurality of layers. In addition, when the first substrate layer (100) has a layer structure of two layers, the first inner insulating layer may be omitted.

The above-mentioned 1-1 insulating layer (111), 1-2 insulating layer (112), and 1-3 insulating layer (113) may each have a thickness (T1) in the range of 20 µm to 60 µm. For example, the thickness (T1) of the 1-1 insulating layer (111), 1-2 insulating layer (112), and 1-3 insulating layer (113) may each satisfy a range of 25 µm to 57 µm. For example, the thickness (T1) of the 1-1 insulating layer (111), 1-2 insulating layer (112), and 1-3 insulating layer (113) may each satisfy a range of 30 µm to 55 µm. The thickness of each insulating layer may correspond to a distance between circuit patterns. For example, the thickness of the 1-1 insulating layer (111) may mean the distance from the lower surface of the 1-1 circuit pattern (121) to the upper surface of the 1-2 circuit pattern (122). For example, the thickness of the 1-2 insulating layer (112) may mean the distance from the lower surface of the 1-2 circuit pattern (122) to the upper surface of the 1-3 circuit pattern (123). For example, the thickness of the 1-3 insulating layer (113) may mean the distance from the lower surface of the 1-3 circuit pattern (123) to the upper surface of the 1-4 circuit pattern (124).

Among the first substrate layers (100), a cavity (111a) may be formed in the insulating layer disposed at the first outermost side. For example, the 1-1 insulating layer (111) disposed at the uppermost side of the first substrate layer (100) may include a cavity (111a). The cavity (111a) may be formed penetrating the 1-1 insulating layer (111). For example, the cavity (111a) may be formed penetrating the first surface and the second surface of the 1-1 insulating layer (111). Accordingly, a part of the 1-2 circuit pattern (122) formed on the second surface or the lower surface of the 1-1 insulating layer (111) may be exposed through the cavity (111a). This will be described in detail below. The cavity (111a) may provide a space within the first substrate layer (100) into which a bridge substrate (300) may be inserted. For example, the cavity (111a) may provide a space for embedding a bridge substrate (300) within the first substrate layer (100).

The width of the cavity (111a) may be greater than the width of the bridge substrate (300). For example, the width of the cavity (111a) may be 105% to 180% of the width of the bridge substrate (300). For example, the width of the cavity (111a) may be 110% to 170% of the width of the bridge substrate (300). For example, the width of the cavity (111a) may be 112% to 160% of the width of the bridge substrate (300). If the width of the cavity (111a) is less than 105% of the width of the bridge substrate (300), a problem may occur in which the bridge substrate (300) is not stably placed within the cavity (111a) due to an error in the processing of the cavity (111a). If the width of the cavity (111a) is less than 105% of the bridge substrate (300), the bridge substrate (300) may be damaged by the glass fiber constituting the first-first insulating layer (111). If the width of the cavity (111a) is greater than 180% of the bridge substrate (300), the volume of the first substrate layer (100) in the width direction may increase.

The first substrate layer (100) may include a first circuit pattern (120) arranged on the surface of each insulating layer.

At this time, the circuit pattern of the first substrate layer (100) may have an ETS (Embedded Trace Substrate) structure. For example, among the circuit patterns of the first substrate layer (100), the circuit pattern arranged on the first outermost side may have a structure embedded in the insulating layer, and the circuit pattern arranged on the second outermost side opposite to the first outermost side may have a structure protruding above the surface of the insulating layer.

For example, the first substrate layer (100) includes a 1-1 circuit pattern (121) disposed on a first surface of a 1-1 insulating layer (111). The 1-1 circuit pattern (121) may have an ETS structure. For example, the 1-1 circuit pattern (121) may have a structure embedded in the 1-1 insulating layer (111). For example, the first surface of the 1-1 circuit pattern (121) may be located on the same plane as the first surface of the 1-1 insulating layer (111). For example, the upper surface of the 1-1 circuit pattern (121) may be located on the same plane as the upper surface of the 1-1 insulating layer (111). In addition, the side surface and the lower surface of the 1-1 circuit pattern (121) may be covered by the 1-1 insulating layer (111).

That is, the 1-1 circuit pattern (121) is a circuit pattern that is most vertically adjacent to the second substrate layer (200) among the first circuit patterns (120) disposed on the first substrate layer (100). In addition, the 1-1 circuit pattern (121) has an ETS structure. That is, the 1-1 circuit pattern (121) is a pattern manufactured through an ETS method, and thus can be embedded in the first surface of the 1-1 insulating layer (111). Since this ETS structure has a structure in which the circuit pattern is embedded in the insulating layer, compared to the comparative example in which the circuit pattern is manufactured in a protruding structure on the insulating layer, it is possible to miniaturize the circuit pattern. Accordingly, in the embodiment, the line width or gap difference between the second circuit pattern (220) disposed on the second substrate layer (200) and the first circuit pattern (120) can be minimized. That is, the second circuit pattern (220) of the second substrate layer (200) may be a finer pattern than the first circuit pattern (120), as described below. For example, the line width or/and spacing of the second circuit pattern (220) may be smaller than the line width or/and spacing of the first circuit pattern (120).

At this time, if the 1-1 circuit pattern (121) arranged most adjacent to the second circuit pattern (220) has a protruding structure corresponding to a SAP structure or an MSAP structure, signal transmission loss may occur due to a numerical difference in line width between the second circuit pattern (220) and the 1-1 circuit pattern (121).

Accordingly, in the embodiment, the 1-1 circuit pattern (121) has an ETS structure. Therefore, in the embodiment, the difference in numerical values (e.g., line width and spacing) between the 1-1 circuit pattern (121) and the second circuit pattern (220) can be minimized. Accordingly, in the embodiment, the signal transmission loss that may occur due to the numerical difference between the second circuit pattern and the 1-1 circuit pattern (121) can be minimized. Furthermore, in the embodiment, the numerical difference between the first circuit pattern and the second circuit pattern is additionally minimized through the layer-by-layer numerical change of the second circuit pattern (220) described below.

The first substrate layer (100) includes a first-second circuit pattern (122) arranged on the second surface of the first-first insulating layer (111). The first-second circuit pattern (122) may protrude downward from the second surface or lower surface of the first-first insulating layer (111). In addition, the side surface and lower surface of the first-second circuit pattern (122) may be covered by the first-second insulating layer (112).

The first-second circuit pattern (122) is arranged on the second surface or lower surface of the first-first insulating layer (111), and at least a portion thereof may be exposed through the cavity (111a). For example, the first-second circuit pattern (122) may include a pad portion (122a) arranged in an area overlapping the cavity (111a) in the thickness direction.

At least a portion of the above pad portion (122a) overlaps the cavity (111a) in the thickness direction, and thus the first surface can be exposed through the cavity (111a).

For example, the first surface or upper surface of the pad portion (122a) includes a first portion (a) covered by the first-first insulating layer (111) without overlapping with the lower portion of the cavity (111a) in the thickness direction. In addition, the first surface or upper surface of the pad portion (122a) includes a second portion (b, c) that overlaps with the cavity (111a) in the thickness direction and is exposed through the cavity (111a).

At this time, the pad portion (122a) may be a pad used as a laser stopper in the process of forming the cavity (111a) in the 1-1 insulating layer (111).

Additionally, the pad portion (122a) may be a mounting pad for mounting the bridge substrate (300).

In addition, the pad portion (122a) may be a heat dissipation pad for dissipating heat generated from the bridge substrate (300). That is, as described above, the pad portion (122a) in the embodiment may provide various functions.

Meanwhile, the second part of the pad portion (122a) includes a 2-1 part (b) where the adhesive layer (360) of the bridge substrate (300) is disposed, and a 2-2 part (c) other than the 2-1 part (b). The 2-1 part (b) provides a space where the adhesive layer (360) is disposed, and where the bridge substrate (300) is stably seated. In addition, the 2-2 part (c) may be covered by the insulating layer of the second substrate layer (200). That is, the cavity (111a) has a width greater than that of the bridge substrate (300). Accordingly, when the bridge substrate (300) is inserted into the cavity (111a), a free space may exist between the cavity (111a) and the bridge substrate (300). And, the 2-2 part (c) of the pad part (122a) can be exposed through the free space. In addition, the free space can be filled by the 2-1 insulating layer (211) in the process of forming the second substrate layer (200). Accordingly, the 2-2 part (c) of the pad part (122a) can be covered by the 2-1 insulating layer (211).

In addition, the first substrate layer (100) includes a 1-3 circuit pattern (123) arranged on the second surface or lower surface of the 1-2 insulating layer (112). The 1-3 circuit pattern (123) may protrude downward from the second surface or lower surface of the 1-2 insulating layer (112). In addition, the side surface and lower surface of the 1-3 circuit pattern (123) may be covered by the 1-3 insulating layer (113).

The first substrate layer (100) includes a first-fourth circuit pattern (124) arranged on the second surface or lower surface of the first-third insulating layer (113). The first-fourth circuit pattern (124) may protrude downward from the second surface or lower surface of the first-third insulating layer (113).

The first circuit pattern (120) including the first-first circuit pattern (121), the first-second circuit pattern (122), the first-third circuit pattern (123), and the first-fourth circuit pattern (124) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the first circuit pattern (120) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. Preferably, the first circuit pattern (120) may be formed of copper (Cu) which has high electrical conductivity and is relatively inexpensive.

Each of the first-first circuit pattern (121), the first-second circuit pattern (122), the first-third circuit pattern (123), and the first-fourth circuit pattern (124) may have a thickness in the range of 7 μm to 20 μm. For example, each of the first-first circuit pattern (121), the first-second circuit pattern (122), the first-third circuit pattern (123), and the first-fourth circuit pattern (124) may have a thickness in the range of 9 μm to 17 μm. Each of the first-first circuit pattern (121), the first-second circuit pattern (122), the first-third circuit pattern (123), and the first-fourth circuit pattern (124) may have a thickness in the range of 10 μm to 13 μm. When the thickness of each of the first circuit patterns (120) is less than 7 μm, the resistance of the first circuit pattern may increase. If the thickness of each of the first circuit patterns (120) exceeds 17 μm, it may be difficult to implement the micropattern required in the first substrate layer.

The first circuit pattern (120) including the first-first circuit pattern (121), the first-second circuit pattern (122), the first-third circuit pattern (123), and the first-fourth circuit pattern (124) includes pads and traces. The pads may include via pads connected to vias, core pads, or BGA pads on which adhesive balls (to be described later) connected to a main board of an electronic device are placed. In addition, the traces may refer to long line-shaped wiring that transmits electrical signals while being connected to the pads. The pads (specifically, via pads) of the first circuit pattern (120) may have a width in the range of 20 μm to 50 μm. The pads of the first circuit pattern (120) may have a width in the range of 22 μm to 40 μm. The pads of the first circuit pattern (120) may have a width in the range of 25 μm to 35 μm. For example, the first substrate layer (100) includes first vias arranged within each insulating layer. At this time, the first insulating layer (110) is formed of a prepreg including reinforcing fibers. Accordingly, the first vias in the first insulating layer (110) have a size of at least 15 μm or more. Accordingly, the pads of the first circuit pattern (120) may have a width greater than the width of the first vias in order to be connected to the first vias.

Meanwhile, the traces of the first circuit pattern (120) may have a specific line width and a specific spacing. For example, the line width of the traces of the first circuit pattern (120) may have a range of 6 μm to 20 μm. For example, the line width of the traces of the first circuit pattern (120) may have a range of 7 μm to 15 μm. For example, the line width of the traces of the first circuit pattern (120) may have a range of 8 μm to 12 μm. In addition, the spacing between the traces of the first circuit pattern (120) may have a range of 6 μm to 20 μm. For example, the spacing between the traces of the first circuit pattern (120) may have a range of 7 μm to 15 μm. For example, the spacing between the traces of the first circuit pattern (120) may have a range of 8 μm to 12 μm.

Additionally, the first substrate layer (100) includes a first via (130) disposed in the first insulating layer (110). The first via (130) may be formed to penetrate one first insulating layer, or alternatively, may be formed to commonly penetrate at least two first insulating layers.

The first via (130) includes a first-first via (131) penetrating the first-first insulating layer (111). The first surface of the first-first via (131) may be connected to the lower surface of the first-first circuit pattern (121), and the second surface may be connected to the upper surface of the first-second circuit pattern (122).

The first via (130) includes a first-second via (132) penetrating the first-second insulating layer (112). The first surface of the first-second via (132) may be connected to the lower surface of the first-second circuit pattern (122), and the second surface may be connected to the upper surface of the first-third circuit pattern (123).

The first via (130) includes a first-third via (133) penetrating the first-third insulating layer (113). The first surface of the first-third via (133) may be connected to the lower surface of the first-third circuit pattern (123), and the second surface may be connected to the upper surface of the first-fourth circuit pattern (124).

The above-described 1-1 via (131), the above-described 1-2 via (132), and the above-described 1-3 via (133) may have the same shape. For example, the above-described 1-1 via (131), the above-described 1-2 via (132), and the above-described 1-3 via (133) may have a trapezoidal shape in which the width of the first surface and the width of the second surface are different from each other. Preferably, the above-described 1-1 via (131), the above-described 1-2 via (132), and the above-described 1-3 via (133) may have a width of the upper surface smaller than the width of the lower surface.

The width of each of the first-first via (131), the first-second via (132), and the first-third via (133) can satisfy a range of 15 μm to 40 μm. The width of each of the first-first via (131), the first-second via (132), and the first-third via (133) can satisfy a range of 18 μm to 35 μm. The width of each of the first-first via (131), the first-second via (132), and the first-third via (133) can satisfy a range of 20 μm to 30 μm.

The above-described 1-1 via (131), the 1-2 via (132), and the 1-3 via (133) penetrate the first insulating layer (110) formed of a prepreg as described above. The above-described 1-1 via (131), the 1-2 via (132), and the 1-3 via (133) may be formed by filling a conductive material into the via hole penetrating the first insulating layer (110). At this time, the first insulating layer (110) includes reinforcing fibers. Accordingly, the via hole formed in the first insulating layer (110), and the 1-1 via (131), the 1-2 via (132), and the 1-3 via (133) filling the inside of the via hole may have a width of at least 15 μm. At this time, the width of each of the 1-1 via (131), the 1-2 via (132), and the 1-3 via (133) described above may refer to the width of the side with the larger width among the first and second sides of each of the 1-1 via (131), the 1-2 via (132), and the 1-3 via (133). For example, the width of each of the 1-1 via (131), the 1-2 via (132), and the 1-3 via (133) described above may refer to the width of the second side or the lower surface of each of the 1-1 via (131), the 1-2 via (132), and the 1-3 via (133).

Meanwhile, the first-first via (131), the first-second via (132), and the first-third via (133) can be formed by forming a via hole (not shown) penetrating each insulating layer (110) and filling the inside of the formed via hole with a conductive material.

The above via hole can be formed by any one of mechanical, laser, and chemical processing methods. When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When the via hole is formed by laser processing, a UV or _CO2 laser method can be used. When the via hole is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. can be used to open at least one of the plurality of insulating layers.

Meanwhile, the processing using the laser is a cutting method that focuses optical energy on a surface to melt and vaporize part of the material, thereby taking on a desired shape, and can easily process complex shapes using a computer program, and can also process composite materials that are difficult to cut using other methods.

In addition, the processing by the above laser has the advantage of a cutting diameter of at least 0.005 mm and a wide range of processable thicknesses.

For the above laser processing drill, it is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a _CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper layer and the insulating layer, and the _CO2 laser is a laser that can process only the insulating layer.

When the above via hole is formed, the inside of the via hole can be filled with a conductive material to form each via portion. The metal material forming the via portions can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material can use any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

Meanwhile, the first circuit pattern (120) and the first via (130) may have a multi-layer structure. However, in the embodiment, one of the first circuit patterns (120) has an ETS structure, and accordingly, the circuit pattern of the ETS structure may have a different layer structure from other circuit patterns.

For example, the 1-1 circuit pattern (121) may have a different layer structure from the 1-2 circuit pattern (122) and the 1-3 circuit pattern (123). For example, the number of layers of the 1-1 circuit pattern (121) may be different from the number of layers of the 1-2 circuit pattern (122) and the 1-3 circuit pattern (123). For example, the number of layers of the 1-1 circuit pattern (121) may be smaller than the number of layers of the 1-2 circuit pattern (122) and the 1-3 circuit pattern (123).

For example, the 1-1 circuit pattern (121) may include only an electroplating layer. In contrast, the 1-2 circuit pattern (122) may include a seed layer (122-1) and an electroplating layer (122-2). In addition, the 1-3 circuit pattern (123) may include a seed layer (123-1) and an electroplating layer (123-2). That is, the 1-1 circuit pattern (121) is the first pattern to be formed in the manufacturing process of the first substrate layer, and thus, the seed layer of the 1-1 circuit pattern (121) is removed in the final process.

Meanwhile, the 1-1 via (131) includes a seed layer (131-1) and an electrolytic plating layer (131-2) corresponding to the 1-2 circuit pattern (122). In addition, the 1-2 via (132) includes a seed layer (132-1) and an electrolytic plating layer (132-2) corresponding to the 1-3 circuit pattern (123).

The first substrate layer (100) includes a protective layer (140). The protective layer (140) can protect the insulating layer and circuit pattern disposed on the outermost side of the first substrate layer (100). For example, the protective layer (140) can be disposed on the second surface of the 1-3 insulating layer (113). The protective layer (140) can include an opening (not shown) that exposes at least a portion of the lower surface of the 1-4 circuit pattern (124) disposed on the second surface of the 1-3 insulating layer (113).

Accordingly, the lowermost side of the first substrate layer (100) may include a protection area (PP) covered by the first protection layer (140) and an open area (OP) exposed through an opening of the first protection layer (140). In addition, at least a portion of the lower surface of the 1-4 circuit pattern (124) may be exposed to the outside through the open area (OP).

In addition, the uppermost side of the first substrate layer (100) may be a first bonding region or a first stacking region (AR1). That is, second insulating layers constituting the second substrate layer (200) may be stacked on the uppermost side of the first substrate layer (100). At this time, a cavity (111a) may be formed in the first bonding region or the first stacking region (AR1) on the uppermost side of the first substrate layer (100) as described above.

As described above, the first substrate layer (100) constituting the circuit board (300) in the embodiment has a multi-layer structure. In addition, the first substrate layer (100) includes a plurality of insulating layers made of prepreg so as to impart rigidity to the circuit board (300). The first substrate layer (100) can transmit a signal transmitted from the second substrate layer (200) to the main board of the electronic device. Accordingly, the first substrate layer (100) can have a standard corresponding to the specifications of the main board of the electronic device (e.g., number of pads, spacing between pads, etc.).

Meanwhile, the second substrate layer (200) is disposed on the first substrate layer (100). Specifically, the second substrate layer (200) is laminated on the first surface of the first substrate layer (100). For example, the plurality of insulating layers constituting the second substrate layer (200) may be sequentially laminated on the 1-1 insulating layer (111) disposed on the uppermost side among the first insulating layers (110) constituting the first substrate layer (100).

The second substrate layer (200) provides a mounting area in which at least two chips of different types are mounted. In addition, the second substrate layer (200) can transmit a signal transmitted from the first substrate layer (100) to the at least two mounted chips, or transmit a signal acquired or processed by the at least two chips to the first substrate layer (100). In addition, the connection between the at least two chips can be made by a bridge substrate (300) connected to the second substrate layer (200).

The lowermost side of the second substrate layer (200) is a portion laminated on the uppermost side of the first substrate layer (100). For example, the second substrate layer (200) may include a second laminated region (AR2) laminated on the first laminated region (AR1) of the first substrate layer (100).

Additionally, the uppermost side of the second substrate layer (200) may include a chip mounting area where multiple chips are mounted. For example, the uppermost side of the second substrate layer (200) may include a chip mounting area (R1) where chips are mounted, and an area (R2) other than the chip mounting area (R1).

In addition, the chip mounting area (R1) may include a first mounting area (MR1) in which a first chip is mounted, a second mounting area (MR2) in which a second chip of a different type from the first chip is mounted, and a separation area (SR) between the first mounting area (MR1) and the second mounting area (MR2).

At this time, the embodiment provides a chip mounting area in which a plurality of first and second chips of different types can be mounted on a single circuit board (300). At this time, the first and second chips may be first and second processor chips separated according to function from an application processor integrated into a single chip in the comparative example.

For example, in the embodiment, the first mounting region (MR1) may be a region where a first processor chip is mounted, and the second mounting region (MR2) may be a region where a second processor chip of a different type from the first processor chip is mounted. For example, the first processor chip may be any one of an application processor (AP) chip such as a central processor (e.g., a CPU), a graphic processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc. The second processor chip may be a processor chip of a different type from the first processor chip among an application processor (AP) chip such as a central processor (e.g., a CPU), a graphic processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, etc. For example, the first processor chip may be a central processor chip, and the second processor chip may be a graphic processor chip. That is, the circuit board of the embodiment may be a circuit board for die splitting that separates the application processor by function and mounts separate processor chips for each of the separated functions on one substrate.

Meanwhile, recently, as the functions required for application processors have increased, there has been a demand for separate processor chips for each function, and for circuit boards on which these processor chips can be mounted. At this time, even when the application processor is divided into two processor chips for each function, the number of terminals (input/output) provided on each processor chip is increasing. At this time, unlike in the comparative example where all functions are processed by a single application processor chip, when the processor chip is divided into at least two, each processor chip must be electrically connected to each other to exchange signals with each other.

At this time, if the spacing between each of the processor chips is large, a fine pattern such as that of the embodiment may not be required. However, if the spacing between each of the processor chips is large, the communication speed for signal exchange between them may decrease. In addition, if the spacing between each of the processor chips is large, the power consumption required for communication increases. In addition, if the spacing between each of the processor chips is large, the length of the trace connecting each of the processor chips also increases, which causes a problem of increased signal transmission loss due to vulnerability to noise.

That is, the spacing between the processor chips must be 150 μm or less for reliability. For example, the spacing between the processor chips must be 120 μm or less for reliability. For example, the spacing between the processor chips must be 100 μm or less for reliability.

Therefore, in order to connect all the wiring between the first processor chip and the second processor chips within the limited space as described above, the circuit pattern must be refined to a specific line width and a specific spacing as described above.

In addition, conventionally, there were X connection wires between the first processor chip and the second processor chip. In addition, when there are X connection wires, the level of refinement of the circuit pattern may be different from that of the embodiment within the limited space as described above.

On the other hand, due to recent reasons such as 5G, Internet of Things (IoT), increased picture quality, and increased communication speed, the number of terminals within the first processor chip and the second processor chip is gradually increasing. Accordingly, the connection wiring between the first processor chip and the second processor chip may be at least twice (2X), three times (3X), or ten times (10X) longer than the conventional wiring.

Accordingly, in order to mount the first processor chip and the second processor chip on a single circuit board while minimizing the gap between them and to connect the first processor chip and the second processor chip to each other within a limited space, ultra-fine circuit patterns included in the second substrate layer (200) are required.

However, there is a limit to the miniaturization of the second circuit pattern (220) formed on the second substrate layer (200). Accordingly, in the embodiment, a bridge substrate (300) is placed within the cavity (111a) of the first substrate layer (100), and the bridge substrate (300) is used to enable connection between the first processor chip and the second processor chip.

The second substrate layer (200) may have a multi-layer structure. The second substrate layer (200) may have at least two layers based on the number of insulating layers.

For example, the second substrate layer (200) may include a second insulating layer (210).

The second insulating layer (210) may include a second-first insulating layer (211) and a second-second insulating layer (212). However, although the number of layers of the second insulating layer (210) constituting the second substrate layer (200) is illustrated as two in the drawing, the present invention is not limited thereto. For example, the number of layers of the second insulating layer (210) may be three or more.

The 2-1 insulating layer (211) is disposed on the first surface of the first substrate layer (100). Specifically, the 2-1 insulating layer (211) is disposed on the first surface or upper surface of the 1-1 insulating layer (111) of the first substrate layer (100). The second surface or lower surface of the 2-1 insulating layer (211) may be in direct contact with the first surface or upper surface of the 1-1 insulating layer (111). In addition, the second surface or lower surface of the 2-1 insulating layer (211) may be in direct contact with the first surface or upper surface of the 1-1 circuit pattern (121) embedded in the 1-1 insulating layer (111). For example, the 2-1 insulating layer (211) may be disposed to cover the 1-1 circuit pattern (121) and the 1-1 insulating layer (111). This means that the first substrate layer (100) and the second substrate layer (200) are not bonded through separate adhesive balls, but the 2-1 insulating layer (211), which is the lowermost layer of the second substrate layer (200), is directly laminated on the 1-1 insulating layer (111), which is the uppermost layer of the first substrate layer (100).

At this time, the second surface or lower surface of the 2-1 insulating layer (211) can be divided into a plurality of regions. For example, the second surface or lower surface of the 2-1 insulating layer (211) includes an overlap region that overlaps with the 1-1 insulating layer (111). In addition, the overlap region of the 2-1 insulating layer (211) can include a first overlap region (OR1) that overlaps with the cavity (111a) of the 1-1 insulating layer (111) in the thickness direction, and a second overlap region (OR2) other than the first overlap region (OR1).

The lower surface of the first overlap region (OR1) of the 2-1 insulating layer (211) may be positioned on a different plane from the lower surface of the second overlap region (OR2). For example, the lower surface of the first overlap region (OR1) of the 2-1 insulating layer (211) may be positioned lower than the lower surface of the second overlap region (OR2). For example, the 2-1 insulating layer (211) is formed to fill the cavity (111a) of the 1-1 insulating layer (111). Accordingly, the 2-1 insulating layer (211) may be formed to surround the bridge substrate (300) disposed within the cavity (111a). Accordingly, the lower surface of the first overlap region (OR1) of the 2-1 insulating layer (211) may be in direct contact with the 2-2 portion (c) of the pad portion (122a).

In the embodiment, the 2-1 insulating layer (211) is formed by filling the cavity (111a) of the 1-1 insulating layer (111) as described above. Accordingly, in the embodiment, the contact area between the 1-1 insulating layer (111) and the 2-1 insulating layer (211) can be increased. Accordingly, in the embodiment, the bonding strength between the 1-1 insulating layer (111) and the 2-1 insulating layer (211) can be improved, and thus the problem of the 2-1 insulating layer (211) being peeled off from the 1-1 insulating layer (111) can be solved. For example, the 1-1 insulating layer (111) and the 2-1 insulating layer (211) include different insulating materials, and thus a problem in the bonding strength may occur. Accordingly, in the embodiment, the 2-1 insulating layer (211) is arranged within the cavity (111a) as described above. Accordingly, in the embodiment, the bonding strength between the 1-1 insulating layer (111) and the 2-1 insulating layer (211) can be increased, thereby improving reliability.

The above 2-2 insulating layer (212) is arranged on the first surface or upper surface of the 2-1 insulating layer (211).

The above 2-2 insulating layer (212) may refer to an insulating layer disposed at the uppermost side of the second substrate layer (200). For example, when the insulating layer of the second substrate layer (200) has a layer structure of three or more layers, at least one inner insulating layer may be additionally formed between the 2-1 insulating layer (211) and the 2-2 insulating layer (212).

In one embodiment, the second insulating layer (210) including the second-1 insulating layer (211) and the second-2 insulating layer (212) may include a second insulating material. For example, the second insulating layer (210) may include a second insulating material that is different from the first insulating material constituting the first insulating layer (110).

Preferably, the second insulating layer (210) may not include reinforcing fibers. For example, the second insulating layer (210) may include a photocurable resin or a photosensitive resin. For example, the second insulating layer (210) may include PID (Photo Imageable Dielectics). As another example, the second insulating layer (210) may include ABF (Aginomoto Build-up Film).

In an embodiment, the second insulating layer (210) constituting the second substrate layer (200) includes an insulating material such as ABF or PID, thereby enabling the formation of a relatively fine circuit pattern and via compared to the first substrate layer (100). For example, when the second insulating layer (210) includes a photocurable resin such as PID, a via hole in the second insulating layer (210) can be formed by an exposure and development process, unlike a via hole in the first insulating layer (110). Accordingly, in the embodiment, the second insulating layer (210) is configured with a photocurable resin, thereby enabling the miniaturization of the second via (230) penetrating the second insulating layer (210), while allowing the size of the second via (230) to be easily controlled.

In addition, as described above, the number of terminals on chips has been increasing recently. Accordingly, in the embodiment, the second insulating layer (210) constituting the second substrate layer (200) is configured to include an insulating material such as ABF or PID so as to minimize the pitch of the mounting pad on which the chip is mounted.

Meanwhile, each insulating layer constituting the second insulating layer (210) may have a thickness thinner than each insulating layer constituting the first insulating layer (110). For example, the thickness (T2) of the 2-1 insulating layer (211) and the 2-2 insulating layer (212) may have a range of 8 μm to 35 μm. For example, the 2-1 insulating layer (211) and the 2-2 insulating layer (212) may have a thickness in a range of 10 μm to 30 μm. For example, the 2-1 insulating layer (211) and the 2-2 insulating layer (212) may have a thickness in a range of 11 μm to 20 μm. If the thickness of the 2-1 insulating layer (211) and the 2-2 insulating layer (212) is less than 8 μm, the second circuit pattern (220) formed on the second insulating layer (210) may not be stably protected. If the thickness of the above 2-1 insulating layer (211) and the 2-2 insulating layer (212) exceeds 35 μm, it may be difficult to miniaturize the second circuit pattern (220), and further, the thickness of the circuit board (400) may increase.

The second substrate layer (200) may include a second circuit pattern (220).

The second circuit pattern (220) may be placed on the first surface or upper surface of the second insulating layer (210).

For example, the second circuit pattern (220) may include the second-1 circuit pattern (221) arranged on the first surface or upper surface of the second-1 insulating layer (211). For example, the second-1 circuit pattern (221) may protrude above the first surface or upper surface of the second-1 insulating layer (211). The side surface and upper surface of the second-1 circuit pattern (221) may be covered by the second-2 insulating layer (212).

The second circuit pattern (220) may include a second-second circuit pattern (222). The second-second circuit pattern (222) may be arranged on the first surface or the upper surface of the second-second insulating layer (212). The second-second circuit pattern (222) may protrude above the first surface or the upper surface of the second-second insulating layer (212).

The second circuit pattern (220) may have a different layer structure from the first circuit pattern (120). For example, the second circuit pattern (220) may have a greater number of layers than the first circuit pattern (120). However, although the second circuit pattern (220) has a greater number of layers than the first circuit pattern (120), it may have a thinner thickness than the first circuit pattern (120).

The second-first circuit pattern (221) and the second-second circuit pattern (222) constituting the second circuit pattern (220) may each have a three-layer structure. For example, the second-first circuit pattern (221) and the second-second circuit pattern (222) may each include a first plating layer (220-1), a second plating layer (220-2), and a third plating layer (220-3). The first plating layer (220-1) and the second plating layer (220-2) may be seed layers.

The first plating layer (220-1) may be a titanium (Ti) layer formed through a sputtering process. The first plating layer (220-1) may have a thickness of 0.01 μm to 0.15 μm. For example, the first plating layer (220-1) may have a thickness of 0.03 μm to 0.12 μm. For example, the first plating layer (220-1) may have a thickness of 0.05 μm to 0.10 μm. The first plating layer (220-1) may be a first seed layer formed to increase the bonding strength between the second plating layer (220-2), the third plating layer (220-3), and the second insulating layer (220).

The second plating layer (220-2) may be a copper (Cu) layer formed through a sputtering process. The second plating layer (220-2) may have a thickness of 0.01 µm to 0.35 µm. For example, the second plating layer (220-2) may have a thickness of 0.05 µm to 0.32 µm. For example, the second plating layer (220-2) may have a thickness of 0.1 µm to 0.3 µm. The second plating layer (220-2) may be a second seed layer formed for electrolytic plating of the third plating layer (220-3). In an embodiment, the sum of the thicknesses of the first plating layer (220-1) and the second plating layer (220-2) may be 0.5 µm or less. Preferably, the sum of the thicknesses of the first plating layer (220-1) and the second plating layer (220-2) may be 0.4 µm or less. More preferably, the sum of the thicknesses of the first plating layer (220-1) and the second plating layer (220-2) may be 0.3 µm or less. If the sum of the thicknesses of the first plating layer (220-1) and the second plating layer (220-2) exceeds 0.5 µm, it may be difficult to miniaturize the second circuit pattern (220). Specifically, the manufacturing process of the second circuit pattern (220) includes a seed layer removal process of etching and removing the first plating layer (220-1) and the second plating layer (220-2). At this time, as the thickness of the first plating layer (220-1) and the second plating layer (220-2) increases, the etching amount in the seed layer process increases, and accordingly, miniaturization of the overall second circuit pattern (220) becomes difficult.

In the embodiment, the seed layer of the second circuit pattern (220) includes a first plating layer (220-1) and a second plating layer (220-2). At this time, the first plating layer (220-1) and the second plating layer (220-2) are formed by a sputtering process, and thus the thickness of the first circuit pattern (120) can be made thinner than that of the seed layer, and thus the second circuit pattern (220) can be made finer.

The third plating layer (220-3) may be an electroplated layer formed by electroplating the second plating layer (220-2) as a seed layer. The third plating layer (220-3) may have a thickness in the range of 2 µm to 12 µm. The third plating layer (220-3) may have a thickness in the range of 3 µm to 11 µm. The third plating layer (220-3) may have a thickness in the range of 4 µm to 10 µm.

If the thickness of the third plating layer (220-3) is less than 2 µm, the third plating layer (220-3) is also etched during the seed layer etching process, making it difficult to normally implement the second circuit pattern (220). If the thickness of the third plating layer (220-3) is greater than 12 µm, it may be difficult to refine the second circuit pattern (220).

The second circuit patterns (220) having the layer structure as described above may each have a thickness in the range of 3 µm to 13 µm. The second circuit patterns (220) having the layer structure as described above may each have a thickness in the range of 4 µm to 12 µm. The second circuit patterns (220) having the layer structure as described above may each have a thickness in the range of 5 µm to 11 µm. If the thickness of the second circuit patterns (220) is less than 5 µm, the resistance of the second circuit patterns may increase, which may lower reliability in connection with the first and second processor chips. If the thickness of each of the first circuit patterns (220) exceeds 11 µm, it may be difficult to implement a fine pattern required in the second substrate layer.

The second substrate layer (200) includes a second via (230) disposed on a second insulating layer (210). The second via (230) may be formed penetrating one second insulating layer, or alternatively, may be formed penetrating two or more second insulating layers.

The above second via (230) includes a second-1 via (231) penetrating the second-1 insulating layer (211).

The above 2-1 via (231) may have a first surface connected to the lower surface of the 2-1 circuit pattern (221), and a second surface connected to the upper surface of the pad of the 1-1 circuit pattern (121) or the bridge substrate (300).

Specifically, the 2-1 via (231) includes a first sub-2-1 via (231a) connected to the first surface or upper surface of the 1-1 circuit pattern (121) of the first substrate layer (100). In addition, the 2-1 via (231) includes a second sub-2-1 via (231b) connected to the upper surface of the pad of the bridge substrate (300).

The width of the first sub-2-1 via (231a) may be different from the width of the second sub-2-1 via (231b). In addition, the height or thickness of the first sub-2-1 via (231a) may be different from the height or thickness of the second sub-2-1 via (231b).

As described above, the first sub-2-1 via (231a) is connected to the 1-1 circuit pattern (121) of the first substrate layer (100), and thus may have a width corresponding to the 1-1 circuit pattern (121). In contrast, the second sub-2-1 via (231b) is connected to the pad of the bridge substrate (300), and thus may have a width corresponding to the pad of the bridge substrate (300). Specifically, the width of the first sub-2-1 via (231a) may be greater than the width of the second sub-2-1 via (231b).

Furthermore, in an embodiment, the height or thickness of the first sub-2-1 via (231a) may be greater than the height or thickness of the second sub-2-1 via (231b). Conversely, in an embodiment, the height or thickness of the first sub-2-1 via (231a) may be less than the height or thickness of the second sub-2-1 via (231b). That is, when the bridge substrate (300) is inserted into the cavity (111a), it may be difficult to align the upper surface of the pad of the bridge substrate (300) and the upper surface of the first-1 circuit pattern (121) on the same plane. Accordingly, when the bridge substrate (300) is inserted into the cavity (111a), the upper surface of the pad of the bridge substrate (300) may be positioned higher than the upper surface of the 1-1 circuit pattern (121), or may be positioned lower than the upper surface thereof. Accordingly, the thickness or height of the second sub-2-1 via (231b) may be greater than the thickness or height of the first sub-2-1 via (231a), or may be smaller than the thickness or height thereof. However, in the embodiment, the difference between the height or thickness of the first sub-2-1 via (231a) and the height or thickness of the second sub-2-1 via (231b) is minimized, and reliability is improved accordingly. This can be achieved by the structural features of the bridge substrate (300) to be described later.

The second via (230) includes a second-second via (232) penetrating the second-second insulating layer (212). The second-second via (232) may have a first surface connected to the lower surface of the second-second circuit pattern (222), and a second surface connected to the upper surface of the second-first circuit pattern (221).

The above-mentioned 2-1 via (231) and the above-mentioned 2-2 via (232) may have the same shape. For example, the above-mentioned 2-1 via (231) and the above-mentioned 2-2 via (232) may have a trapezoidal shape in which the width of the first surface and the width of the second surface are different from each other. Preferably, the width of the upper surface of the above-mentioned 2-1 via (231) and the above-mentioned 2-2 via (232) may be greater than the width of the lower surface.

The above-described 2-1 via (231) and the above-described 2-2 via (232) may have different widths. For example, among the above-described 2-1 via (231) and the above-described 2-2 via (232), the via that is located closest to the first substrate layer (100) may have the largest width. For example, among the above-described 2-1 via (231) and the above-described 2-2 via (232), the via that is located farthest from the first substrate layer (100) (e.g., the via that is closest to a processor chip to be placed later) may have the smallest width. The width of the 2-1 via (231) and the 2-2 via (232) described below may mean the width of the first surface having a wider width among the width of the first surface and the width of the second surface of each of the 2-1 via (231) and the 2-2 via (232).

The above-mentioned 2-1 via (231) may be smaller than the width of the first via (130) constituting the first substrate layer (100).

That is, the width of each of the first sub-2-1 via (231a) and the second sub-2-1 via (231b) constituting the 2-1 via (231) may be smaller than the width of the first via (130). However, the width of the first sub-2-1 via (231a) may be larger than the width of the second sub-2-1 via (231b). For example, the width of the first sub-2-1 via (231a) may have a value between the width of the second sub-2-1 via (231b) and the width of the first via (130).

Additionally, the second-second via (232) may be smaller than the width of the first via (130) and the first sub-second-first via (231a). For example, the second-second via (232) may correspond to the width of the second sub-second-first via (231b).

As described above, in the embodiment, depending on the function of each of the second vias (230) constituting the second substrate layer (200), vias arranged in different layers have different widths, or vias arranged in the same layer have different widths. Accordingly, in the embodiment, it is possible to minimize signal transmission loss occurring between the processor chip and the first substrate layer, and thereby improve communication performance.

Meanwhile, the second substrate layer (200) includes a second protective layer (240). The second protective layer (240) may be a solder resist. The second protective layer (240) may be disposed on the first surface or the upper surface of the 2-2 insulating layer (212). In addition, the second protective layer (240) may include an opening (not shown) that exposes an area of the first surface or the upper surface of the 2-2 circuit pattern (222) where a chip is to be mounted.

The bridge substrate (300) is inserted into the cavity (111a) of the 1-1 insulating layer (111) of the first substrate layer (100). In addition, the bridge substrate (300) is electrically connected to the circuit wiring constituting the second substrate layer (200). For example, the bridge substrate (300) may be electrically connected to the second sub-2-1 via (230b) among the 2-1 vias (231) of the second substrate layer (200).

For example, the second sub-2-1 via (230b) may include a first via portion connected to the first processor chip and a second via portion connected to the second processor chip. In addition, the bridge substrate (300) may include a plurality of pad portions, and thus, some of the plurality of pad portions may be directly connected to the first via portion, and the remaining some of the plurality of pad portions may be directly connected to the second via portion.

The bridge substrate (300) as described above can perform die-to-die interconnection that electrically connects a plurality of processor chips mounted on a circuit board. The plurality of processor chips must be electrically connected to each other within a limited space. At this time, in order to connect the plurality of processor chips, a very dense connection circuit is required within the limited space. Accordingly, in the embodiment, a bridge substrate (300) including a high-density circuit layer is placed in the cavity (111a), and the bridge substrate (300) is used to electrically connect the plurality of processor chips mounted on the circuit board.

The above bridge substrate (300) may include an ultra-fine pattern.

The above bridge substrate (300) may include a base layer (310), an insulating layer (320) disposed on the base layer (310), a circuit layer (330) disposed on the insulating layer (320), a via layer (340) penetrating the insulating layer (320), and a pad layer (350) disposed on the outermost insulating layer of the bridge substrate (300).

The above insulating layer (320), the circuit layer (330), the via layer (340), and the pad layer (350) can be said to be a redistribution layer of the bridge substrate (300) placed on the base layer (310).

The base layer (310) can improve the bending characteristics of the bridge substrate (300). For example, the base layer (310) can support the bridge substrate (300) while enabling thermal deformation together with the first substrate layer (100) and the second substrate layer (200).

To this end, the base layer (310) may include an insulating material having elasticity. For example, the base layer (310) may have flexible characteristics. For example, the base layer (310) may include polyimide (PI). However, the embodiment is not limited thereto, and the base layer (310) may be formed of another insulating material having flexible characteristics other than the polyimide.

At this time, the base layer of a typical bridge substrate is formed of a silicon substrate.

In the embodiment, the base layer (310) is formed of polyimide having flexible properties.

Accordingly, in the embodiment, the material of the base layer (310) of the bridge substrate (300) can be changed to polyimide, which is cheaper than a silicon substrate, thereby reducing the cost of the bridge substrate (300).

In addition, in the embodiment, a circuit layer (330) and a pad layer (350) are formed on the bridge substrate (300). At this time, the pad layer (350) must be connected to the second sub-2-1 via (230b) of the second substrate layer (200) while being connected to the circuit layer (330). Accordingly, the alignment state of the pad layer (350) and the second sub-2-1 via (230b) has a great influence on the product reliability of the circuit substrate and the package substrate. At this time, in the embodiment, a transparent polyimide is used as a base layer (310) to form the circuit layer (330) and the pad layer (350), and thus, the alignment of the circuit layer (330) and the pad layer (350) can be easily achieved. In addition, in the embodiment, the accuracy of the formation position of the pad layer (350) is improved, and further, the alignment between the pad layer (350) and the second sub-2-1 via (230b) is improved, thereby improving product reliability.

In addition, in the embodiment, by forming the base layer (310) from polyimide, the bridge substrate (300) can be stably protected when the first substrate layer (100) and the second substrate layer (200) are thermally deformed.

That is, in the past, the base layer of the bridge substrate was formed of a silicon substrate. At this time, the silicon substrate has rigid characteristics. Accordingly, in the past, when the first or second substrate layer is thermally deformed, the silicon substrate does not flow together with the bridge substrate, and thus reliability issues such as breakage of the bridge substrate occur.

In contrast, in the embodiment, the base layer (310) of the bridge substrate (300) has a flexible characteristic including polyimide. Accordingly, in the embodiment, when the first substrate layer or the second substrate layer is thermally deformed, the bridge substrate (300) is allowed to flow, thereby resolving reliability issues such as breakage of the bridge substrate (300).

In addition, in the embodiment, the thickness of the bridge substrate (300) can be easily controlled by making the base layer (310) include polyimide. For example, in the past, a process of polishing the silicon substrate was required to control the thickness of the bridge substrate including a silicon substrate, and due to the difficulty of the process resulting from this, it was difficult to control the thickness of the bridge substrate to a desired thickness.

In contrast, in the embodiment, due to the characteristics of the polyimide constituting the base layer (310), its thickness can be easily adjusted, and accordingly, the overall thickness of the bridge substrate (300) can be easily controlled to correspond to the height of the cavity (111a). Accordingly, in the embodiment, it is possible to easily align the surface of the pad layer (350) of the bridge substrate (300) and the 1-1 circuit pattern (121). Accordingly, in the embodiment, it is possible to minimize the thickness or height deviation of the first sub-2-1 via (231a) and the second sub-2-1 via (230b) connected to the 1-1 circuit pattern (121), and thereby improve product reliability.

The insulating layer (320) of the bridge substrate (300) may be disposed on one surface of the base layer (310). The insulating layer (320) may be composed of multiple layers. The insulating layer (320) may include a photosensitive material, PID, but is not limited thereto. For example, the insulating layer (320) may include an organic insulating layer, such as SiO ₂ .

A circuit layer (330) and a via layer (340) are formed on the insulating layer (320) of the above bridge substrate (300). The circuit layer (330) and the via layer (340) can be formed by plating a metal material within a circuit pattern groove (not shown) or a via hole (not shown) formed by exposing and developing the insulating layer (320).

Accordingly, the circuit layer (330) of the bridge substrate (300) may include a first metal layer (331) and a second metal layer (332). The first metal layer (331) may be a metal layer formed through sputtering. To this end, the first metal layer (331) may include a titanium (Ti) layer formed through a sputtering process and a copper (Cu) layer. The titanium (Ti) layer may have a thickness of 0.01 μm to 0.15 μm. For example, the titanium (Ti) layer may have a thickness of 0.03 μm to 0.12 μm. For example, the titanium (Ti) layer may have a thickness of 0.05 μm to 0.10 μm. The copper (Cu) layer may have a thickness of 0.01 μm to 0.35 μm. For example, the copper (Cu) layer may have a thickness of 0.05 μm to 0.32 μm. For example, the copper (Cu) layer may have a thickness of 0.1 μm to 0.3 μm. The thickness of the first metal layer (331), which is the sum of the thicknesses of the titanium (Ti) and the copper (Cu) layers, may be 0.5 μm or less. Preferably, the thickness of the first metal layer (331) may be 0.4 μm or less. More preferably, the thickness of the first metal layer (331) may be 0.3 μm or less. If the thickness of the first metal layer (331) exceeds 0.5 μm, miniaturization of the circuit layer (330) may be difficult. Specifically, the process of forming the circuit layer (330) includes a seed layer removal process of removing the first metal layer (331). At this time, as the thickness of the first metal layer (331) increases, the etching amount in the seed layer process increases, and thus, miniaturization of the overall circuit layer (330) becomes difficult.

In the embodiment, the first metal layer (331) is formed by a sputtering process, and miniaturization of the circuit layer (330) may be possible.

The second metal layer (332) may be an electroplated layer formed by electroplating the first metal layer (331) as a seed layer. The second metal layer (332) may have a thickness in the range of 2 µm to 12 µm. The second metal layer (332) may have a thickness in the range of 3 µm to 11 µm. The second metal layer (332) may have a thickness in the range of 4 µm to 10 µm.

If the thickness of the second metal layer (332) is less than 2 μm, the second metal layer (332) may also be etched together in the seed layer etching process, making it difficult to normally implement the circuit layer (330). If the thickness of the second metal layer (332) is greater than 12 μm, it may be difficult to miniaturize the circuit layer (330).

The circuit layer (330) having the layer structure as described above may have a thickness in the range of 3 µm to 13 µm, respectively. The circuit layer (330) having the layer structure as described above may have a thickness in the range of 4 µm to 12 µm, respectively. The second circuit pattern (320) having the layer structure as described above may have a thickness in the range of 5 µm to 11 µm, respectively. If the thickness of the circuit layer (330) is less than 5 µm, the resistance of the circuit layer (330) may increase, thereby lowering reliability in connection with the first and second processor chips. If the thickness of the circuit layer (330) exceeds 11 µm, it may be difficult to implement a fine pattern required for the bridge substrate (300).

The circuit layer (330) may be an ultra-fine pattern. For example, the circuit layer (330) may have a line width of 5 μm or less. For example, the circuit layer (330) may have a line width of 3 μm or less. For example, the circuit layer (330) may have a line width of 2 μm or less. The circuit layer (330) may have a spacing of 5 μm or less. The spacing may refer to a spacing between traces of the circuit layer (330) arranged on the same layer. For example, the circuit layer (330) may have a spacing of 3 μm or less. For example, the circuit layer (330) may have a spacing of 2 μm or less.

Preferably, the circuit layer (330) may have a line width of 1 μm to 5 μm. The circuit layer (330) may have a line width in the range of 1.2 μm to 3 μm. The circuit layer (330) may have a line width in the range of 1.5 μm to 2 μm. If the line width of the circuit layer (330) is smaller than 1 μm, the resistance of the circuit layer (330) increases, and thus normal communication with the processor chip may be difficult. If the line width of the circuit layer (330) is larger than 5 μm, it may be difficult to implement a bridge substrate (300) for connection between a plurality of processor chips in a limited space. For example, if the line width of the circuit layer (330) is larger than 6 μm, it may be difficult to place a bridge substrate (300) including traces for connection between a plurality of processor chips in a cavity (111a) formed in a limited space.

Meanwhile, the via layer (340) of the bridge substrate (300) may also include a first metal layer (341) and a second metal layer (342) corresponding to the circuit layer (330).

Additionally, the bridge substrate (300) includes a pad layer (350) disposed on the outermost insulating layer (322). The pad layer (350) may include a first metal layer (351) and a second metal layer (352) corresponding to the circuit layer (330) and the via layer (340).

The above pad layer (350) may be a pad of a bridge substrate (200) that is directly connected to the second sub-2-1 via (230b) of the second substrate layer (200). That is, the pad layer (350) is arranged on the outermost side of the bridge substrate (300), and the upper surface of the pad layer (350) may be in direct contact with the second sub-2-1 via (230b).

Meanwhile, the cavity (111a) is filled with the 2-1 insulating layer (211), and accordingly, the bridge substrate (300) can be surrounded by the 2-1 insulating layer (211).

The bridge substrate (300) includes an adhesive layer (360) disposed on the lower surface of the base layer (310). The adhesive layer (360) can provide bonding force so that the bridge substrate (300) can be stably inserted and fixed into the cavity (111a) while being attached to the lower surface of the base layer (310). The adhesive layer (360) can be disposed on the pad portion (122a). For example, the adhesive layer (360) can be disposed on the 2-1 portion (b) of the pad portion (122a) while exposing the 2-2 portion (c) of the pad portion (122a). For example, the width of the adhesive layer (360) can be smaller than the width of the cavity (111a). For example, the width of the adhesive layer (360) may correspond to the width of the second-1 portion (b) of the second portion of the upper surface of the pad portion (122a).

Meanwhile, the thickness (T3) of the circuit board (400) in the embodiment may be smaller than the thickness (t8) of the first package (10) of the comparative example.

Specifically, the thickness (T3) of the circuit board (400) may be smaller than the thickness (t8) of the first package (10) of the comparative example. For example, when the circuit board (400) has a five-layer structure based on the number of layers of the first insulating layer of the first substrate layer (100), and the second substrate layer (200) has a three-layer structure based on the number of layers of the second insulating layer, the thickness (T3) of the circuit board (400) may be 400 μm or less. For example, when the first substrate layer (100) of the circuit board (400) has a five-layer structure based on the number of layers of the first insulating layer, and the second substrate layer (200) has a three-layer structure based on the number of layers of the second insulating layer, the thickness (T3) of the circuit board (400) may be 380 μm or less. For example, if the first substrate layer (100) of the circuit board (400) has a five-layer structure based on the number of layers of the first insulating layer, and the second substrate layer (200) has a three-layer structure based on the number of layers of the second insulating layer, the thickness (T3) of the circuit board (400) may be 360 μm or less.

As described above, the embodiment includes a first substrate layer (100) and a second substrate layer (200).

The first substrate layer (100) includes a prepreg, thereby maintaining the rigidity of the circuit board (400) and improving warpage characteristics, thereby enhancing product reliability. Furthermore, the first substrate layer (100) is connected to a main board of an electronic device, and thus includes a first circuit pattern (120) and first vias (130) having specifications corresponding to connection pads (not shown) of the electronic device.

Furthermore, the second substrate layer (200) includes ABF or PID, thereby improving connection reliability with multiple processor chips.

Furthermore, the second circuit pattern (220) and the second via (230) disposed on the second substrate layer (200) may have a width that gradually increases as they approach the first substrate layer (100). Accordingly, in the embodiment, signal transmission loss between the first substrate layer (100) and the second substrate layer (200) can be minimized, and further, communication performance can be improved.

In addition, in the embodiment, a bridge substrate (300) is inserted into the first substrate layer (100), and thus the pad layer (350) of the bridge substrate (300) and the second via (230) of the second substrate layer (200) are directly connected to each other. Accordingly, in the embodiment, the signal transmission distance can be minimized, and further, signal transmission loss can be minimized.

In addition, the base layer of the bridge substrate (300) has a flexible characteristic. For example, the base layer (310) of the bridge substrate (300) may include polyimide (PI). Accordingly, in the embodiment, the material of the base layer (310) of the bridge substrate (300) can be changed to polyimide, which is cheaper than a conventional silicon substrate, thereby reducing the cost of the bridge substrate (300).

In addition, in the embodiment, a circuit layer (330) and a pad layer (350) are formed on the bridge substrate (300). At this time, the pad layer (350) must be connected to the second sub-2-1 via (230b) of the second substrate layer (200) while being connected to the circuit layer (330). Accordingly, the alignment state of the pad layer (350) and the second sub-2-1 via (230b) has a great influence on the product reliability of the circuit substrate and the package substrate. At this time, in the embodiment, a transparent polyimide is used as a base layer (310) to form the circuit layer (330) and the pad layer (350), and thus, the alignment of the circuit layer (330) and the pad layer (350) can be easily achieved. In addition, in the embodiment, the accuracy of the formation position of the pad layer (350) is improved, and further, the alignment between the pad layer (350) and the second sub-2-1 via (230b) is improved, thereby improving product reliability.

In addition, in the embodiment, by forming the base layer (310) from polyimide, the bridge substrate (300) can be stably protected when the first substrate layer (100) and the second substrate layer (200) are thermally deformed.

That is, in the past, the base layer of the bridge substrate was formed of a silicon substrate. At this time, the silicon substrate has rigid characteristics. Accordingly, in the past, when the first or second substrate layer is thermally deformed, the silicon substrate does not flow together with the bridge substrate, and thus reliability issues such as breakage of the bridge substrate occur.

In contrast, in the embodiment, the base layer (310) of the bridge substrate (300) has a flexible characteristic including polyimide. Accordingly, in the embodiment, when the first substrate layer or the second substrate layer is thermally deformed, the bridge substrate (300) is allowed to flow, thereby resolving reliability issues such as breakage of the bridge substrate (300).

In addition, in the embodiment, the thickness of the bridge substrate (300) can be easily controlled by making the base layer (310) include polyimide. For example, in the past, a process of polishing the silicon substrate was required to control the thickness of the bridge substrate including a silicon substrate, and due to the difficulty of the process resulting from this, it was difficult to control the thickness of the bridge substrate to a desired thickness.

In contrast, in the embodiment, due to the characteristics of the polyimide constituting the base layer (310), its thickness can be easily adjusted, and accordingly, the overall thickness of the bridge substrate (300) can be easily controlled to correspond to the height of the cavity (111a). Accordingly, in the embodiment, it is possible to easily align the surface of the pad layer (350) of the bridge substrate (300) and the 1-1 circuit pattern (121). Accordingly, in the embodiment, it is possible to minimize the thickness or height deviation of the first sub-2-1 via (231a) and the second sub-2-1 via (230b) connected to the 1-1 circuit pattern (121), and thereby improve product reliability.

FIG. 9 is a drawing for explaining the height difference between the pad layer and the 1-1 circuit pattern according to the first embodiment, and FIG. 10 is a drawing for explaining the height difference between the pad layer and the 1-1 circuit pattern according to the second embodiment.

Referring to FIG. 9, the bridge substrate (300) in the embodiment is placed within the cavity (111a) of the 1-1 insulating layer (111).

At this time, it may be difficult to exactly match the thickness of the first-first insulating layer (111) corresponding to the depth of the cavity (111a) and the thickness of the bridge substrate (300).

Accordingly, in the embodiment, the base layer (310) constituting the bridge substrate (300) is formed of polyimide, thereby enabling easy control of the thickness of the bridge substrate (300).

Therefore, in the embodiment, the height difference (H1) between the upper surface of the pad layer (350) of the bridge substrate (300) and the upper surface of the 1-1 circuit pattern (121) can be minimized. For example, the upper surface of the pad layer (350) of the bridge substrate (300) can be positioned lower than the upper surface of the 1-1 circuit pattern (121). For example, the upper surface of the pad layer (350) of the bridge substrate (300) can be positioned lower than the upper surface of the 1-1 circuit pattern (121) by a first height (H1).

At this time, in the embodiment, compared to the prior art that uses a silicon substrate as the base layer, the first height (H1) can be easily controlled, and accordingly, the first height (H1) is set to 25 μm or less. For example, in the embodiment, the first height (H1) is set to 20 μm or less. For example, in the embodiment, the first height (H1) is set to 15 μm or less.

Preferably, in the embodiment, the first height (H1) is smaller than the difference (T1-T2) between the thickness (T1) of the first-first insulating layer (111) and the thickness (T2) of the second-first insulating layer (211).

At this time, a difference occurs between the height or thickness of the first sub-2-1 via (231a) constituting the second substrate layer and the height or thickness of the second sub-2-1 via (230b) by the amount of the difference in the first height (H1). At this time, the first sub-2-1 via (231a) and the second sub-2-1 via (230b) are each formed by filling the inside of the via hole with a metal material. At this time, if the first height (H1) as described above increases, the difference between the size of the via hole constituting the first sub-2-1 via (231a) and the size of the via hole constituting the second sub-2-1 via (230b) increases, and thus a problem may occur in the plating property of the plating layer filling the inside thereof. And, as the reliability of plating decreases due to the difference in the size of the via hole, the position of the second sub-2-1 via (230b) becomes misaligned, and thus poor contact between the second sub-2-1 via (230b) and the pad layer (350) of the bridge substrate (300) may occur. Accordingly, in the embodiment, the base layer (310) of the bridge substrate (300) is made of polyimide having flexible characteristics as described above, and thus the thickness control of the bridge substrate (300) is facilitated. Accordingly, in the embodiment, the first height (H1) can be minimized, and thus the height or thickness difference between the first sub-2-1 via (231a) and the second sub-2-1 via (230b) can be minimized. By this, in the embodiment, the contact reliability between the second sub-2-1 via (230b) and the pad layer (350) of the bridge substrate (300) can be improved, and further, product reliability can be improved.

Meanwhile, referring to FIG. 10, the bridge substrate (300) in the embodiment is placed within the cavity (111a) of the 1-1 insulating layer (111).

In the second embodiment, the upper surface of the pad layer (350) of the bridge substrate (300) may be positioned higher than the upper surface of the 1-1 circuit pattern (121). For example, the upper surface of the pad layer (350) of the bridge substrate (300) may be positioned higher than the upper surface of the 1-1 circuit pattern (121) by a second height (H2).

At this time, in the embodiment, the second height (H2) can be easily controlled compared to the prior art that uses a silicon substrate as the base layer, and thus the second height (H2) is set to 25 μm or less. For example, in the embodiment, the second height (H2) is set to 20 μm or less. For example, in the embodiment, the second height (H2) is set to 15 μm or less.

Preferably, in the embodiment, the second height (H2) is made smaller than the difference (T1-T2) between the thickness (T1) of the first-first insulating layer (111) and the thickness (T2) of the second-first insulating layer (211).

At this time, a difference occurs between the height or thickness of the first sub-2-1 via (231a) constituting the second substrate layer and the height or thickness of the second sub-2-1 via (230b) by the difference in the second height (H2). At this time, the first sub-2-1 via (231a) and the second sub-2-1 via (230b) are each formed by filling the inside of the via hole with a metal material. At this time, if the second height (H2) as described above increases, the difference between the size of the via hole constituting the first sub-2-1 via (231a) and the size of the via hole constituting the second sub-2-1 via (230b) increases, and thus a problem may occur in the plating property of the plating layer filling the inside thereof. And, as the reliability of plating decreases due to the difference in the size of the via hole, the position of the second sub-2-1 via (230b) becomes misaligned, and thus poor contact between the second sub-2-1 via (230b) and the pad layer (350) of the bridge substrate (300) may occur. Accordingly, in the embodiment, the base layer (310) of the bridge substrate (300) is made of polyimide having flexible characteristics as described above, and thus the thickness control of the bridge substrate (300) is facilitated. Accordingly, in the embodiment, the second height (H2) can be minimized, and thus the height or thickness difference between the first sub-2-1 via (231a) and the second sub-2-1 via (230b) can be minimized. By this, in the embodiment, the contact reliability between the second sub-2-1 via (230b) and the pad layer (350) of the bridge substrate (300) can be improved, and further, product reliability can be improved.

Hereinafter, a method for manufacturing a circuit board according to the first embodiment will be described.

Figures 11 to 28 are drawings for explaining the circuit board of Figure 2 in process order.

The method for manufacturing a circuit board of the embodiment can be divided into a first process of manufacturing a first substrate layer (100), a second process of attaching a bridge substrate (300) to the first substrate layer (100), and a third process of manufacturing a second substrate layer (200) on the first substrate layer (100) and the bridge substrate (300).

Referring to FIG. 11, the embodiment may perform a process of preparing basic materials for manufacturing a first substrate layer (100) using the ETS method. To this end, the embodiment may prepare a carrier board (CB). The carrier board (CB) may include a carrier insulating layer (CB1) and a carrier metal layer (CB2) disposed on at least one surface of the carrier insulating layer (CB1). At this time, although the drawing illustrates that the carrier metal layer (CB2) is disposed only on the first surface of the carrier insulating layer (CB1), the present invention is not limited thereto. For example, the carrier board (CB) in the embodiment may have the carrier metal layer (CB2) formed on the first surface of the carrier insulating layer (CB1) and the second surface opposite to the first surface. In addition, when the carrier metal layer is formed on both surfaces of the carrier insulating layer (CB1), the manufacturing process of the first substrate layer (100) described below may be performed on each of the two surfaces of the carrier board (CB). For example, in the embodiment, the following processes may be performed on the upper and lower sides of the carrier board (CB), respectively, to form multiple first substrate layers at once. For convenience of explanation, the description will be made below assuming that the carrier metal layer (CB2) is formed only on one side of the carrier insulating layer (CB1), and thus the manufacturing process of the first substrate layer is performed only on one side of the carrier board (CB).

The carrier metal layer (CB2) may be formed by electroless plating the carrier insulating layer (CB1). In addition, in an embodiment, a copper clad laminate (CCL) may be used as the carrier board (CB).

Next, in the embodiment, as in FIG. 12, a process of forming a first mask (510) on the carrier metal layer (CB2) may be performed. At this time, the first mask (510) may be formed to cover the entire second surface of the carrier metal layer (CB2), and may include an opening (not shown) that partially exposes the surface of the carrier metal layer (CB2) through a process of opening it later. That is, the first mask (510) may include an opening (not shown) that opens an area on the second surface of the carrier metal layer (CB2) where the 1-1 circuit pattern (121) is to be formed.

Next, in the embodiment, as illustrated in FIG. 13, a process of forming a 1-1 circuit pattern (121) filling the opening of the first mask (510) can be performed by performing electrolytic plating using the carrier metal layer (CB2) as a seed layer.

Next, in the embodiment, as illustrated in FIG. 14, a process of removing the first mask (510) disposed on the carrier metal layer (CB2) may be performed. In addition, in the embodiment, a process of forming a 1-1 insulating layer (111) covering the 1-1 circuit pattern (121) on the carrier metal layer (CB2) may be performed. The 1-1 insulating layer (111) may include a prepreg.

Next, in the embodiment, as illustrated in FIG. 15, a process of forming a 1-1 via hole (VH) in the 1-1 insulating layer (111) may be performed. The 1-1 via hole (VH) may be formed through a laser process to open the resin and reinforcing fiber constituting the 1-1 insulating layer (111).

Next, in the embodiment, as illustrated in FIG. 16, a process of forming a seed layer (122-1) on the surface of the first-first insulating layer (111) and the inner wall of the first-first via hole (VH) may be performed. The seed layer (122-1) may be formed by a chemical copper plating process, but is not limited thereto.

Next, in the embodiment, as illustrated in FIG. 17, a process of forming a second mask (520) on the seed layer (122-1) formed on the surface of the 1-1 insulating layer (111) may be performed. At this time, the second mask (520) may include at least one opening (not illustrated). For example, the second mask (520) may include an opening exposing an area where the 1-1 via (131) is to be formed and an opening exposing an area where the 1-2 circuit pattern (122) is to be formed.

Next, in the embodiment, as illustrated in FIG. 18, electroplating may be performed using the seed layer (122-1) to form an electroplating layer (122-2) that fills the opening of the second mask (520). At this time, the seed layer (121-1) and the electroplating layer (121-2) may form a first-first via (131) that fills the first-first via hole (VH) and a first-second circuit pattern (122).

Next, in the embodiment, as illustrated in FIG. 19, a process of removing the second mask (520) and a process of etching the seed layer (122-1) may be performed. For example, in the embodiment, a seed layer etching process may be performed to remove a portion of the seed layer (122-1) that does not vertically overlap with the electroplating layer (122-2).

Next, in the embodiment, the process of forming a multilayer first substrate layer (100) can be performed by repeatedly performing the process of FIGS. 12 to 19.

For example, in the embodiment, as illustrated in FIG. 20, a process of forming a 1-2 insulating layer (112) on the 1-1 insulating layer (111) may be performed. In addition, in the embodiment, a process of forming a 1-2 via (132) and a 1-3 circuit pattern (123) on the 1-2 insulating layer (112) may be performed.

In addition, in the embodiment, as illustrated in FIG. 21, a process of forming a 1-3 insulating layer (113) on the 1-2 insulating layer (112) may be performed. In the embodiment, a process of forming a 1-3 via (133) and a 1-4 circuit pattern (124) on the 1-3 insulating layer (113) may be performed.

Next, as illustrated in FIG. 22, when the manufacturing of the first substrate layer (100) is completed, a process of removing the carrier board (CB) can be performed. In addition, when the carrier board (CB) is removed, a process of removing the carrier metal layer (CB2), which is a seed layer of the first-first circuit pattern (121) formed on the first-first insulating layer (111), by etching can be performed. As described above, in the embodiment, the first substrate layer (100) can be manufactured by performing the processes of FIGS. 11 to 22.

Next, as illustrated in FIG. 23, in the embodiment, a process of forming a cavity (111a) by processing the 1-1 insulating layer (111) of the first substrate layer (100) with a laser can be performed. At this time, the 1-2 circuit pattern (122) includes a pad portion (122a) that overlaps in the thickness direction with the area where the cavity (111a) is to be formed. At this time, the laser process for forming the cavity (111a) can be performed using the pad portion (122a) as a laser stopper.

Next, in the embodiment, as illustrated in FIG. 24, a process of inserting and attaching a bridge substrate (300) into the cavity (111a) may be performed. For example, in the embodiment, a process of manufacturing a bridge substrate (300) that forms a redistribution layer using a base layer (310) having a polyimide having flexible properties may be performed. Thereafter, in the embodiment, once the bridge substrate (300) is manufactured, a process of forming an adhesive layer (360) on the lower surface of the base layer (310) of the bridge substrate (300) may be performed. The adhesive layer (360) may be a DAF (Die Attach Film), but is not limited thereto. Thereafter, in the embodiment, a process of attaching the bridge substrate (300) including the adhesive layer (360) onto the pad portion (122a) exposed through the cavity (111a) may be performed.

Next, in the embodiment, as illustrated in FIG. 25, a process of laminating a 2-1 insulating layer (211) on the 1-1 insulating layer (111) may be performed. At this time, the 2-1 insulating layer (211) may include a different insulating material from the 1-1 insulating layer (111). For example, the 2-1 insulating layer (211) may include ABF or PID. The 2-1 insulating layer (211) may be arranged to cover the ETS pattern of the first substrate layer (100). Specifically, the 2-1 insulating layer (211) may be arranged to cover the first surface of the 1-1 insulating layer (111) and the first surface of the 1-1 circuit pattern (121). In addition, the 2-1 insulating layer (211) is formed to fill the interior of the cavity (111a), and accordingly, the bridge substrate (300) inserted into the cavity (111a) can be molded. At this time, in the embodiment, by molding the interior of the cavity (111a) using the 2-1 insulating layer (211) including the ABF or the PID, the bridge substrate (300) can be stably protected.

Meanwhile, in the embodiment, a process of forming a carrier film (not shown) on the opposite surface of the surface on which the 2-1 insulating layer (211) is to be disposed in the first substrate layer (100) may be performed. For example, in the embodiment, the carrier film (not shown) may be formed on the second surface of the 1-3 insulating layer (113) of the first substrate layer (100). The carrier film may protect the 1-3 insulating layer (113) and the 1-3 circuit pattern (123) during the manufacturing process of the second substrate layer (200) to be performed below.

Next, as illustrated in FIG. 26, in the embodiment, a process of forming a via hole (not shown) by processing the 2-1 insulating layer (211) may be performed. At this time, the via hole may include a via hole exposing the 1-1 circuit pattern (121) and a via hole exposing the pad layer (350) of the bridge substrate (300). In addition, the widths of these may be different. Since this has already been described above, a detailed description thereof will be omitted.

Next, in the embodiment, a plating process for filling the via hole may be performed, thereby forming a 2-1 via (231) and a 2-1 circuit pattern (221).

Next, in the embodiment, as illustrated in FIG. 27, a process of manufacturing a second substrate layer (200) having a multi-layer structure may be performed by repeatedly performing the processes of FIGS. 25 and 26. For example, in the embodiment, a process of forming a 2-2 insulating layer (212) on the 2-1 insulating layer (211) may be performed. Thereafter, in the embodiment, a process of forming a 2-2 via (232) penetrating the 2-2 insulating layer (212) and a 2-2 circuit pattern (222) formed on the first surface or the upper surface of the 2-2 insulating layer (212) may be performed.

Next, in the embodiment, as shown in FIG. 28, a process of forming a first protective layer (140) on the outermost side of the first substrate layer (100) and forming a second protective layer (240) on the outermost side of the second substrate layer (200) may be performed.

Fig. 29 is a drawing showing a package substrate according to the first embodiment.

Referring to FIG. 29, in the embodiment, a structure may be provided in which a plurality of chips are mounted on the circuit board (400) of FIG. 2.

For example, the package substrate (600) may include a first adhesive portion (610) arranged on a pad of a second-second circuit pattern (222) arranged on the outermost side of the second substrate layer (200). In addition, the package substrate (600) may include a second adhesive portion (640) arranged on a pad of the second-second circuit pattern (222).

Specifically, it is a pattern disposed on the first outermost side of the circuit board of the 2-2 circuit pattern (222). In addition, the 2-2 circuit pattern (222) may include a pad exposed through the second protective layer (240). For example, the pad of the 2-2 circuit pattern (222) may include a first pad disposed in a first mounting area (MR1) and a second pad disposed in a second mounting area (MR2).

And, the first adhesive portion (610) can be placed on the first pad, and the second adhesive portion (640) can be placed on the second pad.

The first adhesive portion (610) and the second adhesive portion (640) may have the same shape or may have different shapes.

For example, the first adhesive portion (610) and the second adhesive portion (640) may have a hexahedral shape. For example, the cross-sections of the first adhesive portion (610) and the second adhesive portion (640) may include a quadrangular shape. The cross-sections of the first adhesive portion (610) and the second adhesive portion (640) may include a rectangular or square shape. For example, the first adhesive portion (610) and the second adhesive portion (640) may include a spherical shape. For example, the cross-sections of the first adhesive portion (610) and the second adhesive portion (640) may include a circular or semicircular shape. For example, the cross-sections of the first adhesive portion (610) and the second adhesive portion (640) may include a partially or entirely rounded shape. The cross-sectional shape of the first adhesive portion (610) and the second adhesive portion (640) may be flat on one side and curved on the other side. The first adhesive portion (610) and the second adhesive portion (640) may be solder balls, but are not limited thereto.

In an embodiment, a first chip (620) may be disposed on the first adhesive portion (610). The first chip (620) may be a first processor chip. For example, the first chip (620) may be an application processor (AP) chip among a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (630) of the first chip (620) may be electrically connected to a first pad of the 2-2 circuit pattern (222) through the first adhesive portion (610).

In addition, the embodiment may include a second chip (650) disposed on the second adhesive portion (640). The second chip (650) may be a second processor chip. For example, the second chip (650) may be an application processor (AP) chip of a different type from the first chip (620) among a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The terminal (660) of the second chip (650) may be electrically connected to the second pad of the second-2 circuit pattern (222) through the second adhesive portion (640).

For example, the first chip (620) may be a central processor chip, and the second chip (650) may be a graphics processor chip, but is not limited thereto.

Meanwhile, the first chip (620) and the second chip (650) may be arranged on the circuit board (400) with a first separation width (D1). The first separation width (D1) may be 150 μm or less. For example, the first separation width (D1) may be 120 μm or less. For example, the first separation width (D1) may be 100 μm or less.

Preferably, the first gap width (D1) may have a range between 60 μm and 150 μm. Preferably, the first gap width (D1) may have a range between 70 μm and 120 μm. Preferably, the first gap width (D1) may have a range between 80 μm and 110 μm. If the first gap width (D1) is less than 60 μm, a problem may occur in the operational reliability of the first chip (620) or the second chip (640) due to interference between the first chip (620) and the second chip (640). If the first gap width (D1) is less than 60 μm, the bridge substrate (300) may not be placed in an area corresponding to the cavity (111a) that overlaps in the thickness direction with a space corresponding to the first gap width (D1). If the first separation width (D1) is greater than 150 μm, signal transmission loss may increase as the distance between the first chip (620) and the second chip (650) increases. If the first separation width (D1) is greater than 150 μm, the volume of the bridge substrate (300) may increase, and further, the volume of the package substrate (600) may increase.

The above package substrate (600) may include a molding layer (670). The molding layer (670) may be arranged to cover the first chip (620) and the second chip (650). For example, the molding layer (670) may be an EMC (Epoxy Mold Compound) formed to protect the mounted first chip (620) and the second chip (650), but is not limited thereto.

At this time, the molding layer (670) may have a low permittivity to improve heat dissipation characteristics. For example, the permittivity (Dk) of the molding layer (670) may be 0.2 to 10. For example, the permittivity (Dk) of the molding layer (670) may be 0.5 to 8. For example, the permittivity (Dk) of the molding layer (670) may be 0.8 to 5. Accordingly, in the embodiment, the molding layer (670) is made to have a low permittivity, thereby improving heat dissipation characteristics for heat generated from the first chip (620) and/or the second chip (650).

Meanwhile, the package substrate (600) may include a third adhesive portion (680) positioned at the lowermost side of the circuit substrate (400). The third adhesive portion (680) may be positioned on the second side or lower surface of the first-fourth circuit pattern (124) exposed through the first protective layer (140).

Fig. 30 is a drawing showing a circuit board according to the second embodiment.

Referring to FIG. 30, a circuit board (400a) according to the second embodiment may further include a third mounting area (MR3) in the chip mounting area (R1) compared to the circuit board (400) according to the first embodiment.

For example, the circuit board (400) according to the first embodiment provides two mounting areas in which multiple processor chips of different types are mounted. For example, the circuit board (400) of the first embodiment may be a board for replacing the first package (10) of the comparative example.

In contrast, the circuit board (400a) according to the second embodiment may provide at least three mounting areas in which at least one memory chip is placed, together with a plurality of processor chips of different types. For example, the circuit board (400A) of the second embodiment may be a substrate for replacing the first package (10) and the second package (20) of the comparative example.

The circuit board (400a) may include a first substrate layer (100a), a second substrate layer (200a), and a bridge substrate (300).

The basic characteristics of the first substrate layer (100a), the second substrate layer (200a), and the bridge substrate (300) are substantially the same as those of the first substrate layer (100), the second substrate layer (200), and the bridge substrate (300) of FIG. 2, and a detailed description thereof will be omitted.

The chip mounting area (R1) of the second substrate layer (200a) may include a first mounting area (MR1) in which a first processor chip is mounted, a second mounting area (MR2) in which a second processor chip of a different type from the first processor chip is mounted, a third mounting area (MR3) in which a first memory chip is mounted, a first separation area (SR1) that separates the first mounting area (MR1) and the second mounting area (MR2), and a second separation area (SR2) that separates the first mounting area (MR1) and the third mounting area (MR3).

That is, the embodiment provides a circuit board (400a) capable of mounting a plurality of processor chips and at least one memory chip.

The second-second circuit pattern (222) included in the second substrate layer (200a) of the embodiment includes a third pad (not shown) arranged in the third mounting area (MR3). The third pad of the second-second circuit pattern (222) included in the third mounting area (MR3) may have a width corresponding to the first pad or the second pad.

Meanwhile, a trace of the second-second circuit pattern (222) may be arranged in the second separation region (SR2). The trace of the second-second circuit pattern (222) may be a connecting wire for electrically connecting the first pad of the second-second circuit pattern (222) and the second pad of the second-second circuit pattern (222).

Fig. 31 is a drawing showing a package substrate according to the second embodiment.

Referring to FIG. 31, the package substrate (600a) further includes a memory chip mounting portion compared to the package substrate (600) according to the first embodiment.

Specifically, the package substrate (600a) includes a memory chip (690) that is arranged side by side with the first chip (620) while being spaced apart from the first chip (620) by a certain distance. At this time, the memory chip (690) may have a multi-layer structure with an adhesive layer (692) therebetween. In addition, the package substrate (600a) may include a connecting member (694) connected to the memory chip (690). The connecting member (694) may be a wire, but is not limited thereto.

The thickness of the package substrate (600a) in the embodiment may be smaller than the thickness (t8 + t9) of the package substrate of the comparative example. The thickness of the package substrate (600a) may be about 95% of the thickness (t8 + t9) of the package substrate of the comparative example. The thickness of the package substrate (600a) may be about 90% of the thickness (t8 + t9) of the package substrate of the comparative example. The thickness of the package substrate (600a) may be about 85% of the thickness (t8 + t9) of the package substrate of the comparative example.

Here, the thickness of the package substrate (600a) may correspond to the distance from the uppermost side of the molding layer (670) to the lowermost side of the third adhesive portion (680).

For example, the thickness of the package substrate (600a) may be less than 1000 μm. For example, the thickness of the package substrate (600a) may be less than 900 μm. For example, the thickness of the package substrate (600a) may be less than 850 μm.

A circuit board according to an embodiment includes a first substrate layer and a second substrate layer. The first substrate layer includes a prepreg, thereby maintaining rigidity of the circuit board to improve warpage characteristics and enhance product reliability. Furthermore, the first substrate layer is connected to a main board of an electronic device, and thus includes a first circuit pattern and first vias having specifications corresponding to connection pads of the electronic device. Furthermore, the second substrate layer includes an ABF or a PID, thereby improving connection reliability with a plurality of processor chips. Furthermore, the second substrate layer can provide a second circuit pattern or a second via, which have improved connection reliability with the first circuit pattern or the first via of the first substrate layer.

Furthermore, the second circuit pattern and the second via disposed on the second substrate layer may have a width that gradually increases as they approach the first substrate layer. Accordingly, in the embodiment, signal transmission loss between the first substrate layer and the second substrate layer can be minimized, and further, communication performance can be improved.

In addition, in the embodiment, a bridge substrate is inserted into the first substrate layer, so that the pad layer of the bridge substrate and the second via of the second substrate layer are directly connected to each other. Accordingly, in the embodiment, the signal transmission distance can be minimized, and further, signal transmission loss can be minimized.

In addition, the base layer of the bridge substrate has flexible properties. For example, the base layer of the bridge substrate may include polyimide (PI). Accordingly, in the embodiment, the material of the base layer of the bridge substrate can be changed to polyimide, which is cheaper than a conventional silicon substrate, thereby reducing the cost of the bridge substrate.

In addition, in the embodiment, a circuit layer and a pad layer are formed on the bridge substrate. At this time, the pad layer must be connected to the circuit layer and the second sub-2-1 via of the second via of the second substrate layer. Accordingly, the alignment state of the pad layer and the second sub-2-1 via has a great influence on the product reliability of the circuit substrate and the package substrate. At this time, in the embodiment, the circuit layer and the pad layer are formed using transparent polyimide as a base layer, and thus, the alignment of the circuit layer and the pad layer can be easily effected. In addition, in the embodiment, the accuracy of the formation position of the pad layer is improved, and further, the alignment between the pad layer and the second sub-2-1 via is improved, thereby improving product reliability.

In addition, in the embodiment, by forming the base layer with polyimide, the bridge substrate can be stably protected when the first substrate layer and the second substrate layer are thermally deformed. That is, in the past, the base layer of the bridge substrate was formed with a silicon substrate. At this time, the silicon substrate has a rigid characteristic. Accordingly, in the past, when the first substrate layer or the second substrate layer is thermally deformed, the silicon substrate does not flow together with the bridge substrate, and thus reliability problems such as breakage of the bridge substrate occur.

In contrast, in the embodiment, the base layer of the bridge substrate has a flexible characteristic including polyimide. Accordingly, in the embodiment, when the first substrate layer or the second substrate layer is thermally deformed, the bridge substrate is allowed to flow, thereby resolving reliability issues such as breakage of the bridge substrate.

In addition, in the embodiment, by including the base layer as polyimide, the thickness of the bridge substrate can be easily controlled. For example, in the past, a process of polishing the silicon substrate was required to control the thickness of the bridge substrate including a silicon substrate, and due to the difficulty of the process resulting from this, it was difficult to control the thickness of the bridge substrate to a desired thickness.

In contrast, in the embodiment, due to the characteristics of the polyimide constituting the base layer, its thickness can be easily adjusted, and accordingly, the overall thickness of the bridge substrate can be easily controlled in response to the height of the cavity. Accordingly, in the embodiment, the surface alignment of the pad layer of the bridge substrate and the 1-1 circuit pattern can be facilitated. Accordingly, in the embodiment, the thickness or height deviation of the first sub-2-1 via connected to the 1-1 circuit pattern and the second sub-2-1 via connected to the bridge substrate can be minimized, and thus, product reliability can be improved.

The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims (18)

A first substrate layer including a cavity;
A bridge substrate disposed within the cavity of the first substrate layer; and
Including a second substrate layer disposed on the first substrate layer and the bridge substrate,
The first substrate layer includes a plurality of first insulating layers stacked along a vertical direction, a plurality of first circuit patterns respectively disposed within the plurality of first insulating layers, and a plurality of first vias disposed between the plurality of first circuit patterns.
The second substrate layer includes a plurality of second insulating layers disposed on the first substrate layer and stacked along the vertical direction, a plurality of second circuit patterns respectively disposed within the plurality of second insulating layers, and a plurality of second vias disposed between the plurality of second circuit patterns.
The cavity is provided in the upper insulating layer closest to the second substrate layer among the plurality of first insulating layers,
The plurality of first vias include an upper via that overlaps the cavity in a horizontal direction,
The side surface of the upper via and the inner wall of the cavity have slopes that are inclined in opposite directions,
Circuit board. In the first paragraph,
The above first insulating layer comprises glass fiber,
The second insulating layer does not include glass fibers,
Circuit board. In the first paragraph,
The upper via has a slope with a width that decreases in the horizontal direction toward the second substrate layer.
Circuit board. In the third paragraph,
The plurality of first vias of the first substrate layer have the same slope,
Circuit board. In the first paragraph,
The inner wall of the cavity has a slope such that the width of the cavity in the horizontal direction increases toward the second substrate layer.
Circuit board. In paragraph 5,
Each of the plurality of second vias has a slope that decreases in width in the horizontal direction toward the first substrate layer,
Circuit board. In the first paragraph,
The plurality of second insulating layers include a lower insulating layer arranged closest to the first substrate layer,
The lower insulating layer is disposed within the cavity and surrounds the side of the bridge substrate.
Circuit board. In the first paragraph,
The horizontal width of each of the plurality of second circuit patterns is smaller than the horizontal width of each of the plurality of first circuit patterns.
Circuit board. In the first paragraph,
The horizontal width of each of the plurality of second vias is smaller than the horizontal width of each of the plurality of first vias.
Circuit board. In paragraph 9,
Each of the plurality of second vias has a different width in the horizontal direction,
Among the plurality of second vias, the second via arranged closest to the first substrate layer has the largest width in the horizontal direction,
Among the plurality of second vias, the second via that is positioned furthest from the first substrate layer has the smallest width in the horizontal direction.
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