KR102827660B1 - Printed circuit board - Google Patents

Abstract

The present disclosure relates to a printed circuit board, comprising: a first insulating layer having a through hole; a second insulating layer disposed on the first insulating layer and covering at least a portion of each of one surface of the first insulating layer and a wall surface of the through hole, the second insulating layer having a via hole formed on the through hole; and a via filling at least a portion of the via hole.

Description

Printed Circuit Board {PRINTED CIRCUIT BOARD}

The present disclosure relates to a printed circuit board.

Electronic devices are not only required to have superior performance and functions along with the development of technology, but are also required to be miniaturized in terms of size. In line with this trend, the need for printed circuit boards included in electronic devices to implement circuit patterns in greater detail is increasing.

One of the several objects of the present disclosure is to provide a printed circuit board in which fine via processing is easy.

Another object of the present disclosure is to provide a printed circuit board having high stiffness.

Another object of the present disclosure is to provide a printed circuit board with improved warpage.

One of several solutions proposed by the present disclosure is to provide a printed circuit board including: a first insulating layer having a through hole; a second insulating layer disposed on the first insulating layer and covering at least a portion of each of one surface of the first insulating layer and a wall surface of the through hole, the second insulating layer having a via hole formed on the through hole; and a via filling at least a portion of the via hole.

Another of several solutions proposed through the present disclosure is to provide a printed circuit board, comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer; and a via penetrating the second insulating layer; wherein at least a portion of the via is disposed at a level between one surface of the first insulating layer and a second surface opposite to the first surface, and wherein at least a portion of a side surface of the via disposed at the level between the one surface and the second surface of the first insulating layer is surrounded by the second insulating layer.

As one of the effects of the present disclosure, a printed circuit board in which fine via processing is easy can be provided.

Another effect of the present disclosure is that a printed circuit board having high stiffness can be provided.

Another effect of the present disclosure is that a printed circuit board with improved warpage can be provided.

Figure 1 schematically illustrates an example of a block diagram of an electronic device system according to an example.
Figure 2 is a schematic perspective view of an electronic device according to an example.
Figure 3 schematically illustrates a cross-sectional view of a printed circuit board according to an example.
Figure 4 schematically illustrates an I-I' cut plan view of a printed circuit board according to an example.
Figure 5 schematically illustrates a cross-sectional view of a printed circuit board according to another example.
Figures 6a to 6d schematically illustrate a manufacturing process diagram of a printed circuit board according to an example.

Hereinafter, the present disclosure will be described with reference to the attached drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

Electronic devices

Figure 1 schematically illustrates an example of a block diagram of an electronic device system according to an example.

Referring to the drawing, the electronic device (1000) accommodates a main board (1010). Chip-related components (1020), network-related components (1030), and other components (1040) are physically and/or electrically connected to the main board (1010). These are also combined with other electronic components described below to form various signal lines (1090).

Chip-related components (1020) include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processor (e.g., CPU), graphic processor (e.g., GPU), digital signal processor, encryption processor, microprocessor, and microcontroller; logic chips such as analog-to-digital converters and ASICs (application-specific ICs); and the like. In addition, it goes without saying that other types of chip-related electronic components may be included. In addition, it goes without saying that these electronic components (1020) may be combined with each other. The chip-related components (1020) may also be in the form of a package including the above-described chips or electronic components.

Network-related components (1030) include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as IEEE 802.11 family), WiMAX (such as IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and the like, and may include any of a number of other wireless or wired standards or protocols. In addition, it goes without saying that the network-related components (1030) may be combined with the chip-related electronic components (1020).

Other components (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electro magnetic interference) filters, MLCC (multi-layer ceramic condensers), etc. However, the present invention is not limited thereto, and in addition, passive components in the form of chip components used for various other purposes may be included. In addition, it goes without saying that other components (1040) may be combined with chip-related electronic components (1020) and/or network-related electronic components (1030).

Depending on the type of the electronic device (1000), the electronic device (1000) may include other electronic components that may or may not be physically and/or electrically connected to the main board (1010). Examples of the other electronic components include a camera module (1050), an antenna module (1060), a display (1070), a battery (1080), etc. However, the electronic components are not limited thereto, and may include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition, it goes without saying that other electronic components used for various purposes may be included depending on the type of the electronic device (1000).

The electronic device (1000) may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited thereto, and it is obvious that the electronic device may be any other electronic device that processes data.

Figure 2 is a schematic perspective view of an electronic device according to an example.

Referring to the drawing, the electronic device may be, for example, a smartphone (1100). A main board (1110) is accommodated inside the smartphone (1100), and various electronic components (1120) are physically and/or electrically connected to the main board (1110). In addition, other electronic components, such as a camera module (1130) and/or a speaker (1140), which may or may not be physically and/or electrically connected to the main board (1110), are accommodated inside. Some of the electronic components (1120) may be the chip-related components described above, and may be, for example, a semiconductor package (1121), but are not limited thereto. The semiconductor package (1121) may be, but is not limited to, a surface-mounted form such as a semiconductor chip or a passive component on a package substrate in the form of a multilayer electronic component embedded substrate. Meanwhile, the electronic device is not necessarily limited to a smartphone (1100), and may of course be another electronic device as described above.

printed circuit board

Figure 3 schematically illustrates a cross-sectional view of a printed circuit board according to an example.

Figure 4 schematically illustrates an I-I' cut plan view of a printed circuit board according to an example.

Referring to the drawings, a printed circuit board according to an example includes a first insulating layer (121) having a through hole (H), a second insulating layer (131) disposed on the first insulating layer (121) and covering at least a portion of one surface of the first insulating layer (121) and a wall surface of the through hole (H), and having a via hole (V) formed on the through hole (H), and a via (133) filling at least a portion of the via hole (V). At this time, at least a portion of a space between the first insulating layer (121) and the via (133) may be filled with the second insulating layer (131).

In addition, the printed circuit board according to the example may further include a first wiring layer (112) arranged on the other side, which is the opposite side of one side of the first insulating layer (121). At least a portion of the first wiring layer (112) may be exposed through a through hole (H) and a via hole (V) and connected to a via (133). Although the first wiring layer (112) is illustrated as being embedded in the other side of the first insulating layer (121) in the drawing, it may also be arranged to protrude on the other side of the first insulating layer (121).

In addition, the printed circuit board according to the example may further include a second wiring layer (132) arranged on the second insulating layer (131). The second wiring layer (132) may be connected to a via (133) and may also be connected to the first wiring layer (112) through the via (133).

The first insulating layer (121) and the second insulating layer (131) may include different materials. Therefore, the first insulating layer (121) and the second insulating layer (131) may complement each other's deficient characteristics. However, if necessary, the first insulating layer (121) and the second insulating layer (131) may include the same material.

The stiffness of the first insulating layer (121) may be greater than the stiffness of the second insulating layer (131). From a similar perspective, the elastic modulus of the first insulating layer (121) may be greater than the elastic modulus of the second insulating layer (131). For example, prepreg, FR-4 (Frame Retardant 4), BT (Bismaleimide triazine), etc. may be used as the forming material of the first insulating layer (121), but is not limited thereto. In addition, from a similar perspective, the forming material of the first insulating layer (121) may use a resin further containing an inorganic filler and/or a reinforcing material such as glass cloth (Glass Fabric).

The second insulating layer (131) may include a material that is easy to form a microcircuit pattern. From this perspective, ABF (Ajinomoto Build-up Film), RCC (Resin coated copper), PID (Photo Imageable dielectric), etc. may be used as the forming material of the second insulating layer (131), but is not limited thereto. In addition, from a similar perspective, the forming material of the second insulating layer (131) may not include a reinforcing material such as an inorganic filler and/or glass fiber (Glass Cloth, Glass Fabric).

Meanwhile, when forming the insulating layer using a material that is easy to form a fine circuit pattern, such as ABF (Ajinomoto Build-up Film), it may have the characteristic of easy fine via processing, but there may be problems such as insufficient stiffness of the printed circuit board not being secured or warpage occurring. On the other hand, when forming the insulating layer using a material having high stiffness and elastic modulus, such as prepreg, it may be possible to secure the stiffness of the printed circuit board and improve warpage, but there may be a problem that fine via processing is difficult.

Meanwhile, as described above, the printed circuit board according to the example includes a first insulating layer (121) having a through hole (H), a second insulating layer (131) disposed on the first insulating layer (121) and covering at least a portion of one surface of the first insulating layer (121) and a wall surface of the through hole (H), and having a via hole (V), and a via (133) filling at least a portion of the via hole (V).

At this time, the first insulating layer (121) and the second insulating layer (131) may include different materials, and thus the first insulating layer (121) and the second insulating layer (131) may complement each other's deficient characteristics. For example, the first insulating layer (121) may include a material having high rigidity and elastic modulus, and the second insulating layer (131) may include a material that is easy to form a fine circuit pattern. Therefore, sufficient stiffness of the printed circuit board can be secured. In addition, warpage of the printed circuit board can be improved. In addition, a printed circuit board in which fine via processing is easy can be provided.

Meanwhile, the minimum width of the via hole (V) may be narrower than the minimum width of the through hole (H). As described above, the second insulating layer (131) may be formed of a material that is easier to form a fine circuit pattern than the first insulating layer (121), and thus, a via hole (V) having a narrower width than the through hole (H) formed in the first insulating layer (121) may be formed in the second insulating layer (131).

Therefore, as illustrated, the via hole (V) may be arranged inside the through hole (H) in the plane. For example, when each of the via hole (V) and the through hole (H) has a circular shape, the diameter of the via hole (V) may be smaller than the diameter of the through hole (H), and the via hole (V) may be arranged within the circumference of the through hole (H) in the plane. However, it should be understood that the shape of each of the via hole (V) and the through hole (H) is not limited to being circular. The centers of each of the via hole (V) and the through hole (H) may coincide with each other or may be misaligned with each other.

Below, each component of a printed circuit board according to an example is described in more detail.

A conductive material may be used as a material for forming the first wiring layer (112), and non-limiting examples thereof include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The first wiring layer (112) may be formed by a known plating process.

The forming material of the first insulating layer (121) is not particularly limited, and any insulating material can be used without limitation. For example, as the forming material of the first insulating layer (121), a thermosetting resin such as an epoxy resin or a phenol resin, a thermoplastic resin such as a polyimide, or a resin further including an inorganic filler and/or a reinforcing material such as glass cloth or glass fabric in the resin can be used.

As described above, the stiffness of the first insulating layer (121) may be greater than the stiffness of the second insulating layer (131). From a similar viewpoint, the elastic modulus of the first insulating layer (121) may be greater than the elastic modulus of the second insulating layer (131). For example, prepreg, FR-4 (Frame Retardant 4), BT (Bismaleimide triazine), etc. may be used as a forming material of the first insulating layer (121), but is not limited thereto.

The through hole (H) penetrates the first insulating layer (121). The width of the through hole (H) may narrow from the second insulating layer (131) toward the first insulating layer (121), but is not limited thereto, and the width of the through hole (H) may be constant.

The through hole (H) can be formed by a known method, for example, by laser processing. A first wiring layer (112) can be arranged on the bottom surface of the through hole (H), and the first wiring layer (112) can serve as a processing stop layer when forming the through hole (H). In addition, the through hole (H) can expose at least a part of the first wiring layer (112). The bottom surface of the through hole (H) can be at the same level as the bottom surface of the via hole (V).

The minimum width of the through hole (H) may be wider than the minimum width of the via hole (V). The area where the through hole (H) has the minimum width may be the bottom surface of the through hole (H) exposing the first wiring layer (112). At the same level, the width of the through hole (H) may be wider than the width of the via hole (V). The maximum width of the through hole (H) may be wider or narrower than the maximum width of the via hole (V), and the maximum width of the through hole (H) and the maximum width of the via hole (V) may be the same.

The second insulating layer (131) is disposed on the first insulating layer (121) and covers at least a portion of each of one surface of the first insulating layer (121) and the wall surface of the through hole (H). In addition, the second insulating layer (131) covers at least a portion of the first wiring layer (112) and can surround at least a portion of the side surface of the via (V).

The forming material of the second insulating layer (131) is also not particularly limited, and any insulating material can be used without limitation. For example, the forming material of the second insulating layer (131) may be a thermosetting resin such as an epoxy resin or a phenol resin, a thermoplastic resin such as a polyimide, or a resin further including an inorganic filler and/or a reinforcing material such as glass cloth or glass fabric.

As described above, the second insulating layer (131) may include a material that is easy to form a microcircuit pattern. From this perspective, materials for forming the second insulating layer (131) may include, but are not limited to, ABF (Ajinomoto Build-up Film), RCC (Resin coated copper), PID (Photo Image-able Dielectric), etc. In addition, the second insulating layer (131) may not include a reinforcing material such as an inorganic filler and/or glass fiber (Glass Cloth, Glass Fabric).

The via hole (V) penetrates the second insulating layer (131). The width of the via hole (V) may narrow from the second insulating layer (131) toward the first insulating layer (121), but is not limited thereto, and the width of the via hole (V) may be constant.

The via hole (V) can be formed by a known method, for example, by laser processing. A first wiring layer (112) can be arranged on the bottom surface of the via hole (V), and the first wiring layer (112) can serve as a processing stop layer when forming the via hole (V). In addition, the via hole (V) can expose at least a part of the first wiring layer (112). The bottom surface of the via hole (V) can be at the same level as the bottom surface of the through hole (H).

The minimum width of the via hole (V) may be narrower than the minimum width of the through hole (H). The area where the via hole (V) has the minimum width may be the bottom surface of the via hole (V) exposing the first wiring layer (112). At the same level, the width of the via hole (V) may be wider than the width of the through hole (H). The maximum width of the via hole (V) may be wider or narrower than the maximum width of the through hole (H), and the maximum width of the via hole (V) and the maximum width of the through hole (H) may be the same.

The via (133) fills the via hole (V) and thus penetrates the second insulating layer (131) like the via hole (V). In addition, the via (133) can physically and electrically connect the first wiring layer (112) and the second wiring layer (132) to each other. The via (133) can extend onto the second insulating layer (131) to form a via land.

At least a portion of the via (133) is arranged at a level between one surface of the first insulating layer (121) and the other surface, which is the opposite surface of the one surface. With reference to the drawing, the lower surface of the via (133) may be arranged at a level between the upper surface and the lower surface of the first insulating layer (121). Therefore, with reference to the drawing, the lower surface of the via (133) is arranged lower than the upper surface of the first insulating layer (121).

In addition, at least a portion of the side surface of the via (133) is surrounded by the second insulating layer (131) at a level between one side and the other side of the first insulating layer (121). At least a portion of the side surface of the via (133) may also be surrounded by the second insulating layer (131) at a level between one side and the other side of the second insulating layer (131). In addition, the entire side surface of the via (133) may be surrounded by the second insulating layer (131).

A conductive material may be used as a forming material of the via (133), and examples thereof include, but are not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The via (133) may be a via hole (V) completely filled with a metal material, or the metal material may be formed along the wall surface of the via hole (V).

The via (133) may have a known shape such as a tapered shape, an hourglass shape, a cylindrical shape, etc. When the via (133) has a tapered shape, the width of the via (133) may narrow from the second insulating layer (131) toward the first insulating layer (121), but is not limited thereto.

A conductive material may be used as a material for forming the second wiring layer (132), and non-limiting examples thereof include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second wiring layer (132) may be formed by a known plating process. Depending on the process, the second wiring layer (132) may be integrated with the via (133).

Figure 5 schematically illustrates a cross-sectional view of a printed circuit board according to another example.

Referring to the drawings, a printed circuit board according to another example further includes a core layer (110) in the printed circuit board according to the example.

The first insulating layer (121) is disposed on the core layer (110), and thus the second insulating layer (131) is also disposed on the core layer (110). As shown in the drawing, the first insulating layer (121) may be disposed on both sides of the core layer (110), and, unlike as shown in the drawing, the first insulating layer (121) may be disposed on only one side of the core layer (110).

The first insulating layer (121) and the second insulating layer (131) may be build-up insulating layers arranged on the outside of the printed circuit board. Accordingly, a micro via can be selectively formed in an area where micro circuit formation is required due to rewiring, etc.

The core layer (110) includes a third insulating layer (111) and a first wiring layer (112) disposed on the third insulating layer (111). The first wiring layer (112) may be disposed on both sides of the third insulating layer (111), and the core layer (110) may further include a through-via (113) that penetrates the third insulating layer (111) and connects the first wiring layers (112) disposed on both sides of the third insulating layer (111) to each other.

Additionally, a printed circuit board according to another example may further include a passivation layer (140) disposed on the second insulating layer (131).

An insulating material may be used as a material for forming the third insulating layer (111). For example, the material for forming the third insulating layer (111) may be, but is not limited to, a thermosetting resin such as an epoxy resin or a phenol resin, a thermoplastic resin such as a polyimide, or a material including a reinforcing material such as glass fiber (glass cloth, glass fabric) and/or inorganic filler together with these, for example, prepreg, FR-4 (Frame Retardant 4), BT (Bismaleimide triazine), ABF (Ajinomoto Build-up Film), RCC (Resin coated copper), PID (Photo Image-able Dielectric), etc.

The number and thickness of the third insulating layer (111) are not particularly limited. For example, the third insulating layer (111) may be composed of a plurality of layers. The thickness of the third insulating layer (111) may be thicker than each of the first insulating layer (121) and the second insulating layer (131), but is not limited thereto. For example, the thickness of the third insulating layer (111) may be substantially the same as each of the first insulating layer (121) and the second insulating layer (131), and may be thinner than each of the first insulating layer (121) and the second insulating layer (131).

The first wiring layer (112) may be arranged on one side or both sides of the third insulating layer (111). In the drawing, the first wiring layer (112) is illustrated as being arranged to protrude on both sides of the third insulating layer (111), but may also be embedded in one side and/or both sides of the third insulating layer (111). For example, the first wiring layer (112) may be formed to protrude on one side of the third insulating layer (111) and embedded in the other side.

The first wiring layer (112) can perform various functions according to the design of the corresponding layer. For example, the first wiring layer (112) can include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern includes various signals other than the ground pattern, the power pattern, etc., for example, an antenna signal, a data signal, etc. These patterns can include a (line) pattern, a plane pattern, and/or a pad pattern, respectively.

A conductive material may be used as a forming material for the through-via (113), and examples thereof include, but are not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The through-via (113) may be a via hole that is completely filled with a metal material, or the metal material may be formed along the wall surface of the via hole. When the through-via (113) is a via hole that is formed with a metal material along the wall surface of the via hole, the interior of the via hole may be filled with an insulating material. In addition, the through-via (113) is not limited to the shape illustrated in the drawing, and may have a known shape such as a tapered shape, an hourglass shape, a cylindrical shape, or the like.

The second wiring layer (132) may also perform various functions depending on the design of the corresponding layer. For example, the second wiring layer (132) may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern includes various signals other than the ground pattern, the power pattern, etc., such as an antenna signal, a data signal, etc. These patterns may include a (line) pattern, a plane pattern, and/or a pad pattern, respectively.

The passivation layer (140) may serve as a protective layer. The passivation layer (140) may be disposed on the second insulating layer (131) and may have an opening that exposes at least a portion of the second wiring layer (132). The passivation layer (140) may be an ABF (Ajinomoto Build-up Film) layer, or may be a solder resist (SR) layer. However, the present invention is not limited thereto, and a known insulating material may be used as a forming material of the passivation layer (140).

Figures 6a to 6d schematically illustrate a manufacturing process diagram of a printed circuit board according to an example.

Referring to the drawing, first, a third insulating layer (111) is prepared. The third insulating layer (111) may be a copper clad laminate (CCL) in which copper foil (114) is attached to one or both sides of the third insulating layer (111), but is not limited thereto.

Next, a through-via (113) penetrating the third insulating layer (111) is formed by a known plating process, etc., and a first wiring layer (112) is formed on one side or both sides of the third insulating layer (111) to form a core layer (110). In addition, a first insulating layer (111) is formed on one side or both sides of the core layer (110) to cover the first wiring layer (112).

Next, a through hole (H) penetrating the first insulating layer (111) is formed. The through hole (H) can be formed by a known method, for example, by laser processing. A first wiring layer (112) can be arranged on the bottom surface of the through hole (H), and the first wiring layer (112) can serve as a processing stop layer when forming the through hole (H).

Next, a second insulating layer (121) is formed on the first insulating layer (111). At this time, the second insulating layer (121) may be formed to fill at least a portion of the through hole (H). For example, the second insulating layer (121) may be formed to fill the through hole (H) and extend onto the first insulating layer (111).

Next, a via hole (V) penetrating the second insulating layer (131) is formed. The via hole (V) can be formed by a known method, and for example, can be formed by laser processing. A first wiring layer (112) can be arranged on the bottom surface of the via hole (V), and the first wiring layer (112) can serve as a processing stop layer when forming the via hole (V).

Next, a via (133) is formed to fill the via hole (V) by a known plating process, etc., and a second wiring layer (132) is formed on the second insulating layer (131).

Next, a passivation layer (140) having an opening exposing at least a portion of the second wiring layer (132) is formed on the second insulating layer (131).

Meanwhile, as described above, the first insulating layer (121) and the second insulating layer (131) may include different materials, and thus the first insulating layer (121) and the second insulating layer (131) may complement each other's deficiencies. For example, the first insulating layer (121) may include a material having high rigidity and elastic modulus, and the second insulating layer (131) may include a material that is easy to form a fine circuit pattern. Accordingly, sufficient stiffness of the printed circuit board can be secured. In addition, warpage of the printed circuit board can be improved. In addition, a printed circuit board in which fine via processing is easy can be provided.

In addition, the minimum width of the via hole (V) may be narrower than the minimum width of the through hole (H). As described above, the second insulating layer (131) may be formed of a material that is easier to form a fine circuit pattern than the first insulating layer (121), and thus, a via hole (V) having a narrower width than the through hole (H) formed in the first insulating layer (121) may be formed in the second insulating layer (131).

In this specification, terms such as upper surface, upper side, lower side, and lower side are explained based on the drawings.

In this specification, the term "connected" includes not only direct connection but also indirect connection. In addition, the term "electrically connected" includes both cases where the connection is physically connected and cases where the connection is not physically connected.

In this specification, the expressions first, second, etc. are used to distinguish one component from another, and do not limit the order and/or importance of the components. In some cases, without exceeding the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The terms used in this disclosure are used for the purpose of describing examples only and are not intended to limit this disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise.

The term "example" used in this disclosure does not mean identical embodiments, but is provided to emphasize and explain each of the different unique features. However, the examples presented above do not exclude implementations in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to the other example, unless there is a description that is contrary or contradictory to the matter in the other example.

Claims (10)

A first insulating layer having a through hole;
A second insulating layer disposed on the first insulating layer and in contact with at least a portion of the wall surface of the first insulating layer and the through hole, the second insulating layer having a via hole formed on the through hole;
A via filling at least a portion of the above via hole; and
A wiring layer is disposed on the opposite side of the first insulating layer to the side on which the second insulating layer is disposed and is connected to the via;
The above wiring layer is in contact with the second insulating layer,
Printed circuit board.
In the first paragraph,
At least a portion of the space between the first insulating layer and the via is filled with the second insulating layer.
Printed circuit board.
In the first paragraph,
The first insulating layer and the second insulating layer contain different materials.
Printed circuit board.
In the third paragraph,
The elastic modulus of the first insulating layer is greater than the elastic modulus of the second insulating layer.
Printed circuit board.
In the first paragraph,
The minimum width of the above via hole is narrower than the minimum width of the above through hole.
Printed circuit board.
In the first paragraph,
The width of each of the above through hole and the above via hole narrows from the second insulating layer toward the first insulating layer.
Printed circuit board.
In the first paragraph,
In the plane, the via hole is arranged on the inside of the through hole.
Printed circuit board.
In the first paragraph,
The above wiring layer is exposed through the through hole and the via hole and connected to the via.
Printed circuit board.
In Article 8,
A core layer including a third insulating layer and the wiring layer disposed on the third insulating layer;
The first insulating layer is disposed on the core layer.
Printed circuit board.
First insulation layer;
A second insulating layer disposed on the first insulating layer and in contact with the first insulating layer; and
A via penetrating the second insulating layer but spaced apart from the first insulating layer;
At least a portion of said via is arranged at a level between one side of said first insulating layer and the other side which is the opposite side of said one side,
At least a portion of the side surface of the via is surrounded by the second insulating layer at a level between the first surface and the other surface of the first insulating layer.
Printed circuit board.