KR102815729B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes a first substrate, a peripheral circuit area including circuit elements provided on the first substrate, a second substrate disposed on an upper portion of the first substrate, a first laminated structure including first gate electrodes and first interlayer insulating layers alternately and repeatedly laminated on the second substrate, and a memory laminated structure including a second laminated structure disposed on the first laminated structure and including second gate electrodes and second interlayer insulating layers alternately and repeatedly laminated, and a dummy laminated structure including first horizontal insulating layers spaced apart from the first substrate and the peripheral circuit area in a first direction perpendicular to the first substrate, spaced apart from the memory laminated structure in a second direction perpendicular to the first direction, and laminated spaced apart from each other, and second horizontal insulating layers alternately laminated with the first horizontal insulating layers, wherein a first distance from the first substrate to a lowermost second horizontal insulating layer of the second horizontal insulating layers is greater than a second distance from the first substrate to a lowermost first gate electrode of the second gate electrodes.

Description

SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device.

Semiconductor devices are becoming smaller in size while requiring high-capacity data processing. Accordingly, it is necessary to increase the integration of semiconductor elements that make up these semiconductor devices. Accordingly, as one of the methods for improving the integration of semiconductor devices, semiconductor devices with vertical transistor structures instead of conventional planar transistor structures are being proposed.

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U.S. Patent Publication No. 9449987 B1 (2016.09.20.) United States Patent Application Publication No. 2014-0014889 A1 (January 16, 2014)

One of the technical tasks that the technical idea of the present invention seeks to achieve is to provide a semiconductor device with improved integration and reliability.

According to exemplary embodiments, a semiconductor device includes a first substrate, a peripheral circuit area including circuit elements provided on the first substrate, a second substrate disposed on an upper portion of the first substrate, a first stacked structure including first gate electrodes and first interlayer insulating layers alternately and repeatedly stacked on the second substrate, and a memory stacked structure including a second stacked structure disposed on the first stacked structure and including second gate electrodes and second interlayer insulating layers alternately and repeatedly stacked on the first stacked structure, and a dummy stacked structure including first horizontal insulating layers spaced apart from the first substrate and the peripheral circuit area in a first direction perpendicular to the first substrate, spaced apart from the memory stacked structure in a second direction perpendicular to the first direction, and stacked spaced apart from each other, and second horizontal insulating layers alternately stacked with the first horizontal insulating layers, wherein a first distance from the first substrate to a lowermost second horizontal insulating layer of the second horizontal insulating layers is greater than a second distance from the first substrate to a lowermost first gate electrode of the second gate electrodes.

According to exemplary embodiments, a semiconductor device includes a first substrate, a peripheral circuit region including circuit elements provided on the first substrate, a second substrate disposed on the first substrate, a first stacked structure including first gate electrodes and first interlayer insulating layers alternately and repeatedly stacked on the second substrate, and a memory stacked structure disposed on the first stacked structure, including second gate electrodes and second interlayer insulating layers alternately and repeatedly stacked on the first stacked structure, a dummy stacked structure including first horizontal insulating layers spaced apart from the first substrate and the peripheral circuit region in a first direction perpendicular to the first substrate, and spaced apart from the memory stacked structure in a second direction perpendicular to the first direction and stacked spaced apart from each other, and second horizontal insulating layers alternately stacked with the first horizontal insulating layers, and a buffer insulating layer disposed between the peripheral circuit region and the dummy stacked structure in the first direction and disposed on the first stacked structure.

In a semiconductor device, a dummy stacked structure is included in addition to a stacked structure forming a memory cell, and a semiconductor device with improved reliability can be provided by forming a step between the dummy stacked structure and the stacked structure.

The various advantageous and beneficial advantages and effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

FIGS. 1A and 1B are schematic cross-sectional views of semiconductor devices according to exemplary embodiments.
FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments.
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments.
FIGS. 4A to 4F are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

FIGS. 1A and 1B are schematic cross-sectional views of semiconductor devices according to exemplary embodiments.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments.

Referring to FIGS. 1A to 2, the semiconductor device (100) may include a peripheral circuit region (PC) including a first substrate (301), and a memory cell region (MC) including a second substrate (101). The memory cell region (MC) may be disposed on an upper side of the peripheral circuit region (PC). In exemplary embodiments, on the contrary, the cell region (MC) may be disposed on a lower side of the peripheral circuit region (PC).

The peripheral circuit area (PC) may include a first substrate (301), circuit elements (320) arranged on the first substrate (301), circuit contact plugs (370), circuit wiring lines (380), and a peripheral area insulating layer (390).

The first substrate (301) may have an upper surface extending in the x direction and the y direction. The first substrate (301) may have separate device isolation layers formed thereon to define an active region. Source/drain regions (305) including impurities may be arranged in a portion of the active region. The first substrate (301) may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate (301) may be provided as a bulk wafer or an epitaxial layer.

The circuit elements (320) may include planar transistors. Each of the circuit elements (320) may include a circuit gate dielectric layer (322), a spacer layer (324), and a circuit gate electrode (325). Source/drain regions (305) may be disposed within the first substrate (301) on both sides of the circuit gate electrode (325). The circuit gate dielectric layer (322) may include silicon oxide, and the circuit gate electrode (325) may include a conductive material such as a metal, polycrystalline silicon, or a metal silicide. The spacer layer (324) may be disposed on both sidewalls of the circuit gate dielectric layer (322) and the circuit gate electrode (325) and may be made of, for example, silicon nitride.

A peripheral region insulating layer (390) may be disposed on a circuit element (320) on a first substrate (301). The peripheral region insulating layer (390) may be made of an insulating material. Circuit contact plugs (370) may penetrate the peripheral region insulating layer (390) and be connected to the source/drain regions (305). The circuit contact plugs (370) may include first contact plugs (372), second contact plugs (374), and third contact plugs (376) that are sequentially stacked from the first substrate (301). An electrical signal may be applied to the circuit element (320) by the circuit contact plugs (370). In an area not shown, the circuit contact plugs (370) may also be connected to the circuit gate electrode (325). Circuit wiring lines (380) may be connected to circuit contact plugs (370) and may be arranged in multiple layers. The circuit wiring lines (380) may include a first circuit wiring line (382), a second circuit wiring line (384), and a third circuit wiring line (386). The circuit contact plugs (370) and the circuit wiring lines (380) may include a metal, for example, tungsten (W), copper (Cu), aluminum (Al), or the like.

The memory cell region (MC) includes a second substrate (101), a first stacked structure (GS1) and a second stacked structure (GS2) sequentially stacked on the second substrate (101), a memory stacked structure (CS) having a first region (A) and a second region (B), dummy layers (106) arranged on a peripheral circuit region (PC) in a third region (C) which is an outer region of the second substrate (101), an intermediate insulating layer (150) arranged between the dummy layers (106) on the peripheral circuit region (PC), a first capping insulating layer (190) stacked on the second region (B) of the first stacked structure (GS1), the dummy layers (106) and the intermediate insulating layer (150), The third region (C) may include a buffer insulating layer (215) disposed on a first capping insulating layer (190), a dummy stacked structure (DS) spaced apart from a peripheral circuit region (PC) in the z direction and spaced apart from a memory stacked structure (CS) in the x direction, and disposed on the buffer insulating layer (215), and a dummy pattern (DP) disposed on a side surface of the buffer insulating layer (215). In addition, the memory cell region (MC) may include a second region (B) of the second stacked structure (GS2), a second capping insulating layer (290) covering an upper surface of the dummy stacked structure (DS) and the first capping insulating layer (190), and may further include a first insulating layer (295) covering the first region (A) of the second stacked structure (GS2) and an upper surface of the second capping insulating layer (290), and second and third insulating layers (296, 297) on the first insulating layer. The memory cell region (MC) may further include channel contact plugs (270) electrically connected to the channel structures (CH), gate contact plugs (262) electrically connected to the first and second gate electrodes (130, 230), a substrate contact plug (264) electrically connected to the second substrate (101), and a through via (267) connecting the memory cell region (MC) and the peripheral circuit region (PC) in the third region.

A memory stacked structure (CS) may include a second substrate (101) having a first region (A) corresponding to a central region and a second region (B) corresponding to a step region, a first stacked structure (GS1) including first gate electrodes (130) that are vertically stacked and spaced apart from each other on the second substrate (101), first interlayer insulating layers (120) and a middle interlayer insulating layer (160) that are alternately stacked with the first gate electrodes (130), a second stacked structure (GS2) including second gate electrodes (230) that are vertically stacked and spaced apart from each other on the first stacked structure, second interlayer insulating layers (220) that are alternately stacked with the second gate electrodes (230) and an upper insulating layer (250), channel structures (CH) that are arranged to penetrate the first stacked structure (GS1) and the second stacked structure (GS2), and a separation region (SR) that penetrates the first stacked structure (GS1) and the second stacked structure (GS2) and extends in the x direction. Additionally, the semiconductor device (100) may further include first and second conductive layers (104, 105) disposed between the substrate (101) and the first interlayer insulating layer (120).

The first region (A) of the second substrate (101) may be a region where the first stacked structure (GS1) and the second stacked structure (GS2) are stacked and channel structures (CH) are arranged, and may be a region where memory cells are arranged, and the second region (B) may be a region where the first and second gate electrodes (130, 230) extend to different lengths and may correspond to a region for electrically connecting the memory cells to a peripheral circuit region (PERI). The second region (B) may be arranged at least at one end of the first region (A) in at least one direction, for example, the x direction.

The second substrate (101) may have an upper surface extending in the x direction and the y direction. The second substrate (101) may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate (101) may further include impurities. The second substrate (101) may be provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

The first and second gate electrodes (130, 230) may be vertically spaced apart and stacked on a second substrate (101) to form first and second stacked structures (GS1, GS2). The first and second gate electrodes (130, 230) may include electrodes that sequentially form a ground selection transistor, memory cells, and a string selection transistor from the second substrate (101). The number of the first and second gate electrodes (130, 230) forming the memory cells may be determined according to the capacity of the semiconductor device (100).

The first and second gate electrodes (130, 230) are stacked vertically spaced apart from each other on the first region (A) and can extend from the first region (A) to the second region (B) at different lengths to form a step-shaped step structure. The first and second gate electrodes (130, 230) can form a step structure between the gate electrodes (130) along the x direction, as illustrated in FIG. 1A. In some embodiments, at least some of the first and second gate electrodes (130, 230) can form a gate group with a certain number, for example, two to six gate electrodes (130), to form a step structure between the gate groups along the x direction. In this case, the first and second gate electrodes (130, 230) forming the gate group can be arranged to have a step structure with each other in the y direction as well. By the above step structure, the first and second gate electrodes (130, 230) may form a step shape in which the lower first and second gate electrodes (130, 230) extend longer than the upper first and second gate electrodes (130, 230) and may provide ends that are exposed upward from the first and second interlayer insulating layers (120, 220). In some embodiments, at the ends, the first and second gate electrodes (130, 230) may have an increased thickness.

The first and second gate electrodes (130, 230) may include a metal material, for example, tungsten (W). According to an embodiment, the first and second gate electrodes (130, 230) may include polycrystalline silicon or a metal silicide material. In exemplary embodiments, the first and second gate electrodes (130, 230) may further include a diffusion barrier layer, for example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

The first and second interlayer insulating layers (120, 220) may be disposed between the first and second gate electrodes (130, 230), respectively. The first and second interlayer insulating layers (120, 220), like the first and second gate electrodes (130, 230), may be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate (101) and extend in the x direction. The first and second interlayer insulating layers (120, 220) may include an insulating material such as silicon oxide or silicon nitride.

The channel structures (CH) each form one memory cell string and may be arranged spaced apart from each other in rows and columns on the first region (A). The channel structures (CH) may be arranged to form a grid pattern in the x-y plane or may be arranged in a zigzag shape in one direction. The channel structures (CH) have a pillar shape and may have slanted side surfaces that become narrower as they get closer to the second substrate (101) depending on an aspect ratio. In exemplary embodiments, dummy channels that do not substantially form a memory cell string may be further arranged at an end of the first region (A) adjacent to the second region (B) and in the second region (B).

As illustrated in FIG. 1B, a channel layer (140) may be arranged within the channel structures (CH). The channel layer (140) within the channel structures (CH) may be formed in an annular shape surrounding the channel insulating layer (150) therein, but may also have a pillar shape, such as a cylinder or a prism, without the channel insulating layer (150) according to an embodiment. The channel layer (140) may be connected to the first conductive layer (104) at the bottom. The channel layer (140) may include a semiconductor material, such as polycrystalline silicon or single-crystal silicon. Channel pads (255) may be arranged on the upper portion of the channel layer (140) in the channel structures (CH). The channel pads (255) may be arranged to cover the upper surface of the channel insulating layer (150) and be electrically connected to the channel layer (140). The channel pads (255) may include, for example, doped polycrystalline silicon.

Although not specifically illustrated, it may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer (140) between the first and second gate electrodes (130, 230) and the channel layer (140). The tunneling layer can tunnel charges into the charge storage layer and may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

The separation region (SR) may be arranged to extend in the x direction. The separation region (SR) may be a through separation region that penetrates the entire first and second gate electrodes (130, 230) stacked on the substrate (101) and is connected to the substrate (101). The separation region (SR) may separate the first and second gate electrodes (130, 230). The separation region (SR) may be arranged by partially recessing the upper portion of the substrate (101) or may be arranged on the substrate (101) so as to be in contact with the upper surface of the substrate (101). The separation region (SR) may include a separation insulating layer (185), and the separation insulating layer (185) may include an insulating material, for example, silicon oxide. In exemplary embodiments, the separation region (SR) may include a conductive material and an insulating material that electrically insulates the conductive material from the first and second stacked structures (GS1, GS2).

The first and second conductive layers (104, 105) may be stacked and arranged on an upper surface of the second substrate (101). At least a portion of the first and second conductive layers (104, 105) may function as a part of a common source line of the semiconductor device (100), for example, may function as a common source line together with the second substrate (101). The first conductive layer (104) may be directly connected to the channel layer (140) around the channel layer (140). The first and second conductive layers (104, 105) may include a semiconductor material, for example, polycrystalline silicon. In this case, at least the first conductive layer (104) may be a doped layer, and the second conductive layer (105) may be a doped layer or a layer including an impurity diffused from the first conductive layer (104). In exemplary embodiments, the first and second conductive layers (104, 105) may be omitted. In this case, the channel structures (CH) may include an epitaxial layer disposed under the channel layer (140).

The first capping insulating layer (190) may be arranged to cover a step-shaped stepped structure formed by extending to different lengths in the second region (B) of the first laminated structure (GS1), dummy layers (106) arranged on the peripheral circuit region (PC) in the third region (C) which is the outer region of the second substrate (101), and an intermediate insulating layer (150) arranged between the dummy layers (106) on the peripheral circuit region (PC). The first capping insulating layer (190) may be formed of silicon oxide, for example, Tetra Ethyl Ortho Silicate (TEOS).

The buffer insulating layer (215) may be disposed on the first capping insulating layer (190) in a third region (C) spaced apart from the memory stack structure (CS). In one embodiment, the buffer insulating layer (215) may have a thickness substantially the same as the height of one second gate electrode (230) and the second interlayer insulating layer (220), as in FIG. 1A. In one embodiment, the thickness (VT) of the buffer insulating layer (215) may be substantially the same as or greater than the height of two or more gate electrodes (230) and interlayer insulating layers (220), as in FIG. 2. The thickness (VT) of the buffer insulating layer (215) may be, for example, in a range of about 80 nm to about 120 nm. In one embodiment, the buffer insulating layer (215) may include substantially the same material as the first capping insulating layer (190), but is not limited thereto.

The dummy stacked structure (DS) may be disposed on the buffer insulating layer (215). The lowermost surface of the dummy stacked structure (DS) may be covered by the buffer insulating layer (215). The dummy stacked structure (DS) may include first horizontal insulating layers (225) and second horizontal insulating layers (235) that are alternately laminated with each other. In an exemplary embodiment, the dummy stacked structure (DS) may further include an upper insulating layer (250) including an insulating material, for example, silicon oxide, on the uppermost portion. The first and second horizontal insulating layers (225, 235) may extend along the x direction with different lengths to form a step-shaped step structure. By the step structure, the second horizontal insulating layers (235) may form a step-shaped structure in which the lower second horizontal insulating layer (235) extends longer than the upper second horizontal insulating layer (235) and may provide ends that are exposed upward from the first horizontal insulating layers (225). A first distance (d1) from the first substrate (301) to the lowermost second horizontal insulating layer (235) among the second horizontal insulating layers (235) may be greater than a second distance (d2) from the first substrate (301) to the lowermost second gate electrode (230) among the second gate electrodes (230). The first distance (d1) may be a distance from the upper surface of the first substrate (301) to the lower surface of the lowermost second horizontal insulating layer (235). The second distance (d2) may be a distance from the upper surface of the first substrate (301) to the lower surface of the lowermost second gate electrode (230). A difference between the first distance (d1) and the second distance (d2) may be substantially equal to a thickness (VT) of the buffer insulating layer (215). A distance from the first substrate (301) to a top surface of the uppermost second horizontal insulating layer (235) among the second horizontal insulating layers (235) may be greater than a distance from the first substrate (301) to a top surface of the uppermost second gate electrode (230) among the second gate electrodes (230). The first horizontal insulating layers (225) may include an insulating material, for example, silicon oxide or silicon nitride. In an exemplary embodiment, the first horizontal insulating layers (225) may include the same material as the second interlayer insulating layers (220). The second horizontal insulating layers (235) may be made of a different material from the first horizontal insulating layers (225). For example, the second horizontal insulating layers (235) may be made of a different material from the first horizontal insulating layers (225) selected from silicon, silicon oxide, silicon carbide, and silicon nitride.

The dummy pattern (DP) may be arranged on at least one sidewall of the buffer insulating layer (215). In one embodiment, the dummy pattern (DP) may be arranged on each of both sidewalls of the buffer insulating layer (215). The dummy pattern (DP) may include one or more first patterns (225a) and second patterns (235a). In one embodiment, when each of the first patterns (225a) and the second patterns (235a) includes two or more, the first patterns (225a) and the second patterns (235a) may be alternately stacked. The first pattern (225a) or the second pattern (235a) may have an 'L' shape along the sidewall of the buffer insulating layer (215) and the upper surface of the first capping insulating layer (190). The upper surface of the dummy pattern (DP) may be curved, but is not limited thereto, and may be formed in a straight line.

The first pattern (225a) may include the same material as the first horizontal insulating layer (225), and may include an insulating material including, for example, silicon oxide or silicon nitride. The second pattern (235a) may include the same material as the second horizontal insulating layer (235), and may be made of a different material from the first pattern (225a). For example, the second pattern (235a) may be made of a different material from the first pattern (225a) selected from silicon, silicon oxide, silicon carbide, and silicon nitride.

The second capping insulating layer (290) may be arranged to cover the step-shaped step structure and the dummy stacked structure (DS) formed by extending to different lengths in the second region (B) of the second stacked structure (GS2). The distance from the upper surface of the second substrate (101) to the upper surface of the second capping insulating layer (290) may be greater in the third region (C) than in the first region (A) and the second region (B). The second capping insulating layer (290) may be formed of silicon oxide, for example, TEOS.

The first insulating layer (295), the second insulating layer (296), and the third insulating layer (297) may be sequentially laminated on the upper insulating layer (250) and the second capping insulating layer (290). The height of the lower surface of the first insulating layer (295) may be higher in the third region (C) than in the first region (A) and the second region (B). The first insulating layer (295) and the second insulating layer (296) may have a curved upper surface and/or lower surface accordingly in the third region (C). The first to third insulating layers (295, 296, 297) may be made of an insulating material.

Channel contact plugs (270) may penetrate the first to third insulating layers (295, 296, 297) in the first region (A) and be electrically connected to the channel structures (CH). Bit lines (280) electrically connected to the channel contact plugs (270) may be arranged on the channel contact plugs (270).

The gate contact plugs (262) can be electrically connected to the first and second gate electrodes (130, 230) in the second region (B). The gate contact plugs (262) can be arranged to penetrate the first and second insulating layers (295, 296) and be connected to the first and second gate electrodes (130, 230) exposed upward, respectively.

The substrate contact plug (264) may be connected to the second substrate (101) at an end of the second region (B). The substrate contact plug (264) may be connected to the second substrate (101) by penetrating the first and second insulating layers (295, 296) and the first and second conductive layers (104, 105) exposed upward. The substrate contact plug (264) may apply an electrical signal to a common source line including, for example, the second substrate (101).

The cylindrical upper contact plugs (275) and the line-shaped upper wiring lines (285) may be electrically connected to the first and second gate electrodes (130, 230). The upper contact plugs (275) may be arranged on the gate contact plugs (262). The channel contact plugs (270), the bit line (280), the gate contact plugs (262), the substrate contact plug (264), the upper contact plugs (275), and the upper wiring lines (285) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), or the like, and each may further include a diffusion barrier layer.

The through via (267) is arranged in the third region (C) of the memory cell region (MC), which is an outer region of the second substrate (101), and may extend to the peripheral circuit region (PC). The through via (267) may penetrate a portion of the peripheral region insulating layer (390) and the first and second insulating layers (295, 296) to be electrically connected to the upper contact plug (275) and the upper wiring line (285). In an exemplary embodiment, the through via (267) may extend to the peripheral circuit region (PC) by penetrating the dummy stacked structure (DS). The through via (267) may include a conductive material, for example, a metal material such as tungsten (W), copper (Cu), or aluminum (Al).

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments.

In the semiconductor device (100a), the upper surface of the second capping insulating layer (290) of the third region (C) may be coplanar with the upper surfaces of the second capping insulating layers (290) of the first and second regions (A, B). That is, the distances from the first substrate (301) to the first insulating layer (295) and the second insulating layer (296) in the first to third regions (A, B, C) may be the same. The thickness of the upper insulating layer (250) disposed on the uppermost part of the dummy stacked structure (DS) in the z direction may be smaller than in the embodiment of FIG. 1. In an exemplary embodiment, the first insulating layer (295) may be disposed on the uppermost second horizontal insulating layer (235), excluding the upper insulating layer (250).

FIGS. 4A to 4F are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

Referring to FIG. 4a, a peripheral circuit area (PC) including circuit elements (320) and wiring structures is formed on a first substrate (301), and a second substrate (101) in which a memory cell area (MC) is provided on the upper portion of the peripheral circuit area (PC) in the first and second areas is formed, and then first and second source sacrificial layers (111, 112) and a second conductive layer (105) are formed, and first sacrificial insulating layers (110) and first interlayer insulating layers (120) are alternately laminated. Next, a first capping insulating layer (190) covering a laminated structure of first sacrificial insulating layers (110) and first interlayer insulating layers (120), an intermediate insulating layer (150), and dummy layers (106) can be formed, and first and second penetrating sacrificial layers (115, 116) penetrating the laminated structure and the first capping insulating layer (190) can be formed, respectively.

First, a circuit gate dielectric layer (322) and a circuit gate electrode (325) can be sequentially formed on a first substrate (301). The circuit gate dielectric layer (322) and the circuit gate electrode (325) can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer (322) is formed of silicon oxide, and the circuit gate electrode (325) can be formed of at least one of polycrystalline silicon or a metal silicide layer, but is not limited thereto. Next, a spacer layer (324) and source/drain regions (305) can be formed on both sidewalls of the circuit gate dielectric layer (322) and the circuit gate electrode (325). According to embodiments, the spacer layer (324) may be formed of a plurality of layers. Next, an ion implantation process can be performed to form the source/drain regions (305).

Circuit contact plugs (370) can be formed by forming a portion of a peripheral area insulating layer (390), then etching and removing a portion of it, and filling it with a conductive material. Circuit wiring lines (380) can be formed, for example, by depositing a conductive material and then patterning it.

The peripheral area insulating layer (390) may be formed of a plurality of insulating layers. The peripheral area insulating layer (390) may be formed in part at each step of forming the wiring structures including the circuit contact plugs (370) and the circuit wiring lines (380), and may be formed on top of the third circuit wiring line (386) at the top, thereby ultimately covering the circuit elements (320) and the wiring structures.

Next, a second substrate (101) may be formed on the peripheral region insulating layer (390). The second substrate (101) may be made of, for example, polycrystalline silicon and may be formed by a CVD process. The polycrystalline silicon forming the second substrate (101) may include impurities.

The first and second source sacrificial layers (111, 112) may be laminated on the second substrate (101) such that the first source sacrificial layers (111) are disposed above and below the second source sacrificial layer (112). The first and second source sacrificial layers (111, 112) may include different materials. The first and second source sacrificial layers (111, 112) may be layers that are replaced with the first conductive layer (104) of FIG. 1A through a subsequent process. For example, the first source sacrificial layer (111) may be made of the same material as the first and second interlayer insulating layers (120, 220), and the second source sacrificial layer (112) may be made of the same material as the first sacrificial insulating layers (110). The second conductive layer (105) may be formed on the first and second source sacrificial layers (111, 112).

The first sacrificial insulating layers (110) may be layers that are partially replaced with first gate electrodes (130) (see FIG. 1a) through a subsequent process. The first sacrificial insulating layers (110) may be made of a different material from the first interlayer insulating layers (120) and may be formed of a material that can be etched with etch selectivity under specific etching conditions with respect to the first interlayer insulating layers (120). For example, the first interlayer insulating layer (120) may be made of at least one of silicon oxide and silicon nitride, and the first sacrificial insulating layers (110) may be made of a different material from the first interlayer insulating layer (120) selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In embodiments, the thicknesses of the first interlayer insulating layers (120) may not all be the same. The thickness and the number of films constituting the first interlayer insulating layers (120) and the first sacrificial insulating layers (110) may be varied from those shown. An intermediate interlayer insulating layer (160) may be further formed on the uppermost first sacrificial insulating layer (110).

In the second region (B), the photolithography process and the etching process can be repeatedly performed on the first sacrificial insulating layers (110) using a mask layer so that the upper first sacrificial insulating layers (110) extend shorter than the lower first sacrificial insulating layers (110). As a result, the first sacrificial insulating layers (110) can form a step-shaped step structure in predetermined units.

A first capping insulating layer (190) covering the lower laminated structure of the first sacrificial insulating layers (110) and the first interlayer insulating layers (120), the intermediate insulating layer (150), and the dummy layers (106) can be formed.

Next, the first through-hole sacrificial layers (115) can be formed by performing an etching process so as to penetrate the lower laminated structure at positions corresponding to the channel structures (CH) of FIG. 1A. First, through-holes corresponding to the lower channel structures (CH) of the first laminated structure (GS1) of FIG. 1A can be formed. Due to the height of the lower laminated structure, the sidewalls of the through-holes may not be perpendicular to the upper surface of the substrate (101). The through-holes can be formed to extend to the second substrate (101). In exemplary embodiments, the through-holes may be formed to recess a portion of the second substrate (101). The first through-hole sacrificial layers (115) can be formed to fill the through-holes.

In a fourth region (D) outside the first to third regions (A, B, C), second through-pass sacrificial layers (116) may be formed to penetrate the first capping insulating layer (190), similarly to the first through-pass sacrificial layers (115). The fourth region (D) outside the first to third regions (A, B, C), which are defined as chip regions, may be a scribe lane region. The scribe lane region corresponds to a region for performing dicing to separate a semiconductor wafer into individual semiconductor chips after forming a semiconductor element on a semiconductor chip. The scribe lane region may be a region including alignment keys or overlay keys used in exposure processes performed to form the semiconductor element.

Referring to FIG. 4b, a buffer layer (215a) may be formed on the lower laminated structure and the first capping insulating layer (190). In an exemplary embodiment, the buffer layer (215a) may include an insulating material, for example, silicon oxide, etc. In an exemplary embodiment, the buffer layer (215a) may include the same material as the first capping insulating layer (190).

Referring to FIG. 4c, a buffer insulating layer (215) may be formed by patterning the buffer layer (215a) to be disposed on the first capping insulating layer (190) in the third region (C). Specifically, a mask layer is formed to expose the first region (A), the second region (B) including the stacked structure of the buffer layer (215a), and the fourth region (D) including the second through-pass sacrificial layer (116), and then the buffer layer (215a) may be removed from the exposed region by an etching process.

Referring to FIG. 4d, second sacrificial insulating layers (210) and second interlayer insulating layers (220) may be alternately laminated in the first and second regions (A, B), and first horizontal insulating layers (225) and second horizontal insulating layers (235) may be alternately laminated on the buffer insulating layer (215) in the third region (C) and the fourth region (D). An upper laminated structure including the second sacrificial insulating layers (210) and the second interlayer insulating layers (220) forming a step structure in a staircase shape in predetermined units and a dummy laminated structure (DS) forming a step structure in a staircase shape in the third region (C) may be formed, and a dummy pattern (DP) may be formed on at least one sidewall of the buffer insulating layer (215). Next, a second capping insulating layer (290) may be formed that covers the upper laminated structure and the dummy laminated structure (DS) and extends to the fourth region (D).

The second sacrificial insulating layers (210) may be layers that are partially replaced with second gate electrodes (230) (see FIG. 1a) through a subsequent process. The second sacrificial insulating layers (210) may be made of a different material from the second interlayer insulating layers (220) and may be formed of a material that can be etched with etch selectivity under specific etching conditions with respect to the second interlayer insulating layers (220). For example, the second interlayer insulating layer (220) may be made of at least one of silicon oxide and silicon nitride, and the second sacrificial insulating layers (210) may be made of a different material from the second interlayer insulating layer (220) selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In embodiments, the thicknesses of the second interlayer insulating layers (220) may not all be the same. The thickness and the number of films constituting the second interlayer insulating layers (220) and the first sacrificial insulating layers (110) may be varied from those shown. An upper insulating layer (250) may be further formed on the uppermost second sacrificial insulating layer (210).

In the second region (B), the photolithography process and the etching process can be repeatedly performed on the second sacrificial insulating layers (210) using a mask layer so that the upper second sacrificial insulating layers (210) extend shorter than the lower second sacrificial insulating layers (210). As a result, the second sacrificial insulating layers (210) can form a step-shaped step structure in predetermined units.

The buffer insulating layer (215), the first horizontal insulating layers (225), and the second horizontal insulating layers (235) arranged in the third region (C) may be laminated with the same material in the same step as the second interlayer insulating layers (220) and the second sacrificial insulating layers (210), respectively. The photolithography process and the etching process may be repeatedly performed on the second horizontal insulating layers (235) using a mask layer so that the upper second horizontal insulating layers (235) extend shorter than the lower second horizontal insulating layers (235). Thereby, the second horizontal insulating layers (235) may form a step structure in a step shape in a predetermined unit. In an exemplary embodiment, it may also be possible to form them in different process steps. In this case, it may not be a step structure in a step shape.

During an etching process for forming a step-shaped step structure of a dummy laminated structure (DS), the first horizontal insulating layers (225) and the second horizontal insulating layers (235) that are laminated and extended in the x direction of the sidewall of the buffer insulating layer (215) may not be partially removed, thereby forming a first pattern (225a) and a second pattern (235a), thereby forming a dummy pattern (DP). The first pattern (225a) and the second pattern (235a) may be laminated in multiple layers, and in this case, may have a form in which they are alternately laminated. In an exemplary embodiment, the shape and number of the first pattern (225a) and the second pattern (235a) may be variously changed.

The second capping insulating layer (290) may cover the upper stacked structure of the second sacrificial insulating layers (210) and the second interlayer insulating layers (220), the first capping insulating layer (190) and the dummy stacked structure (DS), and may be stacked to extend to the fourth region (D). After the second capping insulating layer (290) is stacked, a planarization process may be performed. The planarization process may be a chemical mechanical polishing process (CMP). During the planarization process, since a step is formed between the dummy stacked structure (DS) and the memory stacked structure (CS) due to the buffer insulating layer (215), unnecessary removal and damage to the memory stacked structure (CS) can be prevented. In addition, since a step is formed between the dummy stacked structure (DS) and the stacked structure of the fourth region (D) due to the buffer insulating layer (215), unnecessary removal of the stacked structure of the fourth region (D) can be prevented.

Referring to FIG. 4e, channel structures (CH) penetrating the upper laminated structure and the lower laminated structure can be formed.

First, at a position corresponding to the channel structures (CH) of FIG. 1a, an etching process is performed to penetrate the upper laminated structure to form a channel through-hole, and then the first through-sacrificial layer (115) is removed to extend the channel through-hole to the lower laminated structure. Next, the channel through-hole can be filled to form the channel structures (CH). The sidewalls of the channel structures (CH) may not be perpendicular to the upper surface of the second substrate (101). The channel structures (CH) may be formed to recess a portion of the second substrate (101). As illustrated in FIG. 1b, a channel layer (140) and a channel insulating layer (150) may be formed within the channel structures (CH). The channel layers (140) may be formed to have a uniform thickness using an ALD or CVD process. The channel insulating layer (150) is formed to fill the internal space of the channel layers (140) and may be an insulating material. However, according to embodiments, the space between the channel layers (140) may be filled with a conductive material instead of a channel insulating layer (150). After the channel structures (CH) are formed, a planarization process may be performed. During the planarization process, Since a step is formed between the dummy stacked structure (DS) and the memory stacked structure (CS) due to the buffer insulating layer (215), unnecessary removal of the memory stacked structure (CS) can be prevented.

Referring to FIG. 4f, first and second gate electrodes (130, 230) can be formed.

In areas corresponding to the separation region (SR) (see Figure 1b), Openings penetrating the laminated structure of the first and second sacrificial insulating layers (110, 210) and the first and second interlayer insulating layers (120, 220) can be formed, and tunnel sections can be formed by removing a portion of the first and second sacrificial insulating layers (110, 210) through the openings.

First, after forming separate sacrificial spacer layers within the openings, the second source sacrificial layer (112) can be selectively removed, and then the first source sacrificial layers (111) can be removed. The first and second source sacrificial layers (111, 112) can be removed, for example, by a wet etching process. A conductive material can be deposited in the areas where the first and second source sacrificial layers (111, 112) are removed to form a first conductive layer (104), and then the sacrificial spacer layers can be removed within the openings. Next, a conductive material can be embedded in the tunnel portions where the first and second sacrificial insulating layers (110, 210) are partially removed to form first and second gate electrodes (130, 230). The conductive material can include a metal, polycrystalline silicon, or a metal silicide material. After forming the first and second gate electrodes (130, 230), the conductive material deposited within the openings can be removed through an additional process and then filled with an insulating material.

Next, referring back to FIG. 1A, additional first to third insulating layers (295, 296, 297) can be laminated, channel contact plugs (270), gate contact plugs (262), substrate contact plugs (264), through vias (267), bit lines (280), and upper wiring lines (285) can be formed, and the fourth region (D) can be cut and removed.

The channel contact plugs (270) may be formed to be electrically connected to the channel structures (CH), and the gate contact plugs (262) may be formed to be electrically connected to the first and second gate electrodes (130, 230) in the second region (B). In addition, the substrate contact plug (264) may be formed to be connected to the second substrate (101) at an end of the second region (B). The channel contact plugs (270), the gate contact plugs (262), and the substrate contact plug (264) may be formed at different depths, but may be formed by simultaneously forming contact holes using an etch stop layer or the like and then filling the contact holes with a conductive material. However, in some embodiments, some of the channel contact plugs (270), the gate contact plugs (262), and the substrate contact plug (264) may be formed in different process steps.

The upper contact plugs (270) can be formed by forming the third insulating layer (297), removing a portion by etching, and filling in a conductive material. The bit line (280) and the upper wiring lines (285) can be formed, for example, by depositing a conductive material and then patterning it.

Next, the fourth region (D) can be cut and removed in the chip region separation process.

By this, the semiconductor device (100) of FIGS. 1a to 2 can be finally manufactured.

The present invention is not limited to the above-described embodiments and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and change, and combinations of the embodiments may be made by those skilled in the art within the scope that does not depart from the technical spirit of the present invention described in the claims, and this will also fall within the scope of the present invention.

CH: Channel structure GS1, GS2: Laminated structure
SR: Separation Area 101: Second Substrate
104: 1st challenge layer 105: 2nd challenge layer
120, 220: Interlayer insulation layer 130, 230: Gate electrode
CH: Channel structure SR: Separation region
140: Channel layer 150: Channel insulation layer
160: Intermediate interlayer insulation layer 190: First capping insulation layer
215: Buffer insulation layer DP: Dummy pattern
225a: Pattern 1 235a: Pattern 2
DS: Dummy laminated structure 225, 235: Horizontal insulation layer
290: Second capping insulating layer 301: First substrate
320: Circuit element 370: Circuit contact plug
380: Circuit wiring line

Claims (10)

A first substrate, a peripheral circuit area including circuit elements provided on the first substrate;
A memory stack structure including a second substrate disposed on the first substrate, a first stacked structure including first gate electrodes and first interlayer insulating layers alternately and repeatedly stacked on the second substrate, and a second stacked structure disposed on the first stacked structure and including second gate electrodes and second interlayer insulating layers alternately and repeatedly stacked on the first stacked structure; and
A dummy laminated structure including first horizontal insulating layers spaced apart from the first substrate and the peripheral circuit area in a first direction perpendicular to the first substrate, and spaced apart from the memory laminated structure in a second direction perpendicular to the first direction and laminated spaced apart from each other, and second horizontal insulating layers alternately laminated with the first horizontal insulating layers,
A semiconductor device wherein a first distance from the first substrate to the lowermost second horizontal insulating layer among the second horizontal insulating layers is greater than a second distance from the first substrate to the lowermost second gate electrode among the second gate electrodes.
In the first paragraph,
Each of the first laminated structure and the second laminated structure includes a central region and a step region,
A semiconductor device further comprising a first capping insulating layer disposed between the peripheral circuit region and the dummy laminated structure and extending onto the step region of the first laminated structure, and a buffer insulating layer disposed between the first capping insulating layer and the dummy laminated structure.
In the second paragraph,
A semiconductor device wherein the difference between the first distance and the second distance is equal to the thickness of the buffer insulating layer.
In the second paragraph,
A semiconductor device wherein the first capping insulating layer and the buffer insulating layer comprise the same material.
In the second paragraph,
A semiconductor device comprising a dummy pattern disposed on at least one sidewall of the buffer insulating layer and comprising the same material as the second horizontal insulating layer.
In clause 5,
A semiconductor device in which the above dummy patterns are respectively arranged on both side walls of the buffer insulating layer.
In clause 5,
The above dummy pattern includes a first pattern and a second pattern that are arranged in a stacked manner,
A semiconductor device wherein the first pattern comprises the same material as the second horizontal insulating layer.
In the first paragraph,
A semiconductor device wherein a distance from the substrate to the upper surface of the uppermost second horizontal insulating layer among the second horizontal insulating layers is greater than a distance from the substrate to the upper surface of the uppermost second gate electrode among the second gate electrodes.
In the first paragraph,
A semiconductor device further comprising a wiring penetrating the dummy laminated structure and electrically connected to the peripheral circuit area.
A first substrate, a peripheral circuit area including circuit elements provided on the first substrate;
A memory stack structure including a second substrate disposed on the first substrate, a first stacked structure including first gate electrodes and first interlayer insulating layers alternately and repeatedly stacked on the second substrate, and a second stacked structure disposed on the first stacked structure and including second gate electrodes and second interlayer insulating layers alternately and repeatedly stacked on the second substrate;
A dummy laminated structure including first horizontal insulating layers spaced apart from the first substrate and the peripheral circuit area in a first direction perpendicular to the first substrate, and spaced apart from the memory laminated structure in a second direction perpendicular to the first direction and laminated spaced apart from each other, and second horizontal insulating layers alternately laminated with the first horizontal insulating layers;
A buffer insulating layer disposed between the peripheral circuit area and the dummy laminated structure in the first direction and disposed on top of the first laminated structure; and
A dummy pattern is disposed on at least one sidewall of the buffer insulating layer and includes a first pattern and a second pattern that are sequentially laminated,
The first pattern comprises the same material as the first horizontal insulating layers,
A semiconductor device wherein the second pattern comprises the same material as the second horizontal insulating layers.

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