KR102545297B1 - Layer Structure for the channel line of Field Effect Transistors - Google Patents

Abstract

A channel improvement structure of a field effect transistor and a process method thereof are presented. The process method for a channel enhancement structure of a field effect transistor proposed in the present invention includes the steps of implanting ions for channel formation into a silicon substrate, and forming an intermediate insulating film through a thermal oxidation process in the process of epitaxially growing silicon on the silicon substrate. alternately depositing a formed silicon layer, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium sacrificial layer having a higher germanium ratio than the silicon-germanium sacrificial layer; dummy gates on the deposited silicon-germanium sacrificial layer; and forming source/drain electrode recesses through dry etching, etching the silicon-germanium sacrificial layer using an etching material, epitaxially depositing source/drain regions, etching the silicon-germanium, , depositing an insulating material to form internal spacers, etching the insulating material of the channel portion, and forming a gate dielectric material and a gate electrode.

Description

Channel improvement structure of field effect transistor {Layer Structure for the channel line of Field Effect Transistors}

The present invention relates to a structure and a process method for improving a vertical direction bending phenomenon of a channel generated during a process of manufacturing a field effect transistor.

As the miniaturization of the planar field effect transistor structure according to the prior art approaches the limit, a fin-type field effect transistor structure that wraps the gate in a fin shape is attracting attention as a new alternative. As the fin-type field effect transistor structure with increased contact area between the gate and the channel is applied, leakage current is reduced and consequently, the effect of lowering the driving voltage can be enjoyed. However, as the aspect ratio of the fin-type field effect transistor increases due to miniaturization of the chip, and process costs accordingly increase, the need for a new field effect transistor structure has been raised.

Gate All Around (GAA) Field Effect Transistor (FET) features a structure in which gates surround all four sides of the channel, unlike the existing fin field effect transistor (FinFET) structure. to be Through this, the current control ability of the gate can be improved, thereby reducing the gate leakage current and lowering the driving voltage. In addition, the ease of processing could be improved by having a smaller aspect ratio than the fin-type field effect transistor. The gate all-around nanosheet field effect transistor is a structure in which a conventional wire-shaped channel is extended into a sheet shape, and the current moving area is greatly increased.

In the gate all-around nanosheet field effect nanosheet transistor, the silicon channel is exposed in the form of a bridge during the process. When exposed to a high-temperature process while the silicon channel is exposed, a bending phenomenon occurs in a vertical direction due to thermal expansion of the material, and thus the accuracy of nanostructure alignment of the device is deteriorated.

Korean Patent Publication No. 10-2017-0045104 (2017.04.26)

A technical problem to be achieved by the present invention is to provide a channel improvement structure of a field effect transistor and a process method for improving a vertical warp phenomenon of a silicon layer during a high-temperature process of a field effect transistor. In particular, an appropriate insulating material is deposited between the silicon layers to improve the vertical channel bending phenomenon of the gate all-around nanosheet field effect transistor in which the silicon layer is exposed to a high-temperature process in the form of a bridge during the fabrication process.

In one aspect, the process method for a channel enhancement structure of a field effect transistor proposed in the present invention includes the steps of implanting ions for channel formation into a silicon substrate, and a thermal oxidation process in the process of epitaxially growing silicon on the silicon substrate. Alternately depositing a silicon layer on which an intermediate insulating film is formed, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium sacrificial layer having a higher germanium ratio than the silicon-germanium sacrificial layer, the deposited silicon-germanium sacrificial layer Forming a dummy gate on the surface and forming source/drain electrode recesses through dry etching, etching the silicon-germanium sacrificial layer using an etching material, and epitaxially depositing source/drain regions, silicon - Etching germanium and depositing an insulating material to form internal spacers, etching the insulating material of the channel portion, and forming a gate dielectric material and a gate electrode.

In the process of epitaxially growing silicon on the silicon substrate, a silicon layer in which an intermediate insulating film is formed through a thermal oxidation process, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium having a higher germanium ratio than the silicon-germanium sacrificial layer In the step of alternately depositing sacrificial layers, when etching silicon-germanium to form internal spacers, a difference in deposition thickness occurs depending on the location of the channel, so that over-etching is not required, so that the vertical displacement is kept constant. In order to do so, an intermediate insulating film is formed between the silicon layers.

An insulating material of an intermediate insulating layer between the silicon layers according to an embodiment of the present invention may include an insulating material having a lower coefficient of thermal expansion than silicon.

According to one embodiment of the present invention, the insulating material of the intermediate insulating film between the silicon layers includes silicon dioxide, and the thickness ratio of the intermediate insulating film to the silicon layer is adjusted according to the electrical characteristics and processes of the field effect transistor. can

According to one embodiment of the present invention, a thickness ratio of the intermediate insulating film to the silicon layer may be 10 to 75%.

In another aspect, the channel improvement structure of the field effect transistor proposed in the present invention includes a silicon substrate implanted with ions for channel formation, a silicon layer alternately deposited on the silicon substrate, upper and lower silicon-germanium sacrificial layers, and An intermediate silicon-germanium sacrificial layer is formed on the silicon layer through a thermal oxidation process during epitaxial growth of silicon, and the intermediate silicon-germanium sacrificial layer contains more germanium than the upper and lower silicon-germanium sacrificial layers. ratio could be higher.

In the channel improvement structure of the field effect transistor proposed in the present invention, a dummy gate formed on the deposited silicon-germanium sacrificial layer and source/drain electrode recesses are formed through dry etching, and then the silicon-germanium sacrificial layer is formed. A gate dielectric material formed by etching using an etching material, etching the source/drain region and silicon-germanium deposited through epitaxial deposition, and etching the insulating material of the internal spacer and channel portion formed by depositing an insulating material, and A gate electrode may be further included.

Through the channel enhancement structure of the field effect transistor according to the embodiments of the present invention, it is possible to improve the vertical direction warpage of the silicon layer during a high-temperature process of the field effect transistor. In particular, by depositing an appropriate insulating material between the silicon layers, it is possible to improve the vertical channel warpage of the gate all-around nanosheet field effect transistor in which the silicon layer is exposed to a high-temperature process in the form of a bridge during the fabrication process.

1 is a view showing the entire process of a gate all-around nanosheet field effect transistor according to the prior art.
FIG. 2 is a view for explaining a vertical displacement aspect during a process of depositing an insulating film of a field effect transistor according to an embodiment of the present invention.
3 is a flowchart illustrating a method of processing a channel structure of a field effect transistor according to an embodiment of the present invention.
4 is a diagram showing a channel structure of a field effect transistor according to an embodiment of the present invention.
5 is a view showing a vertical displacement pattern according to a ratio of an intermediate insulating film in a silicon layer according to an embodiment of the present invention.
6 is a graph showing vertical displacement according to a ratio of an intermediate insulating film in a silicon layer according to an embodiment of the present invention.

The present invention relates to a structure and process method for improving vertical warping of a channel generated during the process of a field effect transistor, and more particularly, by adding an intermediate insulating film to a formed channel to improve vertical displacement. In addition, it relates to a structure and a process method for improving the electrical characteristics of a channel. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing the entire process of a gate all-around nanosheet field effect transistor according to the prior art.

The entire process of the gate all-around nanosheet field effect transistor according to the prior art includes implanting ions for channel formation into a silicon substrate, a silicon layer on the silicon substrate, upper and lower silicon-germanium sacrificial layers, and upper and lower silicon-germanium alternately depositing intermediate silicon-germanium sacrificial layers having a higher germanium ratio than the sacrificial layer, forming dummy gates on the deposited silicon-germanium sacrificial layer, and forming source/drain electrode recesses through dry etching; Step, etching the silicon-germanium sacrificial layer using an etching material, epitaxially depositing source/drain regions, etching the silicon-germanium, depositing an insulating material to form internal spacers, and Etching the insulating material and forming a gate dielectric material and a gate electrode.

1(a) is a diagram illustrating a process of implanting channel isolation ions onto a silicon substrate.

1(b) shows a process of alternately depositing a silicon layer (ie, a silicon channel), upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium sacrificial layer having a higher germanium ratio than the silicon-germanium sacrificial layer. It is a drawing that represents

FIG. 1(c) is a diagram illustrating a process of forming a dummy gate, and FIG. 1(d) is a diagram illustrating a process of forming source/drain electrode recesses through dry etching.

1(e) is a diagram illustrating a process of etching a silicon-germanium region using a material having an appropriate etching ratio.

1(f) is a diagram illustrating a process of epitaxially depositing source/drain regions.

1(g) is a diagram illustrating a process of forming an internal spacer by etching silicon-germanium and depositing an appropriate insulating material.

1(h) is a view showing a process of etching the insulating material of the channel portion.

1(i) is a diagram illustrating a process of forming a gate dielectric material and a gate electrode.

In the process of depositing an insulating material on the channel of FIG. 1(g), in a situation where the nanosheet channel is exposed to a high temperature deposition process, when the silicon layer is exposed to a high temperature, a phenomenon that is bent in the vertical direction due to thermal expansion of the material may occur. can

The present invention proposes a structure for improving a channel of a field effect transistor and a process method for improving vertical warping of a silicon layer during a high-temperature process of such a field effect transistor. In particular, an appropriate insulating material is deposited between the silicon layers to improve the vertical channel bending phenomenon of the gate all-around nanosheet field effect transistor in which the silicon layer is exposed to a high-temperature process in the form of a bridge during the fabrication process.

FIG. 2 is a view for explaining a vertical displacement aspect during a process of depositing an insulating film of a field effect transistor according to an embodiment of the present invention.

Figure 2 shows the vertical displacement of the gate all-around nanosheet field effect transistor that occurs during a high-temperature deposition process (Plasma Enhanced Chemical Vapor Deposition; PECVD). When this problem occurs, there is a disadvantage in that the difficulty of the subsequent process increases.

For example, when wet etching is performed to form internal spacers in FIG. 1 (h), if the difference in deposition thickness is not constant depending on the position of the silicon layer (ie, silicon channel), reliable removal of the insulating film Over-etching must be performed to achieve this, and as a result, a problem in that etching proceeds to the inner spacer to be maintained may occur.

The present invention proposes a method of depositing an appropriate insulating material between silicon layers (ie, silicon channels) in order to improve the vertical displacement problem. The insulating material of the intermediate insulating film can be selected according to thermal characteristics or ease of processing, and in one embodiment of the present invention, a silicon dioxide film is applied as an intermediate insulating film.

3 is a flowchart illustrating a method of processing a channel structure of a field effect transistor according to an embodiment of the present invention.

In the process method of the channel structure of the proposed field effect transistor, injecting ions for channel formation into a silicon substrate (310), an intermediate insulating film is formed through a thermal oxidation process in the process of epitaxially growing silicon on the silicon substrate Alternately depositing a silicon layer, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium sacrificial layer having a higher germanium ratio than the silicon-germanium sacrificial layer (320). Forming gates and forming source/drain electrode recesses through dry etching (330), etching the silicon-germanium sacrificial layer using an etching material, and epitaxially depositing source/drain regions (340) ), etching the silicon-germanium and depositing an insulating material to form an internal spacer (350), and etching the insulating material of the channel portion and forming a gate dielectric material and a gate electrode (360). .

As described above, in step 310, ions for channel formation are implanted into the silicon substrate.

In step 320, in the process of epitaxially growing silicon on the silicon substrate, a silicon layer in which an intermediate insulating film is formed through a thermal oxidation process, upper and lower silicon-germanium sacrificial layers, and a germanium ratio than the silicon-germanium sacrificial layer Alternately deposit higher intermediate silicon-germanium sacrificial layers.

According to an embodiment of the present invention, when etching silicon-germanium to form internal spacers in step 320 (step 350), a difference in deposition thickness occurs depending on the position of the channel, resulting in over-etching. An intermediate insulating film is formed between the silicon layers to keep the vertical displacement constant so that it is not needed.

The insulating material of the intermediate insulating layer between the silicon layers may include an insulating material having a lower coefficient of thermal expansion than silicon.

The insulating material of the intermediate insulating film between the silicon layers according to an embodiment of the present invention includes silicon dioxide, and the thickness ratio of the intermediate insulating film to the silicon layer may be adjusted according to electrical characteristics and processes of the field effect transistor. there is. For example, a thickness ratio of the intermediate insulating film to the silicon layer may be 10 to 75%.

In step 330, a dummy gate is formed on the deposited silicon-germanium sacrificial layer, source/drain electrode recesses are formed through dry etching, and in step 340, an etching material is applied to the silicon-germanium sacrificial layer. etching, and epitaxially depositing source/drain regions.

In step 350, silicon-germanium is etched, an insulating material is deposited to form internal spacers, and finally, in step 360, the insulating material of the channel part is etched, and a gate dielectric material and a gate electrode are formed.

4 is a diagram showing a channel structure of a field effect transistor according to an embodiment of the present invention.

The channel structure of the proposed field effect transistor includes a silicon substrate 410 implanted with ions for channel formation, silicon layers 420 alternately deposited on the silicon substrate 410, and upper and lower silicon-germanium sacrificial layers 430. and an intermediate silicon-germanium sacrificial layer 440;

In the silicon layer 420, an insulator layer 421 is formed through a thermal oxidation process in the process of epitaxially growing silicon, and the intermediate silicon-germanium sacrificial layer 440 forms the upper and lower silicon-germanium sacrificial layers. It may have a higher proportion of germanium than layer 430 .

In the channel structure of the proposed field effect transistor, a dummy gate is formed on the deposited silicon-germanium sacrificial layer, and source/drain electrode recesses are formed through dry etching. Thereafter, the silicon-germanium sacrificial layer is etched using an etching material, and source/drain regions are epitaxially deposited. Internal spacers are formed by etching the silicon-germanium and depositing an insulating material, and finally, the insulating material of the channel part is etched, and a gate dielectric material and a gate electrode are formed.

According to an embodiment of the present invention, when etching silicon-germanium to form internal spacers, a difference in deposition thickness occurs depending on the location of a channel, so that over-etching is not required, and the vertical displacement is kept constant. To do this, an intermediate insulating film 421 is formed between the silicon layers 420 .

An insulating material of the intermediate insulating layer 421 between the silicon layers 420 may include an insulating material having a lower coefficient of thermal expansion than silicon.

An insulating material of the intermediate insulating film 421 between the silicon layers 420 according to an embodiment of the present invention includes silicon dioxide, and the thickness ratio of the intermediate insulating film 421 to the silicon layer 420 is It can be adjusted according to the electrical characteristics and process of the effect transistor. For example, a thickness ratio of the intermediate insulating layer 421 to the silicon layer 420 may be 10 to 75%.

5 is a view showing a vertical displacement pattern according to a ratio of an intermediate insulating film in a silicon layer according to an embodiment of the present invention.

5 shows the distribution of vertical displacement according to the ratio of the intermediate insulating film to the nanosheet channel thickness. By adding an intermediate insulating film, the displacement effect in the vertical direction can be confirmed. The ratio of the intermediate insulating film according to an embodiment of the present invention may be adjusted according to the electrical characteristics of the device or the ease of the process.

6 is a graph showing vertical displacement according to a ratio of an intermediate insulating film in a silicon layer according to an embodiment of the present invention.

As the ratio of the intermediate insulating film in the silicon layer increases, the vertical displacement decreases. Accordingly, an intermediate layer having an appropriate thickness may be employed in consideration of electrical characteristics of the device and ease of processing.

Referring to FIG. 6, when the thickness ratio of the intermediate insulating film is increased to 40%, it can be confirmed that there is an effect of mitigating vertical displacement by about 20% compared to the structure before application.

According to one embodiment of the present invention, by adding an intermediate insulating film to the channel of the field effect transistor, it is possible to improve vertical deformation that may occur during a manufacturing process. Through this, it is possible to reduce the process difficulty and process cost in the subsequent process.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. A processing device may run an operating system (OS) and one or more software applications running on the operating system.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (7)

implanting ions to form a channel into a silicon substrate;
In the process of epitaxially growing silicon on the silicon substrate, a silicon layer in which an intermediate insulating film is formed through a thermal oxidation process, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium having a higher germanium ratio than the silicon-germanium sacrificial layer alternately depositing sacrificial layers;
forming a dummy gate on the deposited silicon-germanium sacrificial layer and forming source/drain electrode recesses through dry etching;
etching the silicon-germanium sacrificial layer using an etchant and epitaxially depositing source/drain regions;
forming internal spacers by etching silicon-germanium and depositing an insulating material; and
Etching the insulating material of the channel portion and forming a gate dielectric material and a gate electrode
including,
In the process of epitaxially growing silicon on the silicon substrate, a silicon layer in which an intermediate insulating film is formed through a thermal oxidation process, upper and lower silicon-germanium sacrificial layers, and an intermediate silicon-germanium having a higher germanium ratio than the silicon-germanium sacrificial layer The step of alternately depositing the sacrificial layer,
When etching the silicon-germanium to form the internal spacer, a difference in deposition thickness occurs depending on the position of the channel, so that over-etching is not required, so as to keep the vertical displacement constant. form,
The insulating material of the intermediate insulating film between the silicon layers includes an insulating material having a lower coefficient of thermal expansion than silicon.
Channel structure process method of field effect transistor. delete delete According to claim 1,
The insulating material of the intermediate insulating film between the silicon layers includes silicon dioxide,
The thickness ratio of the intermediate insulating film to the silicon layer is adjusted according to the electrical characteristics and process of the field effect transistor
Channel structure process method of field effect transistor. According to claim 1,
The thickness ratio of the intermediate insulating film to the silicon layer is 10 to 75%
Channel structure process method of field effect transistor. delete delete

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