KR102221155B1 - Organic light emitting display device and method for driving the same - Google Patents

Abstract

The present invention relates to an organic light emitting display device and a driving method thereof. An organic light emitting display device according to an embodiment of the present invention includes a display panel; A scan driver; A data driver; Power source; And a timing control unit. The display panel includes data lines, scan lines, and pixels connected to the data lines and scan lines. The scan driver supplies scan signals to the scan lines. The data driver supplies data voltages to the data lines in synchronization with the scan signals. The power supply source supplies power voltages to the pixels, the scan driver, and the data driver. The timing control unit divides one frame period into an analog driving period and a digital driving period to control operation timings of the scan driving unit and the data driving unit and power supply timing of the power supply source. Further, the scan driver supplies one scan signal to the scan line during the analog driving period, and supplies a plurality of scan signals to the scan line during the digital driving period of one frame period. Also, the power supply source supplies a first power voltage as a first level voltage during the analog driving period, and supplies the first power voltage as a second level voltage lower than the first level voltage during the digital driving period.

Description

Organic light emitting display device and its driving method {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to an organic light emitting display device and a driving method thereof.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Flat panel displays include a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display.

Among flat panel displays, an organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. The organic light emitting display device has an advantage of having a fast response speed and being driven with low power consumption.

An organic light emitting display device includes a data driver that supplies data voltages to data lines, a scan driver that supplies scan signals to the scan lines, and pixels arranged in a region partitioned by the scan lines and the data lines. do. The pixel emits light with a predetermined luminance by controlling a current supplied to an organic light emitting diode according to a data voltage supplied to a gate electrode of a driving transistor.

The pixels of the organic light emitting display device may be driven by an analog driving method or a digital driving method. The analog driving method is a method of controlling the amount of light emitted from the organic light emitting diode device by controlling the current between the drain and source of the driving transistor according to the data voltage. The digital driving method is a method of controlling the light emission period of the organic light emitting diode device by controlling the turn-on of the driving transistor according to the data voltage.

The analog driving method has the advantage of high gradation expression and low driving frequency, but has a disadvantage in that the circuit complexity of the pixel is high and is greatly affected by the uniformity of the threshold voltage of the driving transistor. The digital driving method has the advantage that the circuit complexity of the pixel is low and is not significantly affected by the uniformity of the threshold voltage of the driving transistor, but has disadvantages of low gradation expression power and high driving frequency. Accordingly, in order to compensate for the disadvantages of the analog driving method and the digital driving method, a hybrid driving method combining an analog driving method and a digital driving method has been proposed.

An embodiment of the present invention provides an organic light emitting display device driven by a hybrid driving method combining an analog driving method and a digital driving method, and a driving method thereof.

An organic light emitting display device according to an embodiment of the present invention includes: a display panel including data lines, scan lines, and pixels connected to the data lines and the scan lines; A scan driver supplying scan signals to the scan lines; A data driver for supplying data voltages to the data lines in synchronization with the scan signals; A power supply source supplying power voltages to the pixels, the scan driver, and the data driver; And a timing control unit that divides one frame period into an analog driving period and a digital driving period to control an operation timing of the scan driving unit and the data driving unit and a power supply timing of the power supply source, wherein the scan driving unit is the analog driving period. One scan signal is supplied to the scan line during the period, and a plurality of scan signals are supplied to the scan line during a digital driving period of one frame period, and the power supply source applies a first power voltage to a first level voltage during the analog driving period. And supplying the first power voltage at a second level voltage lower than the first level voltage during the digital driving period.

A driving method of an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel including data lines, scan lines, and pixels connected to the data lines and scan lines. A driving method comprising: supplying scan signals to the scan lines; Supplying data voltages to the data lines in synchronization with the scan signals; And supplying power voltages to the pixels, the scan driver, and the data driver, wherein the supplying of the scan signals to the scan lines comprises: applying one scan signal to the scan line during the analog driving period of one frame period. Supplying, supplying a plurality of scan signals to the scan line during a digital driving period of one frame period, and supplying power voltages to the pixels, the scan driver, and the data driver include: a first power voltage during the analog driving period Is supplied as a first level voltage, and the first power voltage is supplied as a second level voltage lower than the first level voltage during the digital driving period.

An embodiment of the present invention is driven by a hybrid driving method that combines an analog driving method and a digital driving method. Particularly, according to an exemplary embodiment of the present invention, by driving a pixel by an analog driving method during an analog driving period to represent the upper p bits, it is possible to increase gray scale expression power. At the same time, according to an exemplary embodiment of the present invention, a pixel is driven by a digital driving method during the digital driving period to represent the lower q bits, so that a low gradation can be expressed regardless of the threshold voltage of the driving transistor.

In addition, according to an embodiment of the present invention, the pixel P is driven by the analog driving method during the analog driving period AP to represent the lower p bits, and the pixel P is converted to the digital driving method during the digital driving period DP. By driving by and expressing the lower q bits, power consumption can be reduced.

Further, in the embodiment of the present invention, since only the turn-on and turn-off of the driving transistor is controlled in each of the sub-field periods of the digital driving period, the first power supply voltage is set to a second voltage level lower than the first voltage level. Supply. As a result, the embodiment of the present invention can reduce power consumption.

1 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.
3 is a block diagram showing in detail a timing control unit according to an embodiment of the present invention.
4 is a flowchart illustrating a method of driving an organic light emitting display device according to a first embodiment of the present invention.
5 is an exemplary view showing driving of a display panel during one frame period.
6 is an exemplary view showing a voltage level of a first power voltage in one frame period.
7 is a flowchart illustrating a method of driving an organic light emitting display device according to a second exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail, focusing on an organic light emitting display device, with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted. The names of the constituent elements used in the following description are selected in consideration of ease of preparation of the specification, and may be different from the names of actual products.

1 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 1, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10, a scan driver 20, a data driver 30, a timing controller 40, a power supply source 50, and the like. Equipped.

The display panel 10 is formed such that data lines DL1 to DLm, m is a positive integer of 2 or more, and scan lines SL1 to SLn, n is a positive integer of 2 or more, to cross each other. Pixels P arranged in a matrix form are formed on the display panel 10 in a cross region between the data lines DL1 to DLm and the scan lines SL1 to SLn.

As shown in FIG. 2, the pixel P is a k-th (k is a positive integer satisfying 1≦k≦n) scan line, j-th (j is a positive integer satisfying 1≦j≦m) data line, and It may be connected to the first power voltage line VDDL and the second power voltage line VSSL. Referring to FIG. 2, the pixel P may include a driving transistor DT, an organic light emitting diode (OLED), a scanning transistor ST, and a capacitor C.

The driving transistor DT is formed between the organic light emitting diode OLED and the first power voltage line VDDL, and controls the amount of current flowing to the organic light emitting diode OLED. Specifically, since the drain-source current flowing through the channel of the driving transistor DT varies according to the data voltage supplied to the gate electrode of the driving transistor DT, the amount of current flowing through the organic light emitting diode OLED is determined by the driving transistor ( DT) can be controlled by controlling the data voltage supplied to the gate electrode.

The gate electrode of the driving transistor DT is connected to the second electrode of the scan transistor ST, the first electrode is connected to the first power voltage line VDDL, and the second electrode is an anode of the organic light emitting diode OLED. Connected to the electrode. Here, the first electrode may be a source electrode or a drain electrode, and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

The organic light emitting diode OLED emits light according to the current between the drain and source of the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the second electrode of the driving transistor DT, and the cathode electrode is connected to the low potential voltage line VSSL.

The scan transistor ST is connected between the gate electrode of the driving transistor DT and the j-th data line Dj. The scan transistor ST is turned on by the scan signal of the kth scan line SLk to supply the data voltage of the jth data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the scan transistor ST is connected to the k-th scan line SLk, the first electrode is connected to the j-th data line Dj, and the second electrode is connected to the gate electrode of the driving transistor DT. .

The capacitor C is formed between the gate electrode of the driving transistor DT and the first power voltage line VDDL. The capacitor C maintains the data voltage supplied to the gate electrode of the driving transistor DT for a predetermined period.

Each of the semiconductor layers of the driving transistor DT and the scan transistor ST may be formed of polysilicon, but is not limited thereto, and may be formed of either a-Si or an oxide semiconductor. In FIG. 3, it should be noted that the description is focused on that the driving transistor DT and the scan transistor ST are formed in a P type.

In addition, the pixel P may further include a compensation circuit (not shown) for compensating the threshold voltage of the driving transistor DT. In this case, the compensation circuit (not shown) may include at least one transistor. The compensation circuit (not shown) senses the threshold voltage of the driving transistor DT and reflects it to the gate electrode, so that the drain-source current Ids of the driving transistor DT is equal to the threshold voltage Vth of the driving transistor DT. You can avoid relying on it.

The scan driver 20 supplies scan signals to the scan lines SL1 to SLn in response to the scan timing control signal SCS. The scan driver 20 may sequentially supply scan signals to the scan lines SL1 to SLn. In this case, the scan driver 20 may be implemented in a shift register method. The shift register type scan driver 20 includes a shift register that sequentially generates output signals, a level shifter and an output buffer for converting the output signals of the shift register into a swing width suitable for driving the transistor of the pixel P. I can. Alternatively, the scan driver 20 may non-sequentially supply scan signals to the scan lines SL1 to SLn. In this case, the scan driver 20 may be implemented in a decoder type.

The data driver 30 includes a plurality of source drive ICs. Each of the source drive ICs receives digital video data DATA from the timing controller 40. Each of the source drive ICs converts digital video data DATA into data voltages in response to a source timing control signal DCS from the timing controller 40. The source drive ICs supply data voltages to the data lines D1 to Dm in synchronization with each of the scan signals. Accordingly, data voltages are supplied to the pixels P to which the scan signal is supplied.

The timing controller 40 receives digital video data DATA from a host system (not shown) through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 40 receives timing signals including a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing controller 40 generates timing control signals for controlling operation timings of the data driver 20 and the scan driver 30 based on the timing signals. The timing control signals include a scan timing control signal SCS for controlling an operation timing of the scan driver 30 and a data timing control signal DCS for controlling an operation timing of the data driver 20. The timing controller 40 outputs the scan timing control signal SCS to the scan driver 30 and outputs the data timing control signal DCS and digital video data DATA to the data driver 20.

The power supply source 50 supplies a first power voltage to each of the pixels P of the display panel 10 through a first power voltage line VDDL, and a second power supply through the second power voltage line VSSL. Supply voltage. The first power voltage may be set as the high potential voltage ELVDD, and the second power voltage may be set as the low potential voltage ELVSS. In addition, the power supply source 50 may supply a gate-on voltage Von and a gate-off voltage Voff to the scan driver 20. In addition, the power supply source 50 may generate gamma reference voltages and supply them to the data driver 30.

Meanwhile, in an embodiment of the present invention, one frame period is divided into an analog driving period and a digital driving period, and the digital driving period is driven by dividing into a plurality of sub-field periods. The analog driving period means a period in which the pixels are driven by the analog driving method, and the digital driving period means the period in which the pixels are driven by the digital driving method. The analog driving method is a method of controlling the amount of light emitted by the organic light emitting diode device by controlling the current between the drain and the source of the driving transistor of the pixel according to the data voltage. The digital driving method is a method of controlling a light emission period of an organic light emitting diode device by controlling turn-on of a driving transistor of a pixel according to a data voltage.

An embodiment of the present invention is driven by a hybrid driving method in which pixels are driven by an analog driving method during an analog driving period and pixels are driven by a digital driving method during a digital driving period. The hybrid driving method is a driving method that combines an analog driving method and a digital driving method. For this reason, the timing control unit 40 according to an embodiment of the present invention makes the operation timing of the scan driving unit 20 and the data driving unit 30 and the power supply timing of the power supply unit 50 different in the analog driving period and the digital driving period. It must be controlled.

Hereinafter, a timing control method of the timing controller 40 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

3 is a block diagram illustrating in detail a timing control unit and a power supply source according to an embodiment of the present invention. Referring to FIG. 3, the timing control unit 40 according to an embodiment of the present invention includes a main control unit 41, a memory 42, a look-up table 43, and a digital data conversion unit 44.

The main control unit 41 of the timing control unit 40 receives timing signals TC. The timing signals TC include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The main control unit 41 generates a flag signal FL for dividing one frame period into an analog driving period and a digital driving period based on the timing signals TC. For example, the main control unit 41 generates a flag signal FL of a first logic level indicating an analog driving period during an analog driving period, and a flag of a second logic level indicating a digital driving period during the digital driving period. It is possible to generate a signal FL. The main control unit 41 outputs the flag signal FL to the memory 42 and the power supply source 50.

The main control unit 41 generates and outputs the scan timing control signal SCS and the data timing control signal DCS according to the flag signal FL. That is, the main control unit 41 generates a scan timing control signal SCS and a data timing control signal DCS so that the scan driver 20 and the data driver 30 drive the pixels according to the analog driving method during the analog driving period. And print it out. In addition, the main control unit 41 generates a scan timing control signal SCS and a data timing control signal DCS so that the scan driver 20 and the data driver 30 drive the pixels according to the analog driving method during the digital driving period. And print it out. A detailed description of the driving method of the scan driving unit 20 and the data driving unit 30 during the analog driving period and the digital driving period will be described later with reference to FIGS. 4 to 7.

The memory 42 receives digital video data DATA from the digital data conversion unit 44 and receives a flag signal FL from the main control unit 41. Alternatively, the memory 42 may receive digital video data DATA from a host system (not shown). In this case, the look-up table 43 and the digital data conversion unit 44 may be omitted.

The memory 42 may be implemented as a frame memory that stores digital video data DATA of one frame period. In this case, the digital video data DATA to be supplied to the pixel P may be r (r is a positive integer greater than or equal to 2) bit data. The memory 42 outputs p (p is a positive integer) bit of digital video data DATA during the analog driving period according to the flag signal FL, and q (q is p+q=r) during the digital driving period. A satisfactory positive integer) bit of digital video data (DATA) is output. However, since the digital driving period is divided into a plurality of sub-field periods, the memory 42 outputs digital video data DATA in each of the sub-field periods during the digital driving period. In this case, the gray level to be expressed as q-bit digital video data DATA may be defined by a combination of digital video data DATA output in the sub-field periods. A detailed description of this will be described later with reference to FIG. 4.

The look-up table 43 corrects the digital video data DATA according to the position of the pixel P to which the digital video data DATA is supplied in order to increase the uniformity of the luminance of the pixels P of the display panel 10 Correction data CDATA to be used may be stored. In this case, the look-up table 43 may receive the position coordinates of the digital video data DATA as an input address, and output the correction data CDATA according to the input address.

Alternatively, the look-up table 43 uses a current measuring unit (not shown) to compensate for the threshold voltage of the driving transistor DT or deterioration of the organic light emitting diode OLED. Measures the current between the drain and source of the driving transistor DT of P), and stores correction data CDATA for correcting the digital video data DATA supplied to the pixel P according to the measured value of the current. I can.

The digital data conversion unit 44 receives digital video data DATA from a host system (not shown), and receives correction data CDATA from the look-up table 43. The digital data conversion unit 44 converts the digital video data DATA by adding or subtracting the correction data CDATA to the digital video data DATA. The digital data conversion unit 44 outputs the converted digital video data DATA to the memory 42.

The power supply 50 receives the flag signal FL from the main control unit 41. The power supply source 50 adjusts the level of the first power voltage ELVDD supplied to the display panel 10 in the analog driving period and the digital driving period according to the flag signal FL. For example, the power supply 50 supplies the first power voltage ELVDD as the first level voltage during the analog driving period and the second level voltage during the digital driving period. The first level voltage is a level voltage higher than the second level voltage.

4 is a flowchart illustrating a method of driving an organic light emitting display device according to a first exemplary embodiment of the present invention. 5 is an exemplary view showing driving of a display panel during one frame period. 6 is an exemplary diagram showing a voltage level of a first power voltage in one frame period. Hereinafter, a method of driving an organic light emitting display device according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.

First, the main control unit 41 generates a flag signal FL for dividing one frame period into an analog driving period AP and a digital driving period DP based on the timing signals TC. The flag signal FL may be generated at a first logic level during the analog driving period AP and may be generated at a second logic level during the digital driving period DP.

Meanwhile, in FIG. 5, it is illustrated that the analog driving period AP precedes the digital driving period DP in one frame period, but it should be noted that the present invention is not limited thereto. That is, in one frame period, the digital driving period DP may be implemented to precede the analog driving period AP. (S101)

Second, the main control unit 41 outputs the scan timing control signal SCS to the scan driver 20 so that the pixel P is driven by the analog driving method during the analog driving period AP, and the data timing control signal ( DCS) is output to the data driver 30. The memory 42 outputs the digital video data DATA of upper p bits to the data driver 30 during the analog driving period AP. For example, when the digital video data DATA is 6 bits of digital data, the memory 42 may output the upper 2 bits of digital video data DATA to the data driver 30 during the analog driving period AP. I can.

Specifically, the scan driver 20 supplies one scan signal to each of the scan lines SL1 to SLn as shown in FIG. 5 during the analog driving period AP. The data driver 30 converts the high-order p-bit digital video data DATA into a data voltage during the analog driving period AP and supplies it to the data line. The power supply 50 supplies the first power voltage ELVDD as the first level voltage VL1 as shown in FIG. 6 during the analog driving period AP.

As a result, as shown in FIG. 2, the scan transistor ST of the pixel P of the display panel 10 is turned on by the scan signal of the kth scan line SLk during the analog driving period AP. The data voltage of the data line Dj is supplied to the gate electrode of the driving transistor DT. The current between the drain and source of the driving transistor DT of the pixel P varies depending on the data voltage supplied to the gate electrode of the driving transistor DT. Accordingly, the organic light emitting diode OLED of the pixel P emits light according to the data voltage supplied to the gate electrode of the driving transistor DT during the analog driving period AP, thereby representing the gray level of the upper p bits. (S102, S103)

Third, the main control unit 41 outputs the scan timing control signal SCS to the scan driver 20 so that the pixel P is driven by the digital driving method during the digital driving period DP, and the data timing control signal ( DCS) is output to the data driver 30. The memory 42 outputs the digital video data DATA of lower q bits to the data driver 30 during the digital driving period DP. For example, when the digital video data DATA is 6 bits of digital data, the memory 42 may output the lower 4 bits of digital video data DATA to the data driver 30 during the digital driving period DP. I can.

Specifically, the digital driving period DP may be divided into a plurality of sub-field periods, and the sub-field periods may be set differently from each other. For example, as shown in FIG. 5, the digital driving period DP may be divided into four sub-field periods SF1 to SF4, the first sub-field period SF1 has the shortest length, and the fourth sub-field The length of the period SF4 is the longest, and the length of the second sub-field period SF2 may be set to be shorter than the length of the third sub-field period SF3.

In this case, the memory 42 outputs digital video data DATA in each of the sub-field periods SF1 to SF4 of the digital driving period DP. In this case, the digital video data DATA output to each of the sub-field periods SF1 to SF4 is the first digital data capable of turning on the driving transistor DT of the pixel P and the first digital data capable of turning off the driving transistor DT. It is set to one of the second digital data. Accordingly, the gray level to be expressed as the lower q-bit digital video data DATA may be defined by a combination of the digital video data DATA output to the sub-field periods.

For example, when expressing the lower 4 bits during the digital driving period DP, the digital driving period DP may be divided into four sub-field periods SF1 to SF4 as shown in FIG. 5. In this case, the i-th sub-field period SFi may be set to ^{2 i-1 ×t period.} In this case, the first sub-field period SF1 is 2 ^{0 as the t period} The gray level is expressed, and the second sub-field period SF2 is 2 ^{1 as a 2t period.} Represents the gradation, and the third sub-field period SF3 is a 4t period 2 ² The gradation is expressed, and the fourth sub-field period SF4 is an 8t period 2 ³ Gradation can be expressed. That is, when the lower 4 bits are expressed during the digital driving period DP, 16 gray levels can be expressed as shown in FIG. 5.

The scan driver 20 supplies a plurality of scan signals to each of the scan lines SL1 to SLn as shown in FIG. 5 during the digital driving period DP. That is, the scan driver 20 supplies a scan signal to each of the scan lines SL1 to SLn for each subfield period as shown in FIG. 5. The data driver 30 converts the digital video data DATA input for each sub-field period of the digital driving period DP into a data voltage and supplies it to the data line. In this case, when the digital video data DATA input in the sub-field period is the first digital data, the data driver 20 outputs a first data voltage capable of turning on the driving transistor DT. In addition, when the digital video data DATA input in the sub-field period is the second digital data, the data driver 20 outputs a second data voltage capable of turning off the driving transistor DT. The power supply 50 supplies the first power voltage ELVDD as a second level voltage VL2 lower than the first level voltage VL1 as shown in FIG. 6 during the digital driving period DP.

Accordingly, as shown in FIG. 2, the scan transistor ST of the pixel P of the display panel 10 is turned on by the scan signal of the kth scan line SLk in each of the subfield periods SF1 to SF4. As a result, the data voltage of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT. The driving transistor DT of the pixel P is turned on or off by the data voltage supplied to the gate electrode of the driving transistor DT. The driving transistor DT of the pixel P may be turned on when the first data voltage is supplied to the gate electrode of the driving transistor DT and turned off when the second data voltage is supplied.

As a result, the organic light emitting diode OLED of the pixel P emits light when the driving transistor DT is turned on in each of the sub-field periods SF1 to SF4, and does not emit light when it is turned off. The pixel P can express the gray scale of the lower q bits according to the subfield period in which the organic light emitting diode OLED of the pixel P emits light. (S104, S105)

As described above, the first embodiment of the present invention is driven by a hybrid driving method combining an analog driving method and a digital driving method. In particular, according to the first exemplary embodiment of the present invention, the pixel P is driven by the analog driving method during the analog driving period AP to represent the upper p bits, thereby enhancing the gradation expression power. At the same time, the embodiment of the present invention drives the pixel P by the digital driving method during the digital driving period DP to represent the lower q bits, thereby expressing the low gradation regardless of the threshold voltage of the driving transistor DT. I can.

In addition, in the first embodiment of the present invention, since it is only necessary to control the turn-on and turn-off of the driving transistor DT in each of the sub-field periods SF1 to SF4 of the digital driving period DP, the first power supply The voltage ELVDD is supplied at a second voltage level VL2 lower than the first voltage level VL1. As a result, the first embodiment of the present invention can reduce power consumption.

7 is a flowchart illustrating a method of driving an organic light emitting display device according to a second exemplary embodiment of the present invention. Referring to FIG. 7, a method of driving an organic light emitting display device according to a second embodiment of the present invention includes steps S201 to S205 (S201 to S205).

Steps S201, S203, and S205 according to the second embodiment of the present invention are substantially the same as steps S101, S103, and S105 according to the first embodiment of the present invention described in conjunction with FIGS. 2 to 6. In addition, in step S202 according to the second embodiment of the present invention, except that the memory 42 outputs the digital video data DATA of the lower p bits to the data driver 30 during the analog driving period AP. It is substantially the same as step S102 according to the first embodiment of the present invention described in conjunction with FIGS. 2 to 6. In addition, in step S204 according to the second embodiment of the present invention, except that the memory 42 outputs the high-order q-bit digital video data DATA to the data driver 30 during the digital driving period DP. It is substantially the same as step S104 according to the first embodiment of the present invention described in conjunction with FIGS. 2 to 6. Accordingly, a detailed description of the method of driving the organic light emitting display device according to the second embodiment of the present invention will be omitted.

Consequently, the second embodiment of the present invention is driven by a hybrid driving method that combines an analog driving method and a digital driving method. In particular, in the second embodiment of the present invention, the pixel P is driven by the analog driving method during the analog driving period AP to represent the lower p bits, and the pixel P is digitally driven during the digital driving period DP. By driving by the method to represent the lower q bits, power consumption can be reduced.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 20: data driver
30: scan driving unit 40: timing control unit
41: main control unit 42: memory
43: look-up table 44: digital data conversion unit
50: power source C: capacitor
OLED: organic light emitting diode DT: driving transistor
ST: scanning transistor P: pixel

Claims (11)

A display panel including data lines, scan lines, and pixels connected to the data lines and the scan lines;
A scan driver supplying scan signals to the scan lines;
A data driver for supplying data voltages to the data lines in synchronization with the scan signals;
A power supply supplying power voltages to the pixels, the scan driver, and the data driver; And
A timing control unit is provided for dividing one frame period into an analog driving period and a digital driving period composed of a plurality of sub-field periods, and controlling the operation timing of the scan driving unit and the data driving unit and the power supply timing of the power supply source. and,
The scan driver supplies one scan signal to each scan line during the analog driving period, and supplies a plurality of scan signals to each scan line in correspondence with the plurality of sub-field periods during the digital driving period, and ,
The power supply source maintains a first power voltage supplied to the pixels during the analog driving period as a first level voltage, and applies the first power voltage to the first level voltage during the plurality of sub-field periods of the digital driving period. An organic light emitting display device, characterized in that maintaining the second level voltage lower than the level voltage. The method of claim 1,
The pixels represent digital video data of p (p is a positive integer) bits during the analog driving period, and digital video data of q (q is a positive integer) bits during the digital driving period. Organic light emitting display device. The method of claim 2,
The p-bit is an organic light emitting display device, characterized in that the higher bit than the q-bit. The method of claim 2,
The q-bit is a higher-order bit than the p-bit. The method of claim 2,
Pixels connected to the kth (k is a positive integer) scan line and the jth (j is a positive integer) data line,
A driving transistor whose drain-source current varies according to the voltage of the gate electrode;
A scan transistor turned on by a scan signal of the kth scan line to supply a data voltage of the jth data line to a gate electrode of the driving transistor; And
And an organic light emitting diode that emits light according to a current between a drain and a source of the driving transistor. The method of claim 5,
The data driver,
And supplying a data voltage obtained by converting the p-bit digital video data to the j-th data line in synchronization with the k-th scan signal during the analog driving period. The method of claim 5,
The data driver,
Second data for supplying a first data voltage for turning-on the driving transistor on or turning off the driving transistor to the j-th data line in synchronization with the k-th scan signal during each sub-field period of the digital driving period An organic light emitting display device comprising: supplying a voltage. A driving method of an organic light emitting display device having a display panel including data lines, scan lines, and pixels connected to the data lines and the scan lines,
Supplying scan signals to the scan lines;
Supplying data voltages to the data lines in synchronization with the scan signals; And
Supplying power voltages to the pixels, the scan driver, and the data driver,
The step of supplying scan signals to the scan lines,
One scan signal is supplied to each scan line during an analog drive period of one frame period, and each scan line corresponds to a plurality of sub-field periods constituting the digital drive period during a digital drive period of one frame period. Supplying a plurality of scanning signals to
The step of supplying power voltages to the pixels, the scan driver, and the data driver,
The first power voltage supplied to the pixels during the analog driving period is maintained at a first level voltage, and the first power voltage is lower than the first level voltage during the plurality of sub-field periods of the digital driving period. A method of driving an organic light emitting display device, characterized in that maintaining the second level voltage. The method of claim 8,
The pixels represent digital video data of p (p is a positive integer) bits during the analog driving period, and digital video data of q (q is a positive integer) bits during the digital driving period. A method of driving an organic light emitting display device. The method of claim 9,
The p-bit is a driving method of an organic light emitting display device, characterized in that the higher bit than the q-bit. The method of claim 9,
The q-bit is a driving method of an organic light emitting display device, characterized in that the higher bit than the p-bit.

Images