KR101848503B1 - Shift register and display device using the same - Google Patents

Abstract

The present invention relates to a shift register and a display device using the shift register. The shift register of the present invention includes a plurality of stages for receiving a start voltage, sequentially sequentially phase-delayed i (i is a natural number of 4 or more) phase clocks, and sequentially generating an output, wherein k N is a natural number satisfying 1? K? N, and n is the number of stages). The stage includes: a Q-node discharging unit for discharging a Q node to a gate-low voltage in response to a signal input through the first and second start terminals; A QB node charging unit responsive to a signal input through the first start terminal or charging a QB node to a gate high voltage higher than the gate low voltage in response to a gate low voltage of the Q node; A Q node charging unit charging the Q node with the gate high voltage in response to the gate low voltage of the QB node; A QB node discharging unit discharging the QB node to the gate-low voltage in response to a signal input through a reset terminal; The Q node discharging unit, and the Q node, and when the Q node is bootstrapped and falls to a voltage level lower than the gate low voltage, the Q node discharging unit, the Q node charging unit, And a Q-node voltage blocking unit for blocking connection between the Q-node; And an output unit for outputting a pulse synchronized with a clock inputted through the clock terminal according to the voltage of the Q node and the QB node.

Description

[0001] SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME [0002]

The present invention relates to a shift register and a display device using the shift register.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, a variety of flat panel displays (FPDs) have been developed and marketed to reduce weight and volume, which are disadvantages of cathode ray tubes. For example, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used.

The display device displays an image using a gate drive circuit for supplying a scan signal to the gate lines of the display panel and a data drive circuit for supplying a data voltage to the data lines. Recently, a gate driving circuit has been proposed in which a plurality of gate drive integrated circuits are mounted on a PCB (Printed Circuit Board) and a GIP (Gate Drive IC in Panel) method. In the case of forming the gate driver circuit by the GIP method, the organic light emitting diode display device can be made slimmer as compared with the case of forming the gate driver circuit by the existing TAB method, so that the external appearance can be increased, There is an advantage that a display panel maker can directly design a plurality of scan signals for compensating a threshold voltage of a driving transistor of a pixel of a panel.

A shift register of a gate driving circuit has stages including a plurality of thin film transistors (Thin Film Transistors). Stages are connected in a cascade to generate output sequentially. However, as a result of an experiment in which a pixel circuit is aged using a shift register of a gate driving circuit formed by a GIP method, an abrupt voltage change of a specific node controlling the output of the shift register (for example, A phenomenon that the potential difference between the gate electrode and the source or drain electrode of the thin film transistors connected to the specific node becomes large due to the bootstrapping. As a result, the gate insulator of the thin film transistors connected to the specific node can be destroyed. In this case, since the potential of the specific node controlling the output of the shift register is shaken, the output of the shift register is abnormally generated. The abnormal output of the shift register will appear as a bad lighting on the horizontal line of the display panel.

The present invention provides a shift register capable of preventing breakdown of a gate insulating film of a thin film transistor connected to a specific node for controlling an output, and a display device using the shift register.

The shift register of the present invention includes a plurality of stages for receiving a start voltage, sequentially sequentially phase-delayed i (i is a natural number of 4 or more) phase clocks, and sequentially generating an output, wherein k N is a natural number satisfying 1? K? N, and n is the number of stages). The stage includes: a Q-node discharging unit for discharging a Q node to a gate-low voltage in response to a signal input through the first and second start terminals; A QB node charging unit responsive to a signal input through the first start terminal or charging a QB node to a gate high voltage higher than the gate low voltage in response to a gate low voltage of the Q node; A Q node charging unit charging the Q node with the gate high voltage in response to the gate low voltage of the QB node; A QB node discharging unit discharging the QB node to the gate-low voltage in response to a signal input through a reset terminal; The Q node discharging unit, and the Q node, and when the Q node is bootstrapped and falls to a voltage level lower than the gate low voltage, the Q node discharging unit, the Q node charging unit, And a Q-node voltage blocking unit for blocking connection between the Q-node; And an output unit for outputting a pulse synchronized with a clock inputted through the clock terminal according to the voltage of the Q node and the QB node.

A display device of the present invention includes: a display panel including data lines and scan lines intersecting with the data lines; A data driving circuit for supplying a data voltage to the data lines; And a shift register for sequentially supplying a scan pulse to the scan lines in synchronization with the data voltage, wherein the shift register includes a start voltage, i (where i is 4 (K is a natural number satisfying 1? K? N, n is the number of stages) of the stages, A Q-node discharging unit discharging a Q-node to a gate-low voltage in response to a signal input through the first and second start terminals; A QB node charging unit responsive to a signal input through the first start terminal or charging a QB node to a gate high voltage higher than the gate low voltage in response to a gate low voltage of the Q node; A Q node charging unit charging the Q node with the gate high voltage in response to the gate low voltage of the QB node; A QB node discharging unit discharging the QB node to the gate-low voltage in response to a signal input through a reset terminal; The Q node discharging unit, and the Q node, and when the Q node is bootstrapped and falls to a voltage level lower than the gate low voltage, the Q node discharging unit, the Q node charging unit, And a Q-node voltage blocking unit for blocking connection between the Q-node; And an output unit for outputting a pulse synchronized with a clock inputted through the clock terminal according to the voltage of the Q node and the QB node.

The present invention further includes voltage blocking transistors for preventing breakdown of the gate insulating film of the thin film transistors connected to the Q node controlling the output of the shift register and supplies the gate low voltage to the gate electrode of the voltage blocking transistors. As a result, the present invention can prevent the breakdown of the gate insulating film of the thin film transistors connected to the Q node. As a result, the present invention can prevent abnormal output of the shift register, and thus it is possible to prevent defective horizontal line lighting of the display panel.

1 is a block diagram schematically showing the configuration of a shift register of a gate driving circuit according to a first embodiment of the present invention.
2 is a circuit diagram showing an example of the circuit configuration of the k-th stage of Fig.
Fig. 3 is a waveform diagram showing input and output signals of the k-th stage of Fig. 2;
4 is a block diagram schematically showing the configuration of a shift register of a gate driving circuit according to a second embodiment of the present invention.
5 is a circuit diagram showing an example of the circuit configuration of the k-th stage of Fig.
6A and 6B are waveform diagrams showing input and output signals of the k < th > stage of Fig. 5 in the forward or reverse mode.
Fig. 7 is a circuit diagram showing another example of the circuit configuration of the k-th stage of Fig. 4;
8 is a block diagram schematically showing a display device according to an embodiment of the present invention.
9 is a waveform diagram showing input and output signals of the level shifter of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The component name used in the following description may be selected in consideration of easiness of specification, and may be different from the actual product name.

1 is a block diagram schematically showing the configuration of a shift register of a gate driving circuit according to a first embodiment of the present invention. Referring to FIG. 1, the shift register according to the first embodiment of the present invention has a plurality of stages (ST (1) to ST (n), n being the number of stages as a natural number). In FIG. 1, only the first to third stages ST (1) to ST (3) are illustrated for convenience of explanation.

In the following description, the term "front stage" means that the stage is located above the reference stage. For example, the front stage is divided into a first stage ST (1) to a (k-1) th stage ST (k) on the basis of a stage k (1 <k <n, k, k is a natural number of 2 or more) (k-1)). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, with respect to the k-th stage ST (k), the trailing stage indicates either the (k + 1) th stage ST (k + 1) to the n-th stage ST (n).

The start voltage VST is applied to the start voltage line VSTL and the first clock CLK1 is applied to the first clock line CL1. The second clock CL2 is applied to the second clock line CL2, the third clock CLK3 is applied to the third clock line CL3, and the fourth clock CLK2 is applied to the fourth clock line CL4. CLK4 are applied.

Each of the stages ST (1) to ST (n) has first and second start terminals START1 and START2, a clock terminal CLK, a reset terminal RESET, and an output terminal OUT. The start voltage VST or the carry signal of the front stage is inputted to the first start terminal START1 of each of the stages ST (1) to ST (n). 1, the start voltage VST is applied to the first start terminal START1 of the first stage ST (1), and the start voltage VST is applied to the second to nth stages ST (2) to ST (1) n), the carry signal of the front stage is inputted to each first start terminal START1.

The i (i is a natural number of four or more) phase (s) delayed in phase sequentially to the second start terminal (START2), the clock terminal (CLK) and the reset terminal (RESET) of each of the stages (ST Any one of the clocks is input. In this case, the clock terminal CLK of each of the stages ST (1) to ST (n) is supplied with a clock whose phase is delayed from the clock input to the second start terminal START2, A clock whose phase is delayed from that input to the clock terminal CLK is input. A start voltage VST inputted to the first start terminal START1 or a pulse synchronized with the carry signal of the previous stage is inputted to the second start terminal START2 of each of the stages ST (1) to ST (n) Is input.

In order to secure a sufficient charge time at a high-speed operation of 120 Hz or more, the i-phase clocks are desirably implemented in four or more phases. For example, the four-phase clocks CLK1, CLK2, CLK3, and CLK4 have a pulse width of about one horizontal period (1H) as shown in FIG. 3, and the phases can be sequentially delayed by one horizontal period (1H) . The four-phase clocks CLK1, CLK2, CLK3, and CLK4 input to the shift register swing between the gate high voltage VGH and the gate low voltage VGL and a pulse is generated at the gate low voltage VGL.

Each of the stages ST (1) to ST (n) has one output terminal OUT. The outputs Out (1) to Oout (n) of the stages ST (1) to ST (n) are outputted to the scan lines of the display panel 10 and the outputs of the first start terminal START1) as a carry signal. The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) have a pulse width of approximately one horizontal period (1H) To the n-th stage ST (n). The outputs Out (1) to Out (n) of the stages ST (1) to ST (n) serve as a carry signal input to the first start terminal (START1) of the subsequent stage. The stages ST (1) to ST (n) are connected only when the start voltage VST is supplied to the first stage ST (1) n) sequentially generate outputs.

The gate high voltage VGH and the gate low voltage VGL are supplied to the stages ST (1) to ST (n), respectively. The gate low voltage VGL and the gate high voltage VGH are set in consideration of the threshold voltage of the thin film transistor of each of the stages ST (1) to ST (n). For example, the gate-low voltage VGL may be set to approximately -7V, and the gate-low voltage VGH may be set to approximately 30V. A detailed description of the circuit of each of the stages ST (1) to ST (n) will be given later with reference to FIG.

2 is a circuit diagram showing an example of the circuit configuration of the k-th stage of Fig. 2, the k-th stage ST (k) includes a Q-node discharging unit 21 for discharging a Q-node Q in response to a signal input through the first and second start terminals START, A Q node charging part 22 for charging the Q node Q according to the voltage of the QB node QB and a QB node discharging part 22 for discharging the QB node QB in response to a signal inputted through the reset terminal RESET A QB node charging unit 24 for charging the QB node QB in response to a signal inputted through the first start terminal START1 and a QB node charging unit 24 for preventing the destruction of the gate insulating film of the thin film transistor connected to the Q node Q And an output unit 26 for outputting a signal inputted through the clock terminal CLK according to the voltages of the Q-node voltage cut-off unit 25, Q and QB nodes Q and QB.

The Q-node discharging part 21 includes first and second transistors T1 and T2. The gate electrode of the first transistor T1 is connected to the first start terminal START1, the source electrode thereof is connected to the drain electrode of the second transistor T2, and the drain electrode thereof is connected to the gate electrode. That is, the first transistor T1 is diode-connected. The gate electrode of the second transistor T2 is connected to the second start terminal START2, the source electrode thereof is connected to the first node N1, and the drain electrode thereof is connected to the source electrode of the first transistor T1. The first transistor T1 is turned on in response to a signal input through the first start terminal START1 and the second transistor T2 is turned on in response to a signal input through the second start terminal START2, - on to discharge the first node N1 and the Q node Q to the gate low voltage VGL. The first node N1 is a contact point between the Q-node discharging part 21 and the Q-node voltage blocking part 25. [ More specifically, the first node N1 is a contact point between the source electrode of the second transistor T2 and the drain electrode of the eighth transistor T8.

The Q node charging section 22 includes third and fourth transistors T3 and T4. The gate electrode of the third transistor T3 is connected to the QB node QB, the source electrode thereof is connected to the drain electrode of the fourth transistor T4, and the drain electrode thereof is connected to the second node N2. The gate electrode of the fourth transistor T4 is connected to the QB node QB, the source electrode thereof is connected to the gate high voltage (VGH) terminal, and the drain electrode thereof is connected to the source electrode of the third transistor T3. The third and fourth transistors T3 and T4 are turned on in response to the QB node QB of the gate low voltage VGL to turn the second node N2 and the Q node Q to the gate high voltage VGH, . The second node N2 is a node between the Q node charging unit 22 and the Q node voltage blocking unit 25. [ More specifically, the second node N2 is a contact point between the drain electrode of the third transistor T3 and the source electrode of the ninth transistor T9.

The QB node discharging part 23 includes a fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the reset terminal RESET, the source electrode thereof is connected to the QB node QB, and the drain electrode thereof is connected to the gate low voltage (VGL) terminal. The fifth transistor T5 is turned on in response to a signal input through the reset terminal RESET to discharge the QB node QB to the gate low voltage VGL.

The QB node charging section 24 includes sixth and seventh transistors T6 and T7. The gate electrode of the sixth transistor T6 is connected to the first start terminal START1, the source electrode thereof is connected to the drain electrode of the seventh transistor T7, and the drain electrode thereof is connected to the QB node QB. The gate electrode of the seventh transistor T7 is connected to the first start terminal START1, the source electrode thereof is connected to the gate high voltage (VGH) terminal, and the drain electrode thereof is connected to the source electrode of the sixth transistor T6 . The sixth and seventh transistors T6 and T7 are turned on in response to a signal input through the first start terminal START1 to charge the QB node QB to the gate high voltage VGH.

The Q-node voltage cutoff unit 25 includes eighth and ninth transistors T8 and T9. The gate electrode of the eighth transistor T8 is connected to the gate low voltage (VGL) terminal, the source electrode thereof is connected to the Q node (Q), and the drain electrode thereof is connected to the first node N1. The gate electrode of the ninth transistor T9 is connected to the gate low voltage (VGL) terminal, the source electrode thereof is connected to the second node N2, and the drain electrode thereof is connected to the Q node (Q). The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL to connect the first node N1, the second node N2 and the Q node Q.

However, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate-low voltage VGL due to bootstrapping, the gate electrodes of the eighth and ninth transistors T8 and T9, And the voltage difference (Vgs) between the source electrode (or the drain electrode) becomes higher than the threshold voltage. As a result, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate-low voltage VGL due to bootstrapping, the eighth and ninth transistors T8 and T9 turn- The connection between the Q node Q and the first node N1 and the connection between the Q node Q and the second node N2 are blocked. Because of this, the potentials of the first node N1 and the second node N2 do not drop to the voltage level VGL 'which is lower than the gate-low voltage VGL, so that the potentials of the second and third transistors T2 and T3 The breakdown of the gate insulating film can be prevented.

If the eighth and ninth transistors T8 and T9 are not provided, the gate high voltage VGH is supplied to the gate electrode of the second and third transistors T2 and T3, the gate low voltage VGL is applied to the source electrode thereof, The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the second and third transistors T2 and T3 becomes greater than 50 V because the voltage level VGL 'is lower than the voltage level VGL'. In this case, the gate insulating film for insulating between the gate electrode and the source electrode (or the drain electrode) may be broken. However, since the eighth and ninth transistors T8 and T9 cut off the connection between the Q node Q and the second and third transistors T2 and T3, the breakdown of the gate insulating film can be prevented. Since only the gate low voltage VGL is applied to the gate electrodes of the eighth and ninth transistors T8 and T9, the voltage between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 The difference (Vgs) is maintained at about 25V. That is, the voltage difference (Vgs) between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 is not so large that the gate insulating film is destroyed.

The output 26 includes a pull-up transistor TU and a pull-down transistor TD. The gate electrode of the pull-up transistor TU is connected to the Q node Q, the source electrode thereof is connected to the clock terminal CLK, and the drain electrode thereof is connected to the output terminal OUT. The pull-up transistor TU is turned on according to the voltage of the Q node Q and outputs a clock input through the clock terminal CLK to the output terminal OUT. The gate electrode of the pull-down transistor TD is connected to the QB node QB, the source electrode thereof is connected to the gate high voltage (VGH) terminal, and the drain electrode thereof is connected to the output terminal OUT. The pull-down transistor TD is turned on according to the voltage of the QB node QB to output the gate high voltage VGH to the output terminal OUT.

The first capacitor C1 is connected to the Q node Q and the gate high voltage VGH terminal, and serves to keep the voltage of the Q node Q constant. The second capacitor C2 is connected to the QB node QB and the gate high voltage (VGH) terminal, and serves to keep the voltage of the QB node QB constant. The third capacitor C3 is connected to the Q node Q and the output terminal OUT and serves to maintain a constant voltage of a signal output through the output terminal OUT. However, when the clock input through the clock terminal CLK is output, the third capacitor C3 further lowers the voltage of the Q node Q by bootstrapping.

The first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, the pull-up transistor TU and the pull- ). The semiconductor layers of the first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9, the pull-up transistor TU and the pull- , Poly-Si, or an oxide semiconductor. The first through ninth transistors T1, T2, T3, T4, T5, T6, T7, T8 and T9 and the pull-up transistor TU and the pull- FET. However, the present invention is not limited to this, and it may be implemented as an N-type MOS-FET.

Fig. 3 is a waveform diagram showing input and output signals of the k-th stage of Fig. 2; 3, the start voltage VST input to the k-th stage ST (k) or the output signal OUT (k-1) of the k-1 stage ST (k- ) And four-phase clocks CLK1, CLK2, CLK3 and CLK4 are shown, and a k-th output signal OUT (k) output from the k-th stage ST (k) is shown. The voltage VQ of the Q node Q of the k-th stage ST (k) and the voltage VQB of the QB node QB are shown.

The start voltage VST may occur once at the beginning of one frame period. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated so that the phases are sequentially delayed by one horizontal period (1H). The output signal OUT (k-1) of the k-1 stage ST (k-1) and the four-phase clocks CLK1, CLK2, CLK3 and CLK4, which are the start voltage VST or the front carry signal, A pulse is generated at the low voltage VGL, and the pulse occurs at a pulse width of approximately one horizontal period (1H). One horizontal period (1H) denotes a one-line scanning time at which data is written to pixels of one line of the display panel. The kth output signal OUT (k) is pulsed at the gate low voltage (VGL), and the pulse occurs at a pulse width of approximately one horizontal period (1H).

Hereinafter, the operation of the k-th stage ST (k) during the period from t1 to t4 will be described in detail with reference to Fig. 2 and Fig. The output signal OUT (k-1) of the k-1 stage ST (k-1) which is the previous carry signal or the start voltage VST is applied to the first start terminal START1 of the kth stage ST (k) The first clock CLK is input to the clock terminal CLK and the third clock CLK is input to the reset terminal RESET. (CLK3) is inputted.

During the period t1, the first start terminal START1 receives the start voltage VST of the gate low voltage VGL or the output signal OUT (k-1) of the k-1 stage ST (k- 1), and the fourth clock CLK4 of the gate low voltage VGL is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK and the third clock CLK3 of the gate high voltage VGL is input to the reset terminal RESET.

The first transistor T1 is responsive to the start voltage VST of the gate low voltage VGL or the output signal OUT (k-1) of the k-1 stage ST (k-1) And turned on. The second transistor T2 is turned on in response to the fourth clock CLK4 of the gate low voltage VGL. The sixth and seventh transistors T6 and T7 are connected to the start voltage VST of the gate low voltage VGL or the output signal OUT (k-1) of the k-1 stage ST (k- 1) &lt; / RTI &gt; In addition, the eighth and ninth transistors T8 and T9 are turned on in response to the gate-low voltage VGL. The third, fourth and fifth transistors T3, T4 and T5 are turned off by the gate high voltage VGH.

The first node N1, the second node N2, and the Q node Q are turned on due to the turn-on of the first, second, eighth, and ninth transistors T1, T2, T8, And is discharged to the gate low voltage VGL. The pull-up transistor TU is turned on in response to the gate low voltage VGL of the Q node Q to output the first clock CLK1 of the gate high voltage VGH to the output terminal OUT. Due to the turn-on of the sixth and seventh transistors T6 and T7, the QB node QB is charged to the gate high voltage VGH. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

During the period t2, the first start terminal START1 receives the start voltage VST of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST (k- 1), and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate-low voltage VGL is input to the clock terminal CLK. And the third clock CLK3 of the gate high voltage VGH is input to the reset terminal RESET.

The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are turned off by the gate high voltage VGH. The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL. The pull-up transistor TU maintains the turn-on state in response to the gate low voltage VGL of the Q node Q so that the first clock CLK1 of the gate low voltage VGL is supplied to the output terminal OUT, . At this time, the Q node Q is bootstrapped by the third capacitor C3 and falls to a voltage level VGL 'that is lower than the gate-low voltage VGL. The QB node QB maintains the gate high voltage VGH by the second capacitor C2. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

On the other hand, since the Q node Q is lowered to the voltage level VGL 'lower than the gate-low voltage VGL due to the bootrapping, the gate electrodes of the eighth and ninth transistors T8 and T9, (Or the drain electrode) becomes higher than the threshold voltage. Therefore, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate-low voltage VGL due to bootstrapping, the eighth and ninth transistors T8 and T9 turn- The connection between the Q node Q and the first node N1 and the connection between the Q node Q and the second node N2 are blocked. Because of this, the potentials of the first node N1 and the second node N2 do not drop to the voltage level VGL 'which is lower than the gate-low voltage VGL, so that the potentials of the second and third transistors T2 and T3 The breakdown of the gate insulating film can be prevented.

If the eighth and ninth transistors T8 and T9 are not provided, the gate high voltage VGH is supplied to the gate electrode of the second and third transistors T2 and T3, the gate low voltage VGL is applied to the source electrode thereof, The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the second and third transistors T2 and T3 becomes greater than 50 V because the voltage level VGL 'is lower than the voltage level VGL'. In this case, the gate insulating film for insulating between the gate electrode and the source electrode (or the drain electrode) may be broken. However, since the eighth and ninth transistors T8 and T9 cut off the connection between the Q node Q and the second and third transistors T2 and T3, the breakdown of the gate insulating film can be prevented. Since only the gate low voltage VGL is applied to the gate electrodes of the eighth and ninth transistors T8 and T9, the voltage between the gate and source electrodes (or drain electrodes) of the eighth and ninth transistors T8 and T9 The difference (Vgs) is maintained at about 25V. That is, the voltage difference (Vgs) between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 is not so large that the gate insulating film is destroyed.

During the period t3, the first start terminal START1 receives the start voltage VST of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST (k- 1), and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK. And the third clock CLK3 of the gate high voltage VGH is input to the reset terminal RESET.

The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are turned off by the gate high voltage VGH. The pull-up transistor TU maintains the turn-on state in response to the gate low voltage VGL of the Q node Q so that the first clock CLK1 of the gate high voltage VGH is supplied to the output terminal OUT, . The Q node Q rises to the gate low voltage VGL since the gate high voltage VGH is reflected by the third capacitor C3. The QB node QB maintains the gate high voltage VGH by the second capacitor C2. The pull-down transistor TD is turned off by the gate high voltage VGH of the QB node QB.

The eighth and ninth transistors T8 and T9 are turned on in response to the gate low voltage VGL. The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 becomes lower than the threshold voltage because the Q node Q rises to the gate-low voltage VGL .

During the period t4, the first start terminal START1 receives the start voltage VST of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST (k- 1), and the fourth clock CLK4 of the gate high voltage VGH is input to the second start terminal START2. The first clock CLK1 of the gate high voltage VGH is input to the clock terminal CLK. The third clock CLK3 of the gate low voltage VGL is input to the reset terminal RESET.

The fifth transistor T5 is turned on in response to the third clock CLK3 of the gate low voltage VGL so that the QB node QB is discharged to the gate low voltage VGL. The third and fourth transistors T3 and T4 are turned on in response to the gate low voltage VGL of the QB node QB so that the Q node Q is charged to the gate high voltage VGH. As a result, the pull-up transistor TU is turned off by the gate high voltage VGH of the Q node Q. The pull-down transistor TD is turned on by the gate low voltage VGL of the QB node QB, and thus outputs the gate high voltage VGH to the output terminal OUT.

4 is a block diagram schematically showing the configuration of a shift register of a gate driving circuit according to a second embodiment of the present invention. Referring to FIG. 4, the shift register according to the second embodiment of the present invention has a plurality of stages ST (1) to ST (n) connected in a dependent manner, and n is the number of stages in natural numbers. 1, only the first to third stages ST (1) to ST (3) and the n-1 and nth stages ST (n-1) and ST (n) are illustrated.

In the following description, the term "front stage" means that the stage is located above the reference stage. For example, the front stage is divided into a first stage ST (1) to a (k-1) th stage ST (k) on the basis of a stage k (1 <k <n, k, k is a natural number of 2 or more) (k-1)). Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, with respect to the k-th stage ST (k), the trailing stage indicates either the (k + 1) th stage ST (k + 1) to the n-th stage ST (n).

The shift register according to the second embodiment of the present invention may be implemented in a forward mode or a reverse mode. In the forward mode, the stages ST (1) to ST (n) sequentially generate outputs from the first stage ST (1) to the nth stage ST (n). In the reverse mode, the stages ST (1) to ST (n) sequentially generate outputs from the n-th stage ST (n) to the first stage ST (1).

The start voltage VST is applied to the start voltage line VSTL and the start reverse voltage VST_R is applied to the start voltage line VST_RL. The first clock CL1 is applied to the first clock line CL1 and the second clock CLK is applied to the second clock line CL2 and the third clock CL2 is applied to the third clock line CL3. And a fourth clock CLK4 is applied to the fourth clock line CL4.

Each of the stages ST (1) to ST (n) includes first and second start terminals START1 and START2, first and second start reverse terminals START_R1 and START_R2, a clock terminal CLK, (RESET), and an output terminal (OUT). The start voltage VST or the carry signal of the front stage is inputted to the first start terminal START1 of each of the stages ST (1) to ST (n). For example, the start voltage VST is applied to the first start terminal START1 of the first stage ST (1) and the second to nth stages ST (2) to ST n), the carry signal of the front stage is inputted to each first start terminal START1. The start reverse voltage VST_R or the carry signal of the subsequent stage is inputted to the first start reverse terminal START_R1 of each of the stages ST (1) to ST (n). For example, as shown in Fig. 4, the start reverse voltage VST_R is applied to the first start reverse terminal START_R1 of the n-th stage ST (n), and the second to n-th stages ST (2) ST (n)), the carry signal of the subsequent stage is inputted to the first start reverse terminal (START_R1).

The phases of the first and second start terminals START2 and START_R2 and the clock terminal CLK and the reset terminal RESET of the stages ST (1) to ST (n) One of the i-phase clocks is input. In the forward mode, the clock terminal CLK of each of the stages ST (1) to ST (n) is inputted with a clock whose phase is delayed from the clock input to the second start terminal START2, A clock whose phase is delayed from that input to the clock terminal CLK is input. A start voltage VST inputted to the first start terminal START1 or a pulse synchronized with the carry signal of the previous stage is inputted to the second start terminal START2 of each of the stages ST (1) to ST (n) Is input. In the reverse mode, the clock terminal CLK of each of the stages ST (1) to ST (n) receives a clock whose phase is delayed from the clock input to the second start reverse terminal (START_R2), and the reset terminal RESET A clock whose phase is delayed from the clock input to the clock terminal CLK is input. The start reverse voltage VSTR input to the first start reverse terminal (START_R1) or the carry signal of the next stage and the carry signal of the next stage are supplied to the second start reverse terminal (START_R2) of each of the stages ST (1) A clock having a synchronized pulse is input.

In order to secure a sufficient charge time at a high-speed operation of 120 Hz or more, the i-phase clocks are desirably implemented in four or more phases. For example, the four-phase clocks CLK1, CLK2, CLK3, and CLK4 have a pulse width of about one horizontal period (1H) as shown in FIG. 3, and the phases can be sequentially delayed by one horizontal period (1H) . The four-phase clocks CLK1, CLK2, CLK3, and CLK4 input to the shift register swing between the gate high voltage VGH and the gate low voltage VGL and a pulse is generated at the gate low voltage VGL.

Each of the stages ST (1) to ST (n) has one output terminal OUT. In the forward mode, the outputs Out (1) to Oout (n) of the stages ST (1) to ST (n) are output to the scan lines of the display panel 10, 1 Start terminal (START1) as a carry signal. The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) have a pulse width of approximately one horizontal period (1H) To the n-th stage ST (n). The outputs Out (1) to Out (n) of the stages ST (1) to ST (n) serve as a carry signal input to the first start terminal (START1) of the subsequent stage. The stages ST (1) to ST (n) are connected only when the start voltage VST is supplied to the first stage ST (1) n) sequentially generate outputs.

In the reverse mode, the outputs Out (1) to Oout (n) of the stages ST (1) to ST (n) are outputted to the scan lines of the display panel 10, 1 start reverse terminal (START_R1). The outputs Out (1) to Out (n) of each of the stages ST (1) to ST (n) have a pulse width of approximately one horizontal period (1H) To the first stage ST (1). The outputs Out (1) to Out (n) of the stages ST (1) to ST (n) serve as a carry signal input to the first start reverse terminal (START_R1) of the previous stage. Since the stages ST (1) to ST (n) are connected in a dependent manner, only when the start reverse voltage VSTR is supplied to the n-th stage ST (n) (n) sequentially generate outputs.

The gate high voltage VGH and the gate low voltage VGL are supplied to the stages ST (1) to ST (n), respectively. The gate low voltage VGL and the gate high voltage VGH are set in consideration of the threshold voltage of the thin film transistor of each of the stages ST (1) to ST (n). For example, the gate-low voltage VGL may be set to approximately -7V, and the gate-low voltage VGH may be set to approximately 30V. A detailed description of the circuit of each of the stages ST (1) to ST (n) will be given later in conjunction with FIG. 5 and FIG.

5 is a circuit diagram showing an example of the circuit configuration of the k-th stage of Fig. 5, the k-th stage ST (k) includes a forward Q-node discharging unit (not shown) for discharging the Q-node Q in response to a signal input through the first and second start terminals START1 and START2 A Q-node charging unit 22 for charging the Q-node Q according to the voltage of the QB node QB, a Q-node charging unit 22 for discharging the QB node QB in response to a signal input through the reset terminal RESET, A QB node charging unit 24 for charging the QB node QB in accordance with the voltage of the Q node Q and a Q node charging unit 24 for preventing the breakdown of the gate insulating film of the thin film transistor connected to the Q node Q, An output unit 26 for outputting a signal inputted through the clock terminal CLK in accordance with the voltage of the Q and QB nodes Q and QB, the first and second start reverse terminals START_R1 and START_R2 And a reverse Q-node discharging part 27 for discharging the Q-node Q in response to a signal inputted through the reverse Q-node discharging part 27. [

The Q node charging unit 22, the QB node discharging unit 23, the QB node charging unit 24, and the output unit 26 shown in FIG. 5 are substantially the same as those described in FIG. The forward Q-node discharging portion 21 shown in FIG. 5 is substantially the same as that described in the Q-node discharging portion 21 in FIG. The QB node charging unit 24 shown in FIG. 5 charges the QB node QB according to the voltage of the Q node Q. On the other hand, the QB node charging unit 24 shown in FIG. And charges the QB node QB in response to a signal input via the first inverter START1. That is, the gate electrodes of the sixth and seventh transistors T6 and T7 shown in FIG. 5 are connected to the third node N3 instead of the first start terminal START. The third node N3 is a contact point between the QB node charging unit 24 and the Q node voltage blocking unit 25. [ More specifically, the third node N3 is a contact point between the gate electrode of the sixth and seventh transistors T6 and T7 and the source electrode of the tenth transistor T10.

The Q-node voltage blocking unit 25 includes eighth to tenth transistors T8, T9, and T10. The eighth and ninth transistors T8 and T9 are substantially the same as those described in Fig. The gate electrode of the tenth transistor T10 is connected to the gate low voltage (VGL) terminal, the source electrode thereof is connected to the third node N3, and the drain electrode thereof is connected to the Q node (Q). The tenth transistor T10 is turned on in response to the gate low voltage VGL to connect the third node N3 and the Q node Q.

However, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping, the gate electrode of the tenth transistor T10 and the source electrode Drain electrode) becomes higher than the threshold voltage. As a result, the eighth and ninth transistors T8 and T9 are turned off. That is, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate-low voltage VGL due to bootstrapping, the tenth transistor T10 is turned off, The connection between the node Q and the third node N3 is interrupted. This makes it possible to prevent breakdown of the gate insulating film of the sixth and seventh transistors T6 and T7 connected to the Q node Q. [

If the tenth transistor T10 is not present, the gate high voltage VGH is supplied to the gate electrodes of the sixth and seventh transistors T6 and T7 and the voltage level of the source voltage is lower than the gate low voltage VGL The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the sixth and seventh transistors T6 and T7 becomes larger than 50V. In this case, the gate insulating film for insulating between the gate electrode and the source electrode (or the drain electrode) may be broken. However, since the tenth transistor T10 blocks the connection between the Q node Q and the sixth and seventh transistors T6 and T7, the breakdown of the gate insulating film can be prevented. On the other hand, since only the gate low voltage VGL is applied to the gate electrode of the tenth transistor T10, the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the tenth transistor T10 is maintained at about 25V . That is, the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the tenth transistor T10 is not large enough to cause the gate insulating film to break.

The reverse Q-node discharging portion 27 includes the eleventh and twelfth transistors T11 and T12. The gate electrode of the eleventh transistor T11 is connected to the first start reverse terminal START_R1, the source electrode thereof is connected to the drain electrode of the twelfth transistor T12, and the drain electrode thereof is connected to the gate electrode. That is, the eleventh transistor T11 is diode-connected. The gate electrode of the twelfth transistor T12 is connected to the second start-reverse terminal START_R2, the source electrode thereof is connected to the first node N1, and the drain electrode thereof is connected to the source electrode of the eleventh transistor T11 . The eleventh transistor T11 is turned on in response to a signal input through the first start reverse terminal START_R1 and the twelfth transistor T12 is turned on in response to a signal input through the second start reverse terminal START_R2 And discharges the first node N1 and the Q node Q to the gate low voltage VGL.

The pull-up transistor TU and the pull-down transistor TD are connected to the first to the twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, And may be formed of a thin film transistor (Thin Film Transistor). The first through twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and T12, the pull-up transistor TU, The semiconductor layer may be formed of any one of a-Si, Poly-Si, and an oxide semiconductor. The first through twelfth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11 and T12, the pull- ) Is implemented as a P-type MOS-FET. However, the present invention is not limited to this, and it may be implemented as an N-type MOS-FET.

6A and 6B are waveform diagrams showing input and output signals of the k &lt; th &gt; stage of Fig. 5 in the forward or reverse mode. 6A and 6B, the start voltage VST input to the k-th stage ST (k) or the output signal OUT (k-1) of the k-1 stage ST (k- 1) of the (k + 1) -th stage ST (k + 1), which is the start-reverse voltage VST_R input to the k-th stage ST (k) 1) and four-phase clocks CLK1, CLK2, CLK3 and CLK4 are shown, and the output signal OUT (k) output from the k-th stage ST (k) is shown. The voltage VQ of the Q node Q of the k-th stage ST (k) and the voltage VQB of the QB node QB are shown.

As shown in FIG. 6A, in the forward mode, the start voltage VST may occur once at the beginning of one frame period. In the forward mode, the start reverse voltage VST_R occurs at the gate high voltage VGH. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated so that the phases are sequentially delayed by one horizontal period (1H) in the forward direction. The output signal OUT (k-1) of the k-1 stage ST (k-1) and the four-phase clocks CLK1, CLK2, CLK3 and CLK4, which are the start voltage VST or the front carry signal, A pulse is generated at the low voltage VGL, and the pulse occurs at a pulse width of approximately one horizontal period (1H). One horizontal period (1H) denotes a one-line scanning time at which data is written to pixels of one line of the display panel. The kth output signal OUT (k) is pulsed at the gate low voltage (VGL), and the pulse occurs at a pulse width of approximately one horizontal period (1H). In the forward mode, the k th to (k + 3) th output signals OUT (k) to OUT (k + 3) are sequentially generated in the forward direction.

Hereinafter, the operation of the k-th stage ST (k) during the period from t1 to t4 in the forward mode will be described in detail with reference to Figs. 5 and 6A. The output signal OUT (k-1) of the k-1 stage ST (k-1) which is the previous carry signal or the start voltage VST is applied to the first start terminal START1 of the kth stage ST (k) 1), the fourth clock CLK4 is input to the second start terminal START2, the start reverse voltage VST_R is applied to the first start reverse terminal START_R1, or the (k + 1) th The second clock CLK2 is input to the second start-reverse terminal START_R2 and the output signal OUT (k + 1) of the stage ST (k + 1) The first clock CLK is input and the third clock CLK3 is input to the reset terminal RESET.

On the other hand, when the operation of the k-th stage ST (k) in the forward mode is substantially the same as the operation of the k-th stage ST (k) described with reference to Figs. 2 and 3, . That is, the sixth, seventh, tenth, eleventh, and twelfth transistors T6, T7, T10, T11, and T12 will be described below.

During the period t1, the first start reverse terminal (START_R1) is supplied with the start reverse voltage VST_R of the gate high voltage VGH or the output signal OUT (k-1) of the k- and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The tenth transistor T10 is turned on in response to the gate low voltage VGL. The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. Due to the turn-on of the tenth transistor T10, the third node N3 is discharged to the gate low voltage VGL. The sixth and seventh transistors T6 and T7 are turned on in response to the gate low voltage VGL of the third node N3 to charge the QB node QB to the gate high voltage VGH.

In addition, the description during the period t1 in Fig. 5 is substantially the same as that described during the period t1 in Fig.

During the period t2, the first start reverse terminal (START_R1) is supplied with the start reverse voltage VST_R of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. The gate electrode of the tenth transistor T10 and the source electrode (or the drain electrode) of the tenth transistor T10 are connected to the gate electrode of the tenth transistor T10, because the Q node Q drops to a voltage level VGL 'lower than the gate low voltage VGL due to bootstrapping. The voltage difference Vgs between the source and drain becomes higher than the threshold voltage. Thus, the tenth transistor T10 is turned off. That is, when the voltage of the Q node Q falls to a voltage level VGL 'lower than the gate-low voltage VGL due to bootstrapping, the tenth transistor T10 is turned off, The connection between the node Q and the third node N3 is interrupted. This prevents the potential of the third node N3 from dropping to the voltage level VGL 'that is lower than the gate-low voltage VGL so that the gate insulating film breakdown of the sixth and seventh transistors T6 and T7 can be prevented have.

A gate high voltage VGH is supplied to the gate electrodes of the sixth and seventh transistors T6 and T7 and a voltage level VGL lower than the gate low voltage VGL is applied to the source electrode of the sixth and seventh transistors T6 and T7, The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the sixth and seventh transistors T6 and T7 becomes greater than 50V. In this case, the gate insulating film for insulating between the gate electrode and the source electrode (or the drain electrode) may be broken. However, since the tenth transistor T10 blocks the connection between the Q node Q and the sixth and seventh transistors T6 and T7, the breakdown of the gate insulating film can be prevented. On the other hand, since only the gate low voltage VGL is applied to the gate electrode of the tenth transistor T10, the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the tenth transistor T10 is maintained at about 25V . That is, the voltage difference Vgs between the gate-source electrode (or the drain electrode) of the tenth transistor T10 is not large enough to cause the gate insulating film to break.

In addition, the description during the period t2 in Fig. 5 is substantially the same as that described during the period t2 in Fig.

During the period t3, the first start reverse terminal (START_R1) is supplied with the start reverse voltage VST_R of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST and the second clock CLK2 of the gate-low voltage VGL is input to the second start-reverse terminal START_R2.

The eleventh transistor T12 is turned off by the gate high voltage VGH while the twelfth transistor T12 is turned on by the second clock CLK2 of the gate high voltage VGH. The turn-on of the twelfth transistor T12 does not affect the driving of the k-th stage ST (k). The tenth transistor T10 is turned on in response to the gate low voltage VGL. The voltage difference Vgs between the gate-source electrode (or the drain electrode) of the eighth and ninth transistors T8 and T9 becomes lower than the threshold voltage because the Q node Q rises to the gate-low voltage VGL .

In addition, the description during the period t3 in Fig. 5 is substantially the same as that described during the period t3 in Fig.

During the period t4, the first start reverse terminal (START_R1) is supplied with the start reverse voltage VST_R of the gate high voltage VGH or the output signal OUT (k-1) of the k-1 stage ST and the second clock CLK2 of the gate high voltage VGH is input to the second start reverse terminal START_R2.

The eleventh and twelfth transistors T11 and T12 are turned off by the gate high voltage VGH. The tenth transistor T10 is turned on in response to the gate low voltage VGL.

In addition, the description for the period t4 in Fig. 5 is substantially the same as that described during the period t4 in Fig.

As shown in FIG. 6B, in the backward mode, the start reverse voltage VST_R may occur once at the start of one frame period. In the reverse mode, the start voltage VST occurs at the gate high voltage VGH. The four-phase clocks CLK1, CLK2, CLK3, and CLK4 are generated so that the phases are sequentially delayed by one horizontal period (1H) in the reverse direction. The output signal OUT (k-1) of the k-1 stage ST (k-1) and the four-phase clocks CLK1, CLK2, CLK3 and CLK4, which are the start voltage VST or the front carry signal, A pulse is generated at the low voltage VGL, and the pulse occurs at a pulse width of approximately one horizontal period (1H). One horizontal period (1H) denotes a one-line scanning time at which data is written to pixels of one line of the display panel. The kth output signal OUT (k) is pulsed at the gate low voltage (VGL), and the pulse occurs at a pulse width of approximately one horizontal period (1H). In the backward mode, the k th to (k + 3) th output signals OUT (k) to OUT (k + 3) are sequentially generated in the reverse direction.

Hereinafter, the operation of the k-th stage ST (k) during the period from t1 to t4 in the reverse mode will be described in detail with reference to Figs. 5 and 6B. The output signal OUT (k-1) of the k-1 stage ST (k-1) which is the previous carry signal or the start voltage VST is applied to the first start terminal START1 of the kth stage ST (k) 1), the third clock CLK3 is input to the second start terminal START2, the start reverse voltage VST_R is supplied to the first start reverse terminal START_R1, or the (k + 1) th The first clock CLK1 is input to the second start-reverse terminal START_R2 and the output signal OUT (k + 1) of the stage ST (k + 1) 4 clock CLK4 is input and the second clock CLK2 is input to the reset terminal RESET.

On the other hand, the operation of the k-th stage ST (k) in the reverse mode is performed by the first start terminal START1, the second start terminal START2, the first start reverse terminal START_R1, the second start reverse terminal START_R2, The clock terminal CLK and the reset terminal RESET are substantially the same as the operation of the k-th stage ST (k) in the forward mode described with reference to Figs. 5 and 6A. Therefore, detailed description of the operation of the k-th stage ST (k) in the reverse mode will be omitted. However, the first and second transistors T1 and T2 connected to the first and second start terminals START1 and START2 in the reverse mode are connected to the first and second start reverse terminals START_R1 and START_R2 in the forward mode And operates substantially the same as the eleventh and twelfth transistors T11 and T12. The eleventh and twelfth transistors T11 and T12 connected to the first and second start reverse terminals START_R1 and START_R2 in the backward mode are connected to the first and second start terminals START1 and START2 in forward mode And operates substantially the same as the first and second transistors T1 and T2.

Fig. 7 is a circuit diagram showing another example of the circuit configuration of the k-th stage of Fig. 4; 7, the k-th stage ST (k) includes a forward Q-node discharging unit (discharging unit) Q for discharging the Q-node Q in response to a signal input through the first and second start terminals START1 and START2 A Q-node charging unit 22 for charging the Q-node Q according to the voltage of the QB node QB, a Q-node charging unit 22 for discharging the QB node QB in response to a signal input through the reset terminal RESET, The QB node QB is charged according to the voltage of the Q node Q in response to a signal inputted through the discharger 23, the first start terminal START1 and the first start reverse terminal START_R1 A Q-node voltage charging unit 25 for preventing a breakdown of a gate insulating film of a thin film transistor connected to the Q-node Q, a Q- An output unit 26 for outputting a signal input via the first clock terminal CLK, and a control unit 26 in response to a signal input through the first and second start reverse terminals START_R1 and START_R2 And a reverse Q-node discharging part 27 for discharging the Q-node Q.

The Q node charging unit 22, the QB node discharging unit 23, and the output unit 26 shown in Fig. 7 are substantially the same as those described in Fig. The forward Q-node discharging portion 21, the Q-node voltage blocking portion 25, and the reverse Q-node discharging portion 27 shown in Fig. 7 are substantially the same as those described in Fig. The drain electrode of the first transistor T1 of the forward Q-node discharging unit 21 shown in FIG. 7 is connected to the gate low voltage (VGL) terminal and the drain of the eleventh transistor T11 are connected to the gate low voltage (VGL) terminal.

The sixth and seventh transistors T6 and T7 of the QB node charging section 24 shown in Fig. 7 are substantially the same as those described in Fig. The QB node charging unit 24 shown in FIG. 7 further includes thirteenth and fourteenth transistors T13 and T14. The gate electrode of the thirteenth transistor T13 is connected to the first start terminal START1, the source electrode thereof is connected to the gate high voltage (VGH) terminal, and the drain electrode thereof is connected to the QB node (QB). The gate electrode of the fourteenth transistor T14 is connected to the first start reverse terminal (START_R1), the source electrode thereof is connected to the gate high voltage (VGH) terminal, and the drain electrode is connected to the QB node (QB). The thirteenth transistor T13 is turned on in response to a signal input through the first start terminal START1 to charge the QB node QB to the gate high voltage VGH. The fourteenth transistor T14 is turned on in response to a signal input through the first start reverse terminal START_R1 to charge the QB node QB to the gate high voltage VGH.

The first capacitor C1 shown in FIG. 7 is connected to the Q node Q and the output terminal OUT and serves to maintain a constant voltage of a signal output through the output terminal OUT. However, when the clock input through the clock terminal CLK is output, the third capacitor C3 further lowers the voltage of the Q node Q by bootstrapping. 7 shows a capacitor connected to the Q node Q and the gate high voltage VGH terminal to keep the voltage of the Q node Q constant and a capacitor QB connected to the QB node QB and the gate high voltage VGH terminal The capacitor connected to keep the voltage of the QB node QB constant is deleted. The present invention deletes the capacitors since the 13th and 14th transistors T13 and T14 can be added to the QB node charging unit 24 to ensure control of the QB node QB.

The first to fourteenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and T14, the pull- (TD) may be formed of a thin film transistor (Thin Film Transistor). The first to fourteenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and T14, the pull- (TD) may be formed of any one of a-Si, Poly-Si, and an oxide semiconductor. In addition, the first to fourteenth transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, the pull- Although the down transistor TD is implemented as a P-type MOS-FET, the present invention is not limited to this, and it may be implemented as an N-type MOS-FET.

On the other hand, the input and output signals of the k-th stage ST (k) in Fig. 7 are substantially the same as the waveforms shown in Figs. 6A and 6B. First, the operation of the k-th stage ST (k) during the period from t1 to t4 in the forward mode will be described in detail with reference to Fig. 6A and Fig. On the other hand, when the operation of the k-th stage ST (k) in the forward mode is substantially the same as the operation of the k-th stage ST (k) described with reference to Figs. 5 and 6A, . That is, in the following, the thirteenth and fourteenth transistors T13 and T14 will be mainly described.

During the period t1, the thirteenth transistor T13 receives the start voltage VST of the gate low voltage VGL or the carry signal OUT (k-1) of the k-1 stage ST (k-1) ) To charge QB node QB to gate high voltage VGH. The fourteenth transistor T14 is connected to the start reverse voltage VST_R of the gate high voltage VGH or the carry signal OUT (k + 1) of the (k + 1) th stage ST (k + Lt; / RTI &gt;

In addition, the description during the period t1 in Fig. 7 is substantially the same as that described during the period t1 in Fig.

During the period from t2 to t4, the thirteenth transistor T13 receives the start voltage VST of the gate high voltage VGH or the carry signal OUT (k (k)) of the k-1 stage ST -1). The fourteenth transistor T14 is turned off by the start reverse voltage VST_R of the gate high voltage VGH or the (k + 1) th stage ST (k + 1) And is turned off by the carry signal OUT (k + 1).

In addition, the description during the period from t2 to t4 in Fig. 7 is substantially the same as that described during the period from t2 to t4 in Fig.

Hereinafter, the operation of the k-th stage ST (k) during the period from t1 to t4 in the backward mode will be described in detail with reference to Figs. 7 and 6B. On the other hand, the operation of the k-th stage ST (k) in the reverse mode is performed by the first start terminal START1, the second start terminal START2, the first start reverse terminal START_R1, the second start reverse terminal START_R2, The clock terminal CLK and the reset terminal RESET are substantially the same as the operation of the k-th stage ST (k) in the forward mode described in conjunction with Figs. 7 and 6A. Therefore, detailed description of the operation of the k-th stage ST (k) in the reverse mode will be omitted. However, the first and second transistors T1 and T2 connected to the first and second start terminals START1 and START2 in the reverse mode are connected to the first and second start reverse terminals START_R1 and START_R2 in the forward mode And operates substantially the same as the eleventh and twelfth transistors T11 and T12. The eleventh and twelfth transistors T11 and T12 connected to the first and second start reverse terminals START_R1 and START_R2 in the backward mode are connected to the first and second start terminals START1 and START2 in forward mode And operates substantially the same as the first and second transistors T1 and T2.

8 is a block diagram schematically showing a display device according to an embodiment of the present invention. Referring to FIG. 8, a display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit, a timing controller 11, and the like.

The display panel 10 is formed so that the data lines DL and the scan lines SL intersect with each other. The display panel 10 includes a pixel array PIXEL ARRAY in which pixels are arranged in a matrix in cell regions defined by data lines DL and scan lines SL.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data RGB from the timing controller 11. [ The source driver ICs 12 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, To the data lines (DL) of the display panel 10 so as to be synchronized with each other. The source drive ICs 12 may be connected to the data lines DL of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate drive circuit includes a level shifter 13 and a shift register 14. The level shifter 13 shifts the TTL (Logic-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 to the gate high voltage VGH and the gate low voltage VGL Level-shifting. The level-shifted clocks (CLKs) are input to the shift register (14). The shift register 14 is connected to the scan lines GL of the display panel 10 and sequentially outputs the scan pulses SP to the scan lines SL. The shift register 14 sequentially outputs the scan pulses SP in the forward direction in the forward mode and sequentially outputs the scan pulses SP in the reverse mode in the backward mode. The shift register 14 is formed directly on the lower substrate of the display panel 10 by a GIP (Gate Drive-IC In Panel) method. In the GIP scheme, the level shifter 13 is mounted on a printed circuit board 15.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data (RGB) input from the host system to the source drive ICs 12.

The timing controller 11 receives a timing signal such as a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a main clock from the host system through the LVDS or TMDS interface receiving circuit. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit, a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage VST and clocks CLKs sequentially generated in three phases. The start voltage VST is input to the shift register 14 to control the shift start timing of the shift register 14. The clocks CLKs are input to the level shifter 13 and level-shifted, then input to the shift register 14 and used as a clock signal for shifting the start voltage VST.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 12. [ The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, according to the present invention, voltage blocking transistors for preventing breakdown of a gate insulating film of thin film transistors connected to a Q node controlling the output of a shift register are additionally formed, and a gate low voltage Supply. As a result, the present invention can prevent the breakdown of the gate insulating film of the thin film transistors connected to the Q node. As a result, the present invention can prevent abnormal output of the shift register, and thus it is possible to prevent defective horizontal line lighting of the display panel.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: shift register 15: printed circuit board

Claims (20)

A plurality of stages for sequentially receiving output clocks of i, i (i is a natural number of 4 or more) phase clocks sequentially delayed in phase,
K stages (k is a natural number satisfying 1? K? N, n is the number of stages) of the stages,
A Q-node discharging unit discharging a Q-node to a gate-low voltage in response to a signal input through the first and second start terminals;
A QB node charging unit responsive to a signal input through the first start terminal or charging a QB node to a gate high voltage higher than the gate low voltage in response to a gate low voltage of the Q node;
A Q node charging unit charging the Q node with the gate high voltage in response to the gate low voltage of the QB node;
A QB node discharging unit discharging the QB node to the gate-low voltage in response to a signal input through a reset terminal;
Wherein the Q node is composed of two transistors connected between the Q node discharging part and the Q node and between the Q node charging part and the Q node, respectively, and when the Q node is bootstrapped and lowered to a voltage level lower than the gate low voltage, A Q-node voltage cutoff unit for turning off the two transistors to cut off the connection between the Q-node discharging unit and the Q-node and between the Q-node charging unit and the Q-node; And
And an output unit for outputting a pulse synchronized with a clock inputted through a clock terminal according to a voltage of the Q node and the QB node. The method according to claim 1,
The Q-node voltage-
And a second node connected between the Q node discharging part and the Q node and turned on in response to the gate low voltage to connect the first node and the Q node between the Q node discharging part and the Q node voltage blocking part 8 transistors; And
And a ninth transistor connected between the Q node charging unit and the Q node and turned on in response to the gate low voltage to connect a second node between the Q node charging unit and the Q node voltage blocking unit to the Q node, And a shift register. 3. The method of claim 2,
The gate electrode of the eighth transistor is connected to the gate low voltage terminal, the source electrode is connected to the Q node, the drain electrode is connected to the first node,
The gate electrode of the ninth transistor is connected to the gate low voltage terminal, the source electrode is connected to the second node, and the drain electrode is connected to the Q node. 3. The method of claim 2,
The Q-node voltage-
A sixth transistor connected between the QB node charging unit and the Q node and turned on in response to the gate low voltage to connect the third node between the QB node charging unit and the Q node voltage blocking unit to the Q node; Further comprising a shift register. 5. The method of claim 4,
The gate electrode of the tenth transistor is connected to the gate low voltage terminal, the source electrode is connected to the third node, and the drain electrode is connected to the Q node. The method according to claim 1,
Wherein the first start terminal receives a start voltage or a carry signal of a previous stage, and the second start terminal, the clock terminal, and the reset terminal receives one of the i phase clocks,
Wherein the clock input to the clock terminal is a clock whose phase is delayed from the clock input to the second start terminal and the clock inputted to the reset terminal is a clock whose phase is delayed from the clock input to the clock terminal. register. The method according to claim 1,
The Q node discharger includes:
And discharges the Q node to a gate low voltage in response to a signal input through the first and second start reverse terminals. 8. The method of claim 7,
Wherein a start voltage or a carry signal of a previous stage is input to the first start terminal and a carry signal of a start reverse voltage or a subsequent stage is input to the first start reverse terminal and the carry signal of the second start terminal, , The clock terminal, and the reset terminal, respectively. 9. The method of claim 8,
In a forward mode in which the output of the output unit is sequentially generated in a forward direction,
Wherein the clock input to the clock terminal is a clock whose phase is delayed from the clock input to the second start terminal and the clock inputted to the reset terminal is a clock whose phase is delayed from the clock input to the clock terminal. register. 9. The method of claim 8,
In a reverse mode in which the output of the output unit is sequentially generated in the reverse direction,
Wherein a clock input to the clock terminal is a clock whose phase is delayed from a clock input to the second start reverse terminal and a clock input to the reset terminal is a clock whose phase is delayed from a clock input to the clock terminal, Shift register. 8. The method of claim 7,
The Q node discharger includes:
And a first transistor and a second transistor that are turned on in response to a signal input through the first and second start terminals to discharge the Q node to the gate low voltage. 12. The method of claim 11,
Wherein the gate electrode of the first transistor is connected to the first start terminal, the source electrode is connected to the drain electrode of the second transistor, the drain electrode is connected to the first start terminal or the gate low voltage terminal,
A gate electrode of the second transistor is connected to the second start terminal, a source electrode thereof is connected to a first node between the Q-node discharging portion and the Q-node voltage blocking portion, and a drain electrode is connected to the source And the electrode is connected to the electrode. 12. The method of claim 11,
The Q node discharger includes:
Further comprising an eleventh and twelfth transistors for turning on the Q node in response to a signal input through the first and second start reverse terminals to discharge the Q node to the gate low voltage. 14. The method of claim 13,
The gate electrode of the eleventh transistor is connected to the first start reverse terminal, the source electrode is connected to the drain electrode of the twelfth transistor, the drain electrode is connected to the first start reverse terminal or the gate low voltage terminal,
A gate electrode of the twelfth transistor is connected to the second start-reverse terminal, a source electrode thereof is connected to a first node between the Q-node discharging portion and the Q-node voltage blocking portion, And is connected to the source electrode. 8. The method of claim 7,
The QB node charging unit,
And a sixth transistor and a seventh transistor that are turned on in response to a signal inputted through the first start terminal or a gate low voltage of the Q node to charge the QB node with the gate high voltage. register. 16. The method of claim 15,
A gate electrode of the sixth transistor is connected to a third node between the first start terminal or the Q-node voltage blocking unit and the QB node charging unit, the source electrode is connected to the drain electrode of the seventh transistor, Connected to the QB node,
The gate electrode of the seventh transistor is connected to the third node between the first start terminal or the Q-node voltage blocking portion and the QB node charging portion, the source electrode is connected to the gate high voltage terminal, And the source electrode of the transistor is connected to the source electrode of the transistor. 16. The method of claim 15,
The QB node charging unit,
A thirteenth transistor that is turned on in response to a signal input through the first start terminal to charge the QB node to a gate high voltage; And
And a 14th transistor that is turned on in response to a signal input through the first start reverse terminal to charge the QB node to a gate high voltage. 18. The method of claim 17,
The gate electrode of the thirteenth transistor is connected to the first start terminal, the source electrode is connected to the gate high voltage terminal, the drain electrode is connected to the QB node,
The gate electrode of the fourteenth transistor is connected to the first start reverse terminal, the source electrode is connected to the gate high voltage terminal, and the drain electrode is connected to the QB node. The method according to claim 1,
Wherein the output of the output section is supplied to the scan line of the display panel and also functions as a carry signal of the front stage or the rear stage. A display panel including data lines and scan lines crossing the data lines;
A data driving circuit for supplying a data voltage to the data lines; And
And a shift register for sequentially supplying scan pulses to the scan lines in synchronization with the data voltage,
The shift register includes:
A plurality of stages for sequentially receiving output clocks of i, i (i is a natural number of 4 or more) phase clocks sequentially delayed in phase,
K stages (k is a natural number satisfying 1? K? N, n is the number of stages) of the stages,
A Q-node discharging unit discharging a Q-node to a gate-low voltage in response to a signal input through the first and second start terminals;
A QB node charging unit responsive to a signal input through the first start terminal or charging a QB node to a gate high voltage higher than the gate low voltage in response to a gate low voltage of the Q node;
A Q node charging unit charging the Q node with the gate high voltage in response to the gate low voltage of the QB node;
A QB node discharging unit discharging the QB node to the gate-low voltage in response to a signal input through a reset terminal;
Wherein the Q node is composed of two transistors connected between the Q node discharging part and the Q node and between the Q node charging part and the Q node, respectively, and when the Q node is bootstrapped and lowered to a voltage level lower than the gate low voltage, A Q-node voltage cutoff unit for turning off the two transistors to cut off the connection between the Q-node discharging unit and the Q-node and between the Q-node charging unit and the Q-node; And
And an output unit for outputting a pulse synchronized with a clock inputted through the clock terminal according to the voltage of the Q node and the QB node.

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