KR101776298B1 - Embedded PCB and Manufacturing method of the same - Google Patents

Abstract

The present invention relates to a method of manufacturing a buried printed circuit board and a structure therefor. More particularly, the present manufacturing process includes a first step of forming a chip mounting area on a top surface of a first metal layer formed on a carrier and mounting an electronic device chip, Forming an internal circuit pattern layer including an insulating layer and a second metal layer for embedding the device chip, forming an external circuit pattern layer electrically connecting the internal circuit pattern layer and the solder via via the conductive via, .
According to the present invention, in manufacturing a buried printed circuit board (Embedded PCB) in which an active element and a passive element are embedded in a substrate, a solder via for directly connecting a connection terminal of the element and an external circuit is provided, The active device and the passive device can be bonded together at the same time and the electrical connection to the external pattern can be realized by one solder via, thereby improving the productivity by simplifying the process. Particularly, the pad pitch of the active device There is an effect that the minute size can be reduced.

Description

[0001] Embedded printed circuit board and manufacturing method thereof [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a buried type printed circuit board, and more particularly, to a technique capable of realizing efficient packaging structure and method of an electronic device chip.

Printed circuit boards are solidifying their position as one of the electronic components at the same time as the development of semiconductors and electronic devices. They are used in all kinds of electrical and electronic devices, such as radio, television, PCS, Is widely used as a component for implementing the circuit of FIG. Recently, as technological advances in this field have become remarkable, a high quality of a printed circuit board has been demanded, which has led to a rapid increase in density. Particularly, in the manufacture of embedded PCBs, metal parts such as Au are plated on the parts to be surface mounted, and masking treatment is performed using dry film resist (hereinafter referred to as "DFR"). This is accomplished through the process of

One of the most important core technologies of Embedded PCB is whether high I / O count of internal parts is supported. As a result, it can be expressed as a level of implementation of fine pitch. For this purpose, in most developed technologies, vias and lands or metal bumps / lands are used to connect electronic device chips to circuits. , Or a bonding process using a structure such as a solder and a solder / pad, using a fine pattern circuit technology.

Referring to FIG. 1, this conceptually illustrates a process of mounting an electronic device chip on a printed circuit board using a solder and a solder / pad in a conventional manufacturing process of a buried type printed circuit board.

Conventionally, in order to connect the electronic element chip 5 to the inner layer circuit board on which the insulating layer 1, the outer metal layers 2 and 2 'and the circuit pattern 3 are implemented, as shown in the drawing, the solder ball pads 6 The solder ball 7 is formed on the printed circuit board 3 and indirectly connected to a part of the circuit pattern 3 of the printed circuit board. Thereafter, the insulating layer 8 is laminated to form an outer circuit pattern (10) or the via hole (11) is plated to complete the circuit.

In this case, it is necessary to connect vias and lands, metal bumps and lands, or solder and solder pads to connect the built-in transfer element chips to the printed circuit board. However, in this case, there is a limit in reducing the pitch of the component electrodes. Particularly, when a solder pad is used, there is a case where a passive element is connected to a solder printing technique due to a difference in technical difficulty between the passive element and the active element, while the active element is connected with another bonding technique . In this case, there is a possibility that the workability due to the addition of the process is limited and additional defects may occur.

In addition, when a chip is connected using a via, a plating technique such as fill plating is applied due to the process connection, but there is a need to invest in a separate facility and raise a material cost.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems described above, and it is an object of the present invention to provide a method of manufacturing a buried type printed circuit board (Embedded PCB) in which an active element and a passive element are embedded in a substrate, The present invention relates to a solder via for connecting a device and a pad together by connecting the active element and the passive element at the same time and by electrically connecting the external pattern to the external pattern by a single solder via, And to provide a manufacturing process capable of extremely miniaturizing the pad pitch of the active device.

As a means for solving the above-mentioned problems, the present invention is a semiconductor device comprising: a first step of forming a chip mounting region on an upper surface of a first metal layer formed on a carrier and mounting an electronic device chip; A second step of forming an internal circuit pattern layer including an insulating layer and a second metal layer for embedding the electronic device chip; Forming an external circuit pattern layer electrically connecting the internal circuit pattern layer and the solder via via the conductive via; And a method of manufacturing the buried type printed circuit board.

The first step includes: a 1) forming a chip mounting region by forming a peripheral portion of a chip mounting region on a top surface of the first metal layer as a metal pattern layer; a 2) bonding the electronic device chip to a chip mounting area via an adhesive material; ≪ / RTI > Particularly, the a1) step may be performed by any one of screen printing, electroplating, suppering, evaporation, ink jetting and dispensing on the top surface of the first metal layer or a combination thereof , And the step a2) may include at least one active element via an adhesive material on the chip mounting region, or may include a step of forming a metal pattern layer using the active element and the passive element 1 or more.

In addition, the second step in the manufacturing process described above may include the steps of: 1) laminating at least one insulating layer group for embedding a peripheral portion of the electronic device chip and an internal circuit metal layer on the insulating layer group; b) separating the carrier from the first metal layer and performing etching on the first metal layer until a terminal portion of the electronic device chip is exposed; b 3) patterning the internal circuit metal layer and the first metal layer to form an internal circuit pattern; As shown in FIG.

The above-described three steps in the manufacturing process may include: 1) laminating an external insulating layer for embedding the internal circuit pattern; c2) processing the outer insulating layer to form solder vias and conductive vias; c) forming an external circuit pattern electrically connected to the electronic device chip or the internal circuit pattern; As shown in FIG. In this case, in the step c2), a process hole may be formed so that the external insulating layer may be exposed to the outside of the internal circuit pattern or the terminal of the electronic device chip, the solder material may be filled in the process hole, To form solder vias and conductive vias.

In this case, the filling of the solder material for forming the solder via can be performed by a solder printing process by taking a metal mask.

The electrical connection between the electronic device chip and the external circuit pattern may be performed through the solder via. The electrical connection between the internal circuit pattern and the external circuit pattern may include a conductive via Lt; / RTI >

The method may further include the step of patterning and forming a sol-resistant resist layer to selectively expose a part of the external circuit pattern after the step 3, and forming a surface treatment layer on the exposed surface of the external circuit pattern, .

In this case, the surface treatment layer is subjected to plating treatment in a single layer or in multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, or a binary or an alloy thereof on the exposed surface of the external circuit pattern .

In addition to the above-described manufacturing steps, the step of laminating the insulating layer and the metal layer on the upper surface of the external circuit pattern, and processing the circuit pattern electrically connected to the external circuit pattern by processing the metal layer is repeated at least once or more A plurality of layers of the printed circuit board can be formed.

The structure of the printed circuit board manufactured according to the above-described manufacturing process is as follows.

Specifically, an external circuit pattern electrically connected to a plurality of internal circuit patterns formed inside the insulating layer; A solder via connecting the electronic device chip embedded in the insulating layer and the external circuit pattern; As shown in FIG.

In this case, the electrical connection between the inner and outer circuit patterns may be realized through a plating via filled with a plating material in the via hole. The inner circuit pattern may include a first inner circuit Pattern and a second internal circuit pattern that is spaced apart from an upper portion of the electronic device chip.

The electronic element chip in the above-described structure may be at least one or more than one active element and a passive element disposed in a chip mounting region between the first internal circuit patterns. In this case, And the terminal of the electronic device chip may be filled with an adhesive material.

A solder resist pattern layer selectively exposing a part of the external circuit pattern of the buried type printed circuit board according to the present invention and a surface treatment layer formed on an exposed surface of the external circuit pattern, In this case, the surface treatment layer is subjected to plating treatment in a single layer or in multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, or a binary or an alloy thereof on the exposed surface of the external circuit pattern .

And a buried printed circuit board having a structure in which at least one second external circuit pattern and an insulating layer are stacked on the external circuit pattern and electrically connected to the external circuit pattern.

According to the present invention, in manufacturing a buried printed circuit board (Embedded PCB) in which an active element and a passive element are embedded in a substrate, a solder via for directly connecting a connection terminal of the element and an external circuit is provided, The active device and the passive device can be bonded together at the same time and the electrical connection to the external pattern can be realized by one solder via, thereby improving the productivity by simplifying the process. Particularly, the pad pitch of the active device There is an effect that the minute size can be reduced.

Particularly, it is possible to cope with the pad pitch of the active element of 150 탆 or less and to maximize the degree of freedom of design of the printed circuit board by simultaneously connecting the external circuit with the passive element and the active element at the same time There are advantages.

1 is a conceptual view showing a process of mounting a conventional electronic device chip on a printed circuit board.
2A to 2E are a flow chart and a process diagram showing a manufacturing process of a buried type PCB according to the present invention.
3 is a process diagram showing a manufacturing process of a modified embodiment of the printed circuit board according to the present invention.

Hereinafter, the configuration and operation according to the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same reference numerals denote the same elements regardless of the reference numerals, and redundant description thereof will be omitted. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The present invention realizes electrical connection between an electronic element chip and an external circuit through a solder via filled with a solder material instead of a separate pad or solder ball so that material cost can be reduced without introducing new equipment investment and fine pitch can be realized Technology is provided.

FIGS. 2A to 2E are a flow chart and a process diagram of a manufacturing process of a buried type printed circuit board according to the present invention.

A manufacturing process of a printed circuit board according to the present invention includes a first step of forming a chip mounting area on a top surface of a first metal layer formed on a carrier and mounting an electronic device chip, And forming an external circuit pattern layer electrically connecting the internal circuit pattern layer and the solder via via the conductive via.

The above-described process will be described in detail with reference to the flowchart and the flowchart shown in the drawings.

1. Mounting the electronic device chip in the chip mounting area (Step 1)

In the first step, as shown in FIG. 2B, a chip mounting area is formed on the top surface of the first metal layer 110 formed on the carrier 120, and the electronic device chip is mounted on the chip mounting area (Step S 1).

Specifically, the carrier 120 supporting the first metal layer 110 is laminated (S11 to S12), as shown in the detailed step of Step S1. The carrier 120 may be a carrier capable of stably supporting the first metal layer 110 in the manufacturing process. In this embodiment, the carrier 120 may be formed of a copper foil layer 121, an adhesive material 122, And a supporting insulating layer 123 is applied. The copper foil layer 121 and the first metal layer 110 are then released to remove carriers. It is preferable that the thickness of the copper foil layer 121 is thicker than the thickness of the first metal layer 110 in order to facilitate the release.

A dry film resist D is patterned on the upper surface of the first metal layer 110 and a metal pattern layer 130 is formed through a plating process to form a chip mounting region C (S13 to S14) . In this case, a method of forming the metal pattern layer 130 may be one of screen printing, electroplating, sputtering, evaporation, ink jetting, and dispensing on the upper surface of the first metal layer. A process of embodying a metal pattern layer may be performed using a combination of the two methods.

The chip mounting area C is a region in which the metal pattern layer 130 is formed as a cavity and then the electronic device chips 150 and 151 are bonded to the space through an adhesive material B S17). The electronic device chip is a concept including an active device or a passive device.

2. Process of forming internal circuit pattern layer (step 2)

After the step of mounting the electronic device chip, a step of forming an internal circuit pattern layer including the insulating layer and the second metal layer for embedding the electronic device chip is performed (step S 2). In particular, A buried printed circuit board on which a plurality of chips including the active device chip 140 are mounted is described as a preferred embodiment. The buried type printed circuit board may be formed of only at least one active device chip 140, ) Are mounted.

Referring to FIG. 2C, at least one insulation layer group 160 for embedding a peripheral portion of the electronic device chip on the top of the electronic device chip 140, 150 mounted thereon, A step of laminating the circuit metal layer 170 is performed (S21). In the insulating layer group 160, the external insulating layer may be an epoxy, a phenol resin, a prepreg, a polyimide film, an ABF film, or the like. The insulating layer group includes a first insulating layer group 161 surrounding the periphery of the electronic device chip and a second insulating layer group 162 stacked on the upper portion of the electronic device chip and the first insulating layer group 161 And the first insulating layer group 161 may have a structure in which a position corresponding to the electronic device chip is basically opened. (Unlike the present embodiment, the first insulating laminated group 161 may have a predetermined circuit pattern on its surface, and may have a structure for electrically connecting the circuit patterns through via holes. )

Next, the above-described carrier is separated from the first metal layer (S23), and the separated substrate is flipped and the subsequent process is performed (S24).

The first metal layer 110 is etched until the terminal portion of the electronic element chip 140 is exposed after the substrate is turned over for the convenience of the process. In this case, the metal pattern layer 130 and the electron The terminals of the device chip and the adhesive material may be exposed (S25).

Thereafter, the internal circuit patterns can be formed by patterning the dry film resist (D 1, D 2) on both sides of the substrate and selectively etching the metal pattern layer 130 and the internal circuit metal layer 170. The internal circuit pattern includes a first internal circuit 131 formed by etching the metal pattern layer 130 and a second internal circuit 171 patterned with the internal circuit metal layer 170. The outer insulating layers 180 and 181 may then be laminated for further processing. This will be described below. The external insulating layer may be an epoxy, a phenol resin, a prepreg, a polyimide film, an ABF film, or the like.

3. External circuit pattern layer formation and solder via formation (step 3)

2D, after the internal circuit patterns 131 and 171 are formed, the external insulating layers 180 and 181 for embedding the internal circuit patterns are stacked, A machining hole H is formed through mechanical machining (S31). The processing hole H is preferably formed such that a terminal portion of the electronic device chip is exposed or an internal circuit pattern surface is exposed.

Then, a metal mask M is placed on a part of the processing hole H, and a solder via SP is formed through a solder printing process. The solder via SP is a structure in which a solder paste is filled in a machining hole, and the solder via electrically connects a terminal of the upper electronic device chip to an external circuit pattern. In the solder screen printing method, screen printing is performed by using a metal mask (M), and it is possible to control the thickness and design of the metal mask and the amount of solder to be printed upon solder printing. Thereafter, reflow and Dwflux processes may be involved.

Thereafter, an outer circuit metal layer 190 is formed to fill the plurality of process holes H 1 in which the solder vias SP are not implemented and to form the outer circuit (S34). A structure for filling electrical connection between an internal circuit pattern and an external circuit pattern to be described later by filling the processing hole H with a metal material other than a solder via is defined as a 'plating via H 2'. The filling of the metal material is most commonly performed by a plating method and is performed by using any one of screen printing, electrolytic plating, suppering, evaporation, ink jetting and dispensing, or a combination thereof .

Then, the outer circuit metal layer 190 is patterned to form an outer circuit pattern 191 (S35).

4. Surface treatment process

2E, the solder resist pattern layer 210 selectively exposes a part of the outer layer circuit pattern 191 in the process of step S 4, and a solder resist pattern layer 210 which selectively exposes a part of the outer layer circuit pattern 191, A step of further forming the surface treatment layer 211 to be formed may be added. In this case, the surface treatment layer may be formed by plating a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag and Co, or a binary or an alloy thereof on the exposed surface of the external circuit pattern .

5. Multi-layer implementation process

Referring to FIG. 3, a process of forming a printed circuit board having a structure different from the above-described structure by modifying the step after step S 3 in FIG. 2D will be described.

After the external circuit pattern 191 is completed, an insulating layer 220 and a metal layer 230 are laminated on the metal layer 230 (S 5 to S 7), and the metal layer is processed to electrically connect the external circuit pattern 191 The step of processing the second external circuit pattern 232 to be connected (S8 to S9) is repeated at least once, so that the multilayer printed circuit board having a multilayer structure can be realized. The electrical connection between the external circuit pattern 191 and the second external circuit pattern 232 is realized by processing the via hole H 3 and filling the metal via the via hole H 3 in the step S 9.

The buried type printed circuit board formed by the manufacturing process described above can be formed with the following structure. The structure of the printed circuit board to be manufactured will be described with reference to the structure of FIG. 2E and the structure of the step S9 of FIG. 3E.

The buried type printed circuit board according to the present manufacturing process includes an external circuit pattern 191 electrically connected to a plurality of internal circuit patterns 131 and 171 formed in the insulating layer 160, And the solder vias SP connecting the external circuit patterns 191 with the electronic device chips 140, 150, and 151 embedded in the internal circuit patterns 160 and 160.

That is, the electrical connection between the connection terminals of the electronic device chips 140, 150 and 151 and the external circuit pattern 191 can be realized through the solder via SP filled with the solder paste, The electrical connection between the inner and outer circuit patterns 131 and 191 is realized through the plating via H 2 filled with the plating material in the via hole.

In addition, in the above-described structure, the internal circuit patterns 131 and 171 include a first internal circuit pattern 131 formed on the terminal surface of the electronic device chip and a horizontal plane, The electronic device chip may include at least one or more of the internal circuit patterns 171. In this case, the electronic device chip may include at least one active device disposed in the chip mounting region between the first internal circuit patterns 131, And may be formed of at least one active element and a passive element. In addition, an adhesive material may be filled in the interface between the chip mounting area and the terminals of the electronic device chip.

In addition, the buried type printed circuit board according to the present invention includes a solder resist pattern layer 210 selectively exposing a part of the external circuit pattern 191, a surface treatment layer 211 formed on the exposed surface of the external circuit pattern, And the surface treatment layer 211 may be formed by using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or an alloy thereof on the exposed surface of the external circuit pattern Or may be formed with a structure in which plating is performed by a single layer or a multilayer.

3, at least one external circuit pattern 232 and an insulating layer 220, which are electrically connected to the external circuit pattern, are stacked on the external circuit pattern 191, But may be implemented as a substrate.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

110: first metal layer
120: Carrier
130: metal pattern layer
131: 1st internal circuit
140: active element
150: Passive element
160: first insulation layer group
170: internal circuit metal layer
171: Second internal circuit
180: outer insulating layer
190: external circuit metal layer
191: External circuit pattern
210: Solder resist
211: Surface treatment layer

Claims (20)

Disposing a first metal layer on the carrier;
Forming a metal pattern layer including a cavity in which a chip mounting area is opened on the first metal layer;
Forming an adhesive layer in the cavity of the metal pattern layer;
Mounting an electronic device chip in the cavity using the adhesive layer;
Forming an internal circuit pattern layer including a first insulating layer for embedding the electronic device chip on the metal pattern layer and a second metal layer on the first insulating layer;
Separating the carrier from the first metal layer and etching the first metal layer until a terminal portion of the electronic device chip is exposed;
Forming a first internal circuit pattern by patterning the metal pattern layer and patterning the second metal layer to form a second internal circuit pattern;
Inverting the first insulating layer such that the first internal circuit pattern is located on the first insulating layer;
Forming a second insulating layer on the first insulating layer to cover the first internal circuit pattern, the adhesive layer, and the terminal portions of the electronic device chip;
Forming at least one first via hole exposing the first internal circuit pattern and at least one second via hole exposing the terminal portion by processing the second insulating layer;
Filling the at least one first via hole with a metallic material to form a conductive via and filling the at least one second via hole with a solder paste to form a solder via;
And forming an external circuit pattern electrically connected to the first internal circuit pattern and the terminal portion of the electronic device chip through the conductive via and the solder via on the second insulating layer,
The thickness of the first internal circuit pattern is preferably,
Is equal to the thickness of the adhesive layer,
The upper surface of the first internal circuit pattern, the upper surface of the adhesive layer, and the upper surface of the terminal portion are arranged on the same plane,
Wherein the electronic device chip and the external circuit pattern are electrically connected to each other,
Electrically connected through the solder via,
Wherein the first internal circuit pattern and the external circuit pattern are electrically connected to each other,
And electrically connected through the conductive vias.
delete The method according to claim 1,
The forming of the metal pattern layer may include:
Wherein the first metal layer is formed on the upper surface of the first metal layer by using any one of screen printing, electroplating, sputtering, evaporation, ink jetting, And embedding the metal pattern layer on the printed circuit board.
The method according to claim 1,
Wherein the mounting comprises:
Mounting at least one active element on the adhesive layer formed in the cavity, or mounting at least one active element and at least one passive element, respectively.
delete delete delete delete delete The method according to claim 1,
A step of patterning and forming a polysilicon layer so as to selectively expose a part of the external circuit pattern on the second insulating layer;
Further comprising the step of forming a surface treatment layer on the exposed surface of the external circuit pattern.
The method of claim 10,
The surface-
Wherein the exposed surface of the external circuit pattern is plated with a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, and Co, Gt;
The method according to claim 1,
A step of laminating an insulating layer and a metal layer on the upper surface of the external circuit pattern and processing the circuit pattern electrically connected to the external circuit pattern by processing the metal layer is repeated at least once or more.
A first insulating layer;
A first internal circuit pattern disposed on an upper surface of the first insulating layer and including a cavity corresponding to a chip mounting area;
A second internal circuit pattern disposed on a lower surface of the first insulating layer;
An adhesive layer applied in the cavity;
An electronic element chip disposed in the adhesive layer, at least a part of which is inserted into the cavity;
A second insulating layer disposed on the first insulating layer and filling the first internal circuit pattern, the adhesive layer, and the electronic device chip;
An external circuit pattern disposed on the second insulating layer;
A conductive via electrically connecting the first internal circuit pattern and the external circuit pattern, the conductive via including a metallic material filled in a first via hole passing through the second insulating layer; And
And a solder via filled in a second via hole passing through the second insulating layer, the solder via electrically connecting the terminal portion of the electronic device chip to the external circuit pattern,
The thickness of the first internal circuit pattern is preferably,
Is equal to the thickness of the adhesive layer,
Wherein an upper surface of the first internal circuit pattern, an upper surface of the adhesive layer, and an upper surface of the terminal portion are disposed on the same plane.
delete delete delete delete 14. The method of claim 13,
A solder resist pattern layer disposed on the second insulating layer and selectively exposing a portion of the external circuit pattern; and a surface treatment layer formed on an exposed surface of the external circuit pattern.
19. The method of claim 18,
The surface-
Wherein at least one of the Cu, Ni, Pd, Au, Sn, Ag, and Co is formed on the exposed surface of the external circuit pattern by a single layer or multilayer plating process.
14. The method of claim 13,
At an upper portion of the external circuit pattern,
A second external circuit pattern electrically connected to the external circuit pattern, and a third insulating layer.

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