KR101429921B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display, which includes a data line intersecting a gate line, and two liquid crystal cells are provided between two adjacent data lines in a direction parallel to the gate line, And a common line provided between the two liquid crystal cells, wherein the liquid crystal cell is formed on the same layer as the common electrode, Wherein the common electrode of the two liquid crystal cells provided between the two data lines has a structure extending from the one common line to the pixel electrode, , The common line is formed of a transparent conductive material, and the second line of the gate lines Th gate line (i is a natural number) and the (2i + 1) th gate line are formed adjacent to each other.

Inflation switching mode, aperture ratio

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of improving an aperture ratio of a liquid crystal display device.

Generally, liquid crystal display devices have various modes depending on the arrangement of liquid crystal molecules. For example, the liquid crystal display device is divided into a TN mode (Twisted Nematic Mode) for controlling the liquid crystal director by the vertical electric field and an In-Plane Switching Mode for controlling the director of the liquid crystal by the horizontal electric field .

Here, the infra-red switching mode liquid crystal display device is constituted by a color filter array substrate and a thin film array substrate which are opposed to each other with a liquid crystal layer therebetween. On the color filter array substrate, a black matrix for preventing light leakage and a color filter layer for coloring on a black matrix are formed. A thin film transistor array substrate is provided with gate lines and data lines defining unit pixels, thin film transistors formed at intersections of gate lines and data lines, and common electrodes and pixel electrodes formed in parallel to each other to generate a horizontal electric field.

Such an in-plane switching mode liquid crystal display device requires a large number of data lines and gate lines in a large area. In particular, if the number of data lines increases, the number of data driver ICs that supply image signals to the data lines also increases, resulting in an increase in manufacturing cost.

Also, the liquid crystal driving method using the horizontal and vertical electric fields of the common electrode and the pixel electrode is excellent in the viewing angle characteristic, but the aperture ratio and the luminance are lowered. Therefore, a high aperture ratio liquid crystal display device is required in consideration of efficiency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of improving the aperture ratio in a liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel in which at least two liquid crystal cells arranged in a direction parallel to a gate line are supplied with a data signal through one data line, At least one common line formed between lines, a plurality of common electrodes connected to the common line, a pixel electrode having a horizontal electric field with the common electrode, and a thin film transistor connected to the pixel electrode, The second (i-th) gate line and the (2i + 1) -th gate line of the gate lines are formed adjacent to each other.

The liquid crystal display device according to the present invention has the following effects.

First, by forming one data line per at least two liquid crystal cells, the number of data lines and data driver ICs can be reduced, thereby improving the aperture ratio.

Second, the aperture ratio can be improved by forming the liquid crystal cells adjacent to the upper and lower sides to share the source electrode.

Third, the data lines and the pixel electrodes in the odd-numbered pixel region and the odd-numbered pixel region are formed to be symmetrical with respect to the common line, so that the coupling size between the data lines and the pixel electrode is the same.

Fourth, the aperture ratio can be improved by forming the liquid crystal cells adjacent to each other between the data lines DL to share a common line.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a thin film transistor substrate of an in-plane switching mode liquid crystal display according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a thin film transistor substrate taken along a line I-I 'shown in FIG.

The switching mode liquid crystal display of FIG. 1 and FIG. 2 includes a plurality of gate lines GL formed on a substrate 100 and a gate electrode GL formed to cross the gate lines GL with the gate insulating film 112 interposed therebetween. A thin film transistor TFT formed at a portion where the gate line GL and the data line DL intersect each other and a plurality of pixel electrodes GL connected to the thin film transistor TFT A common electrode 140 forming a horizontal electric field with the pixel electrode 130 in each pixel region and a common line CL connected to the common electrode 140 between the data line DL do. Here, the pixel electrode 130 and the common electrode CL are an in-plane switching structure applied with lateral rubbing.

The gate line GL and the data line DL are connected to a pad terminal connected to the driving circuit portion in the outer portion of the thin film transistor array to supply a gate signal and a data signal to the thin film transistor TFT. The second i-th gate line GL2i (i is a natural number) and the (2i + 1) -th gate line GL2i + 1 are formed adjacent to each other.

The common line CL is formed in parallel with the data line DL between the data lines DL and the odd-numbered common line CL2k-1 (k is a natural number) and the even-numbered common line CL2k are adjacent to each other And supplies a reference voltage for driving the liquid crystal to the common electrode 140. [

The liquid crystal cells located on both sides of the common lines CL are connected to different data lines DL and the liquid crystal cells located on both sides of the data line DL are connected to the data lines DL Share. Here, the liquid crystal cell means the common electrode 140 and the pixel electrode 130 facing each other with the liquid crystal therebetween.

The thin film transistor TFT includes a gate electrode 102 branched from the gate line GL, a gate insulating film 112 formed on the entire surface of the substrate 100 on which the gate electrode 102 is formed, A semiconductor layer 108 composed of an ohmic contact layer 108a and an active layer 108b formed so as to overlap with the gate electrode 102 and a source electrode 110a formed on the semiconductor layer 108 at the data line DL, And a drain electrode 110b formed on the semiconductor layer 108 so as to face the source electrode 110a.

The pixel electrode 130 includes a vertical portion 130a formed in parallel with the data line DL and a plurality of fingers 130b extending from the vertical portion 130a of the pixel electrode 130 in parallel with the gate line GL. 130b. The fingers 130b of the pixel electrode 130 are formed to be inclined so as to be symmetrical with respect to each other at the center of the pixel region. The uppermost and lowermost fingers of the plurality of fingers 130b are formed to have a relatively thicker width than the pad finger. The lowest finger is connected to the drain electrode 110b through the contact hole 150 passing through the protective film 120. [

The common electrode 140 is branched from the common line CL and alternately formed with the fingers 130b of the pixel electrode 130 to form a horizontal electric field. The finger electrodes 140b of the common electrode 140 are formed to be inclined so as to be symmetrical with each other at the center of the pixel region like the finger electrode 130b of the pixel electrode 130. [

The pixel electrode 130 and the common electrode 140 may be formed of a transparent conductive layer or an opaque metal layer. As the transparent conductive layer, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO) . As the opaque metal layer, a metal such as molybdenum (Mo), aluminum (Al), aluminum-neodymium (Al-Nd), copper (Cu), chromium (Cr), titanium (Ti) Layer structure.

The odd-numbered liquid crystal cell and the odd-numbered liquid crystal cell are formed symmetrically with respect to the common line CL, ie, the data line DL, the pixel electrode 130, the common line CL, the common line CL, 130, and a data line DL. Here, if the data line DL, the pixel electrode 130, the common line CL, the pixel electrode 130, the common line CL, and the data line DL are formed in this order, 130 and the data line DL and the coupling line between the pixel electrode 130 and the data line DL in the odd-numbered pixel region are different from each other, so that a vertical line defect occurs. To prevent this, DL) and the pixel electrode 130, the aperture ratio is reduced.

Therefore, the data lines DL and the pixel electrodes 130 in the odd-numbered pixel region and the even-numbered pixel region are formed to be symmetrical with respect to the common line CL, so that the distance between the data lines DL and the pixel electrodes 130 The coupling size becomes the same, and the vertical line defect can be prevented. In addition, the aperture ratio can be improved by sharing the common line CL.

The common line CL may be formed such that the odd-numbered liquid crystal cell and the even-numbered liquid crystal cell share each other as shown in FIG.

Though not shown in the figure, the thin film transistor substrate 100 is bonded together with the color filter substrate and the liquid crystal layer interposed therebetween. The color filter substrate includes a black matrix formed so as to prevent light leakage and pixel regions, and a color filter layer for expressing color hues. Here, the black matrix is formed to correspond to a metal pattern such as a gate line GL and a data line DL of the TFT substrate 100.

As described above, the structure in which the common line CL is formed between the data lines DL, that is, the structure shown in FIGS. 1 and 3, can reduce the data line DL shown in FIGS. 4A to 4D Applicable.

4A to 4D are circuit diagrams showing first and fourth embodiments of a liquid crystal panel capable of saving a data line DL.

FIG. 4A is a cross-sectional view of a semiconductor device in which thin film transistors (TFTs) are arranged in an S-shape, FIG. 4B is a cross- And 4d are formed by disposing thin film transistors (TFTs) in an inverted S-shape. 4A to 4D show that at least one common line CL is formed between the odd-numbered data line DLk-1 and the even-numbered data line DL2k, and the even-numbered data line DL2k is shared with the adjacent pixel region. . That is, the number of the data lines DL and the number of the data driver ICs can be reduced by forming one data line DL per at least two liquid crystal cells, thereby improving the aperture ratio.

5 is a plan view illustrating a thin film transistor substrate 100 of an in-plane switching mode liquid crystal display device according to another embodiment of the present invention. FIG. 6 is a cross-sectional view taken along the line II- Fig.

5 and 6, the description of the redundant elements in the in-plane switching mode liquid crystal display device will be omitted in comparison with FIG. 1 and FIG.

5 and 6, the thin film transistor TFT connected to the second i-th gate line GL2i and the thin film transistor TFT connected to the (2i + 1) th gate line GL2i + 1 are connected to the source electrode 110a. The source electrode 110a is formed in an H-shape by being branched from the data line DL.

Each of the thin film transistors TFT includes a gate electrode 102 branched from the gate line GL, a gate insulating film 112 formed on the entire surface of the substrate 100 on which the gate electrode 102 is formed, A semiconductor layer 108 composed of an ohmic contact layer 108a and an active layer 108b formed on the semiconductor layer 108 to overlap with the gate electrode 102 on the data line DL, A source electrode 110a connected to the gate line GL2i and a (2i + 1) th gate line GL2i + 1, a drain electrode 110b formed on the semiconductor layer 108 to face the source electrode 110a, .

In this manner, the aperture ratio can be improved by forming the liquid crystal cells vertically adjacent to each other to share the source electrode 110a. In addition, the overlapped area between the source electrode 110a and the gate line GL is reduced as compared with the related art, so that the loading of the data line DL is also reduced, and the data line (DL) delay can be reduced.

As described above, the structure in which the upper and lower adjacent liquid crystal cells share the source electrode 110a is applicable to a facing thin film transistor (TFT) in a structure capable of saving the data line DL of FIGS. 4B to 4D.

7A to 7E are process sectional views showing a method of manufacturing the thin film transistor substrate 100 shown in FIG.

Referring to FIG. 7A, a first conductive pattern including a gate line GL and a gate electrode 102 is formed on a thin film transistor substrate 100.

Specifically, a gate metal layer is formed on the thin film transistor substrate 100 by a deposition method such as sputtering. Then, a trench gate metal layer is patterned by a photolithography process and an etching process using a mask to form a gate line GL and a gate electrode 102.

The gate metal layer may be formed of a single layer or a plurality of layers of metals such as molybdenum (Mo), aluminum (Al), aluminum-neodymium (Al-Nd), copper (Cu), chromium (Cr), titanium Layer structure.

Referring to FIG. 7B, a gate insulating layer 112 and a semiconductor layer 108 are sequentially formed on a substrate 100 including a first conductive pattern.

Specifically, a gate insulating layer 112, a gate insulating layer 112, and a gate insulating layer 114 are formed on the entire surface of the thin film transistor substrate 100 including the gate line GL, the gate electrode 102 and the common line 145 by a deposition method such as PECVD (Plasma Enhanced Chemical Vapor Deposition) An amorphous silicon (a-Si) layer and an amorphous silicon layer doped with an impurity (n +) are sequentially formed. Then, a semiconductor layer 108 composed of the active layer 108b and the ohmic contact layer 108a is formed by patterning by a photolithography process and an etching process using a mask.

As the gate insulating film 112, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

Referring to FIG. 7C, a source / drain pattern including a data line DL, source and drain electrodes 110a and 110b is formed on a semiconductor layer 108. In FIG.

Specifically, after a source / drain metal layer is formed on a substrate 100 including a semiconductor layer 108 by a deposition method such as sputtering, a source / drain metal layer including a data line DL, source and drain electrodes 110a and 110b Source / drain patterns are sequentially formed. At this time, a diffraction exposure or a half-tone mask is used for electrically separating the source and drain electrodes 110a and 110b from the ohmic contact layer 108a. Here, the source electrode 110a is connected to the upper and lower liquid crystal cells, that is, the thin film transistor (TFT) connected to the second i-th gate line GL2i and the (2i + 1) th gate line GL2i + 1 And the connected thin film transistors (TFTs) are formed to share with each other.

 The source / drain metal layer may comprise at least one of Mo, Al, Al-Nd, Cu, Cr, Ti, MoTi, (MoNb), and a titanium-niobium alloy (TiNb), and alloys thereof are formed in a single-layer or multi-layer structure.

Referring to FIG. 7D, a passivation layer 120 including a contact hole 150 is formed on a source / drain pattern.

Specifically, the protective film 120 is formed on the source / drain pattern including the data line DL, the source and drain electrodes 110a and 110b. Then, a contact hole 150 is formed on the passivation layer 120 to expose the drain electrode 110b by a photolithography process using a mask and an etching process.

The passivation layer 120 may be formed by depositing an inorganic insulating material such as the gate insulating layer 112 by a deposition method such as PECVD or by using an acryl based organic compound having a small dielectric constant, a BCB (Benzocyclobutene), a PFCB (Perfluorocyclobutane) an organic insulating material such as Teflon, Cytop or the like is formed by coating with a coating method such as spin or spinless.

Referring to FIG. 7E, a common line CL, a pixel electrode 130, and a common electrode 140 are formed on the passivation layer 120.

Specifically, a transparent conductive material is deposited on the passivation layer 120, and then patterned by a photolithography process and an etching process using a mask to form a common line CL and a drain electrode 110b through a contact hole 150, A pixel electrode 130 electrically connected to the common line CL and a common electrode 140 electrically connected to the common line CL and forming a horizontal electric field with the pixel electrode 130 are formed.

Here, the common line CL, the pixel electrode 130, and the common electrode 140 may be formed of an opaque metal layer. As the transparent conductive layer, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO) . As the opaque metal layer, a metal such as molybdenum (Mo), aluminum (Al), aluminum-neodymium (Al-Nd), copper (Cu), chromium (Cr), titanium (Ti) Layer structure.

The structure in which the source electrode 110a formed so as to be in common with the liquid crystal cells adjacent to the upper and lower sides is formed has a structure in which the common line CL is shared by the odd-numbered liquid crystal cells and the even-numbered liquid crystal cells as shown in Figs. 8A and 8B And is not limited to a liquid crystal display device of an in-plane switching mode.

The source electrode 110a may be formed in an inverse E-shape as shown in FIGS. 9A and 9B in a structure in which a source electrode 110a formed to be mutually shared with upper and lower liquid crystal cells is formed.

At this time, the central portion of the source electrode 110a of the inverted E-character is located between the second i-th gate line GL2i and the (2i + 1) -th gate line GL2i + 1 of the vertically adjacent liquid crystal cell, Th gate line GL2i and the (2i + 1) th gate line GL2i + 1.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. It will be clear to those who have knowledge.

1 is a plan view of a thin film transistor substrate of an in-plane switching mode liquid crystal display according to an embodiment of the present invention.

2 is a cross-sectional view of the thin film transistor substrate taken along the line I-I 'shown in FIG.

3 is a plan view of a thin film transistor substrate of an in-plane switching mode liquid crystal display according to another embodiment of the present invention.

4A to 4D are circuit diagrams showing first and fourth embodiments of a liquid crystal panel capable of saving data lines.

5 is a plan view of a thin film transistor substrate of an in-plane switching mode liquid crystal display according to another embodiment of the present invention.

6 is a cross-sectional view of the thin film transistor substrate taken along a line II-II 'shown in FIG.

FIGS. 7A to 7E are process sectional views showing a method of manufacturing the thin film transistor substrate shown in FIG.

8A and 8B are views showing a thin film transistor substrate of a switching mode liquid crystal display device in which an odd-numbered liquid crystal cell and an even-numbered liquid crystal cell are formed to share a common line.

FIGS. 9A and 9B are diagrams showing a thin film transistor substrate having a source electrode formed so as to be in common with upper and lower adjacent liquid crystal cells. FIG.

Description of the Related Art

GL: gate line DL: data line

CL: common line 100: thin film transistor substrate

102: gate electrode 108: semiconductor layer

110a, 110b: source and drain electrodes 112: gate insulating film

120: protective film 130: pixel electrode

140: common electrode 150: contact hole

Claims (7)

And a data line intersecting the gate line, wherein two liquid crystal cells are provided in a direction parallel to the gate line between two adjacent data lines, and the data signals are supplied from the different data lines to the two liquid crystal cells And a common line provided between the two liquid crystal cells, Wherein the liquid crystal cell comprises a common electrode, a pixel electrode formed on the same layer as the common electrode and having a horizontal electric field with the common electrode, and a thin film transistor connected to the pixel electrode, Wherein the common electrodes of the two liquid crystal cells provided between the two data lines extend in the one common line, The common line is formed of a transparent conductive material, And a second i-th gate line (i is a natural number) gate line and a (2i + 1) th gate line are formed adjacent to each other. delete The method according to claim 1, And the liquid crystal cells located on both sides of the data line share the data line. The method according to claim 1, And the thin film transistor connected to the (2i) -th gate line and the thin film transistor connected to the (2i + 1) -th gate line are formed so as to share a source electrode. The method according to claim 1, Wherein the two liquid crystal cells on both sides are formed symmetrically with respect to the common line. The method according to claim 1, Wherein the common line supplies a common voltage to the two liquid crystal cells on both sides based on the common line. The method according to claim 1, And the two liquid crystal cells located between the two data lines are formed symmetrically with the common line interposed therebetween.

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