KR100710608B1 - Flash memory with pre-detection for data loss - Google Patents

Abstract

A new method for detecting and calibrating weakly programmed cells of a nonvolatile memory device is achieved. The method includes providing a plurality of nonvolatile memory cells. The means for reading the selected cell compares the performance of the reference cell with the performance of the selected cell. The read state of the selected cell is high when the selected cell exceeds the reference cell. The read state of the selected cell is low when the selected cell is smaller than the reference cell. The first read state is obtained by biasing the reference cell to the first value and reading the selected cell. The second read state is obtained by biasing the reference cell to a second value that is greater than the first value and reading the selected cell. The selected cell is flagged as high, weakly programmed when the first and second read states do not match. The third read state is obtained by biasing the reference cell to a third value less than the first value and reading the selected cell. The selected cell is flagged low, programmed weakly when the first and third read states do not match. The selected cell is refreshed when the selected cell is weakly programmed.

Flash memory, flags, cells, read status, bias.

Description

Flash memory with pre-detection for data loss

1 illustrates a conventional nonvolatile memory cell.

2 illustrates a conventional method for reading selected cells of a nonvolatile memory.

3 shows a preferred embodiment of the method of the invention.

4 shows a first preferred embodiment of the device of the invention;

5 shows a second preferred embodiment of the device of the invention;

6 shows a third preferred embodiment of the device of the invention;

Fig. 7 shows a fourth preferred embodiment of the device of the present invention.

* Description of the symbols for the main parts of the drawings *

10 flash cells 14 drain

16 source 18 floating gate

20 control gates

The present invention relates to a nonvolatile memory device, and more particularly, to a method and circuit for preventing data retention errors of a nonvolatile memory device.

Nonvolatile memory is an important component of microprocessor-based systems. Maximum system flexibility is achieved through the use of nonvolatile, reprogrammable memories such as flash memory. By storing operating programs or key system parameters in flash memories, system performance in the field can be changed quickly and permanently.

Referring now to FIG. 1, a typical flash memory cell is shown in the form of schematic 22 and cross-section 10. The flash cell 10 is in the form of a MOS transistor having a source 16 and a drain 14 formed in the sub substrate region 12. The composite gate is formed to include a control gate (CG) 20 and a floating gate (FG) 18. The transistor can be operated by biasing the control gate 20, drain 14 and source 16 as is known in the art. The floating gate 18 includes a conductive region electrically insulated from the sub substrate 12 by the first dielectric region 17 and electrically insulated from the control gate 20 by the second dielectric region 19. As with any MOS transistor, the device is turned on when a bias is applied to the control gate 20 sufficient to create a channel region for carrying charge from drain 14 to source 16. The required control gate bias is defined as the threshold voltage V _TH . As is known in the art, the charge in the form of electrons can be injected into or out of the floating gate 18. The presence of charge on the floating gate 18 will change the V _TH of the device 10. This fact can be used to create a digital memory cell in which the first state is defined by the large presence of charge and the second state is defined by the absence of charge. To program or delete the state of the cell 10, relatively large voltage biases are applied to the control gate 20 to cause the injection of charge into the floating gate 18 or to remove the charge from the floating gate 18. ), Drain 14, and source 16 may be applied in combination. To read the state of the cell 10, the control gate 20 may be biased to a voltage at which the device should be turned on or off depending on the charged state of the floating gate. The voltage bias from drain 14 to source 16 will cause current to flow when the device is turned on. This current flow, or the absence of such a current flow, can be detected to determine the state of the cell 10 as is well known in the art.

Referring now to FIG. 2, a typical diagram of a circuit for reading a flash cell is shown. Cross section 30 of an integrated circuit device is shown representing an array 32 of nonvolatile cells. The particular cell 34 of the memory array is selected by asserting its wordline WL 42 and bitline BL by methods well known in the art. The WL voltage is connected to the control gate of the cell 34 and the BL voltage V _BL is connected to the drain. Cell current I _CELL is the drain-source current I _DS of cell 34. If the cell threshold voltage (V _TH ) exceeds the WL voltage, the cell 34 will be off and the I _CELL will be very small. If cell V _TH is less than WL voltage, cell 34 will be on and I _CELL will be very large.

To determine the relative V _TH , and thus cell 34 logic state, reference cell 36 is used. Reference cell 36 includes a comparable flash device having a fixed V _TH . The reference cell 36 control gate is biased with a reference voltage V _REF and the drain is biased with a bit line voltage V _BL . The reference current I _REF is generated. Comparator 40 is used to compare the reference current I _REF with the cell current I _CELL . Comparator output 46 is a decoded cell state that is high or low.

The logic state of each cell of the flash memory array is typically tested at the factory after programming. Theoretically, the solid state characteristics of the isolated floating gates and devices should produce very long data retention times. However, a statistical distribution of retention capacities of cells is known in the art, and some data cells will exhibit data retention times substantially shorter than average. It has also been found that these leaking cells have an inconsistent amount of floating gate charge over time. For example, if the cell is fully charged during programming, the cell will read the calibration cell state of 'X' for the first time, but the latter will read the undefined cell state of 'Y' when the floating gate is substantially discharged. . In the field, this shortened data holding cell will generate a single bit failure, as opposed to a grouped or burst failure. In some applications, particularly in automated or industrial control systems, product manufacturing due to such memory errors is a serious problem. Thus, the present invention is a great advantage for preventing such memory errors.

Some prior inventions relate to methods for detecting bit errors of nonvolatile memories. Sacki's U.S. Patent 6,483,745 B2 teaches a method and circuit for detecting and correcting soft errors in a nonvolatile cell. The cell is read three times using three different reference transistors. One criterion is a standard read criterion, one criterion is for a programmed state threshold, and one criterion is for an erase state threshold. By comparing the results of each of the three reads, the cell state and margin can be determined. Auclair et al. U.S. Patent 6,049,899 describes a method and circuit for detecting soft errors in a nonvolatile memory array. The cells are read using variable control gate voltages or variable reference currents to thereby evaluate the state and margin of the cell. Cells with inappropriate margins are refreshed. U.S. of Yoshida et al. Patent 6,525,960 B2 describes a method and circuit for writing multiple values of a nonvolatile memory array. A method for calibrating erratic cells is described.

The principle object of the present invention is to provide an efficient and highly productive integrated circuit device.

It is another object of the present invention to provide a method for detecting and correcting weak cell states in a nonvolatile memory device.                         

Another object of the present invention is to prevent bit errors in a nonvolatile memory device.

It is another object of the present invention to selectively refresh memory cells in a nonvolatile memory device in an efficient manner.

It is another object of the present invention to provide a method for continuously detecting weak cell states.

It is another object of the present invention to provide a method for a multilevel nonvolatile memory as well as in a binary nonvolatile memory.

It is another object of the present invention to provide a nonvolatile memory device capable of detecting weak cell states.

In accordance with the objects of the present invention, a method is provided for detecting and correcting a weakly programmed cell in a nonvolatile memory device. The method includes providing a plurality of nonvolatile memory cells. The means for reading the selected cell compares the performance of the selected cell with that of the reference cell. The read state of the selected cell is high when the selected cell exceeds the reference cell. The read state of the selected cell is low when the selected cell is smaller than the reference cell. The first read state is obtained by biasing the reference cell to the first value and reading the selected cell. The second read state is obtained by biasing the reference cell to a second value that is greater than the first value and reading the selected cell. The selected cell is flagged high, programmed weakly when the first and second read states do not match. The third read state is obtained by biasing the reference cell to a third value less than the first value and reading the selected cell. The selected cell is flagged low, programmed weakly when the first and third read states do not match. The selected cell is refreshed when the selected cell is weakly programmed.

Also in accordance with the objects of the present invention, a nonvolatile memory device is achieved. The device includes a plurality of nonvolatile memory cells and means for determining a read state of the selected cell by comparing the capabilities of the selected cell and the reference cell. The reference cell has a gate biased with a read value. The read state is either an upper value or a lower value based on the comparison. The means for determining the read state also includes a first reference cell having a gate set to the first value. The first comparator is coupled to the reference cell and the selected cell. The first read state is the output of the first comparator. The second reference cell has a gate set to a second value. The second comparator is coupled to the reference cell and the selected cell. The second read state is the output of the second comparator. The third reference cell has a gate set to a third value. The third comparator is coupled to the reference cell and the selected cell. The third read state is the output of the third comparator.

Preferred embodiments of the present invention describe methods for detecting and correcting weakly programmed flash memory cells. Architectures for reading flash memory cells are shown. It should be apparent to those skilled in the art that the present invention can be applied and extended without departing from the scope of the present invention.

Referring now to FIG. 3, a preferred embodiment of the method 60 of the present invention is shown. Some important features of the invention are shown and discussed below. This method 60 is also illustrated by the first embodiment device shown in FIG. 4, which is referred to herein. Referring again to FIG. 4, a first preferred embodiment of the integrated circuit device 100 is shown. Such device 100 includes an array 104 of nonvolatile devices. Non-volatile cells may include flash cells formed using any well known configurations and methods. Stacked gate or split-gate devices can be used. In addition, various addressing architectures may be used as is well known in the art. Certain cells 106 are shown as "selected" cells in an array. As main features, the addressing and biasing means causes a fixed read bias to collect on the WL 122 with respect to the cell 106 and a fixed BL bias V _BL to collect on the drain of the cell 106 so that the cell current _Allow (I _CELL ) to be generated. As in the conventional device described above, it is assumed that the relative cell current I _CELL will depend on the threshold voltage V _TH of the selected cell 106. Finally, V _TH will also depend on the stored charge on the floating gate of cell 106.

Means 108 are included for determining the read state of the selected cell 106 by comparing the performance of the selected cell 106 with the performance of some reference cells 110, 114, and 118. In particular, the means for determining the read state 108 includes a first reference cell 110 and a first comparator 138, a second reference cell 114 and a second comparator 146, and a third reference cell 118. ) And a third comparator 154. With this new arrangement, the drain current I _CELL of the selected cell 106 can be compared independently with three other reference cell drain currents I _NORM , I _UPPER , I _LOWER . The first reference cell control gate is biased with the first read value V _NORM . This first reading (V _NORM ) 126 is preferably equal to the midpoint between the upper state value and the lower state value. The first reference cell 110 drain current I _NORM is compared with the selected cell 106 using the first comparator 138. The output 142 of the first comparator 138 is in a first read state (cell state 1). For example, if I _CELL exceeds I _NORM , cell state 1 is a "top state" (which can also be defined as "1" or "0"). If I _CELL is less than I _NORM , cell state 1 is "lower state". Thus, the first comparator 138 is configured to perform a typical read function as in the prior art.

As an important characteristic, the second reference cell 114 and the second comparator 138 are selected cells for the second threshold level (V _UPPER ) 130 that is higher than the typical, first read threshold (V _NORM ) 126. 106) provide a means for testing. The control gate of the second reference cell 114 is set to the second read value V _UPPER 130 during the read operation. The drain current I _UPPER generated by the second reference cell 114 may be compared with the drain current I _CELL selected in the cell 106 using the second comparator 146. Cell state 2, which is the second read state, is the output 150 of the second comparator 146. In a preferred configuration, the cell state 2 is the "upper state" is, the I _CELL is "lower state" state cell 2 is less than I when the _{UPPER CELL} I exceeds I _UPPER. In a similar form, means for testing the selected cell for a third threshold level (V _LOWER ) 134 where the third reference cell 118 and the third comparator 154 are lower than the standard reading of V _NORM 126. To provide. The control gate of the third reference cell 118 is set to the third read value V _LOWER 134 during the read operation. The drain current I _LOWER generated by the third reference cell 118 may be compared with the drain current I _CELL selected in the cell 106 using the third comparator 154. Cell state 3, which is the third read state, is the output 158 of third comparator 154. In a preferred configuration, cell state 3 is an "upper state" when I _CELL exceeds I _LOWER and cell state 3 is a "lower state" when I _CELL is less than I _LOWER .

Referring again to FIG. 3, a preferred method 60 for detecting and correcting the states of the weak cells of the nonvolatile memory device described above is now described. The method 60 first includes reading the selected cells using the first read value to determine the first read state in step 65. The selected cells may comprise a group of cells, such as one byte (8 bits) or one word (16 bits). However, each cell or bit is read separately using the first reference cell 110 and the comparator 138 as shown in FIG.

Referring again to FIG. 3, at step 70, selected cells are read at a second read value where the second read value is greater than the first read value. Referring back to FIG. 4, this second read corresponds to reading using a second reference cell 114 biased at a second reference value V _UPPER and compared using a second comparator 146. . Referring again to FIG. 3, in step 75 as an important step, any cells for which the second read step does not match the first read step are flagged as weak, upper state cells. Referring back to the embodiment of FIG. 4, a comparison of cell state 2 150 reads and cell state 1 142 reads is generated, and if cell state 2 is not equal to cell state 1 for the selected cell 106, then Cell 106 may result in being programmed to an "upper" state. In addition, it may result that the cell is only weakly programmed into the "top" state. In other words, if the first read comparator 142 indicates that the cell is in an "upper" state, the cell 106 is discharged to the extent that it no longer has to pass the stricter V _LOWER threshold. In accordance with the teachings of the present invention, cell 106 is at risk of failure. Alternatively, if cell state 2 is equal to cell state 1, cell 106 is in the "bottom" state or cell 106 is strongly in the "top" state, so there is no risk of failure.

Referring again to FIG. 3, in step 80 selected cells at a third read value less than the first read value are read. Referring again to FIG. 4, this third readout corresponds to a readout using a third reference cell 118 biased at a third reference value V _LOWER and is compared using a third comparator 154. Referring again to FIG. 3, as an important step, in step 85 any cells whose third read state does not match the first read state are flagged as weak, low state cells. Referring back to the embodiment of FIG. 4, a comparison of cell state 3 158 read and cell state 1 142 read is generated, and if cell state 3 is not equal to cell state 1 for the selected cell 106, This may result in cell 106 being programmed to a "bottom" state. Additionally, cell 106 may result in being weakly programmed only in the "bottom" state. In other words, if the first read comparator 142 indicates that the cell is in an "upper" state, the cell 106 is discharged to the extent that it no longer has to pass the stricter V _LOWER threshold. In accordance with the teachings of the present invention, cell 106 is at risk of failure. Alternatively, if cell state 3 is equal to cell state 1, then cell 106 is in an "upper" state or cell 106 is in a strongly "lower" state, thus there is no risk of failure.

Referring again to FIG. 3, any weak, “up” or weak, “bottom” state cells are refreshed in step 90. That is, by comparing the first, second, and third reads as described above, the method of the present invention can detect specific, weakly programmed bit cells of a nonvolatile array. These weakly programmed cells represent potential bit errors into the memory system. The memory system responds by reprogramming these cells to their present state, ie, "top" or "bottom", so that these cells return to a strongly programmed condition.

Referring now to FIGS. 5 and 6, second and third preferred embodiments of the devices of the present invention are shown. Each of these embodiments shows a flash memory device including three read comparators as described above along the microprocessor device. With particular reference to FIG. 5, a second embodiment shows a flash memory 200 and a microprocessor 232. Flash memory 200 includes a nonvolatile memory array 204 and a read section that also includes a general comparator 212, an upper comparator 208, and a lower comparator 216. According to an additional important feature, means 220 for selecting and providing a particular read channel to flash memory output 224 is shown. The signal 228 from the microprocessor is any one of the normal, upper, and lower threshold data reads, such as the data read value 224 as one byte (8 bits) or one word (16 bits) based to be input to the microprocessor 232. Used to select

Microprocessor device 232 generally reads data values via data read channel 224 using generic threshold comparator 212. The entire section, or block, of memory array 204 will thus be transferred to microprocessor device 232 and then stored in a secondary memory structure such as RAM. Microprocessor device 232 may then enter a test mode in which comparator control signal 228 selects an upper reference comparator or a lower reference comparator. For example, a section of memory array 204 can be read using upper threshold reference comparator 208. The microprocessor device may then compare the upper threshold data reads with normal threshold data reads stored in RAM. Microprocessor device 232 may then flag any bits that do not agree as "weak" bits where normal and upper threshold reads should be refreshed. Microprocessor device 232 may then refresh these bit positions by writing these positions via data write line 226.

Similarly, microprocessor device 232 may enter a test mode in which comparator control signal 228 selects lower REF 216, which is a lower reference comparator. The microprocessor device may then compare the lower threshold data reads with normal threshold data reads stored in RAM. The microprocessor device 232 may flag any bit that does not agree as a "weak" bit where the normal and upper threshold reads should be refreshed. Microprocessor device 232 may then refresh these bit positions by writing these positions via data write line 226.

Referring again to FIG. 6, a third preferred embodiment of the device of the present invention is shown. In this embodiment, the flash memory device 300 includes a memory array 304 and read means that also includes a general threshold comparator 312, an upper threshold comparator 308, and a lower threshold comparator 316. In this embodiment, each of the threshold comparators 308, 312, and 316 are from flash memory device 300 of all read operations over the upper read 320, normal read 324, and lower read 328 buses. Output. Thus, it is possible to continuously monitor incoming read data for "weak" data bits for the microprocessor device 332. As a preferred approach, all bits of the incoming data byte / word on the top read 320, normal read 324, and bottom read 328 lines detect and correct weak bits as shown in Table 1 below. Filtered by the microprocessor device 332 using a voting scheme for The data bits are detected as "weak" and then these bits are refreshed by the microprocessor device 332 using the data write bus 326.

Upper threshold General threshold Lower critical Vote value low low low low low low Hi Low, refresh required low Hi Hi High, refresh required Hi Hi Hi Hi

Table 1. Voting scheme for detecting and correcting weak bits.

Referring now to FIG. 7, a fourth embodiment of the present invention is shown. In the foregoing embodiments, the nonvolatile memory cells are programmed to binary levels of '0' or '1'. The invention can be extended to non-volatile memories that are programmable in multiple levels. For example, a cell can be programmed at any three levels. In this case, the cell can be values 0, 1, or 2. Another range of ideas is shown in FIG. 7. The selected cell 404 can be programmed to any of four levels (0, 1, 2, or 3). To read this cell 404, three comparators CN1 467, CN2 464, and CN3 461 are required. Six additional comparators CL1 468, CU1 466, CL2 465, CU2 463, CL3 462, and CU3 460 are performed to perform new detection and calibration of the weakly programmed cell. need.

The selected cell 404 is biased by the wordline signal WL 408 to produce a cell current I _CELL . Reference currents are generated in nine reference cells REF1-REF9 450-458. Each reference cell is biased with a specific gate bias as shown. In particular, level 1 bias (V _LEVEL1 ) 440 is used to generate an I _LEVEL1 current. I _LEVEL1 is compared to I _CELL by a general level comparator for level 1 CN1 467. The cell state level1 signal corresponds to the level1 state and also corresponds to the first read described in the first embodiment. The upper margin of the level 1 state is measured using the upper comparator for level 1 CU1 466. The upper reference for level 1 V _UPPER1 436 biases cell _REF7 to produce I _UPPER1 . I _UPPER1 is used to measure the Level 1 upper margin which corresponds to the signal cell state level 1 upper margin 476 and also corresponds to the second readout of the first embodiment. The third readout of the first embodiment corresponds to cell state level1 lower margin 478. V _LOWER1 signal 446 is used to generate the I _LOWER1 current of _REF9 458.

Levels 1, 2, and 3 require three comparators to perform state detection and weak programming state detection, respectively. Level 1 uses CL1 468, CN1 467, and CU1 466. Level 2 includes CL2 465, CN2 464, and CU2 463 to generate cell state Level 2 lower margin 475, cell state Level 2 474, and cell state Level 2 upper margin 473. Use Level 3 includes CL3 462, CN3 461, and CU3 460 to generate cell state level 3 lower margin 472, cell state level 3 471, and cell state level 3 upper margin 470. Use Level 0 does not require additional comparators. In general, a programmable cell requires three comparators for each programming level except the '0' level. More generally, 3 x (n-1) comparators are needed for n-level cells.

The advantages of the present invention are now summarized. An efficient and highly productive integrated circuit device is achieved. A method is provided for detecting and correcting weak cell states of a nonvolatile memory device. Bit errors are prevented in the nonvolatile memory device. An efficient method for selectively refreshing memory cells in a nonvolatile memory device is achieved. A method for continuously detecting weak cell states in non-volatile memory devices is achieved. The present invention is scalable to multi-level memory devices. A nonvolatile memory device is provided that can detect weak cell states.

As shown in the preferred embodiments, the novel methods and devices of the present invention provide an efficient and productive method and device unlike the prior art.

While the invention has been particularly shown and described with reference to its preferred embodiments, it will be understood by those skilled in the art that changes may be made in various forms and details without departing from the spirit and scope of the invention.

Claims (30)

A method for detecting and calibrating a weakly programmed cell of a nonvolatile memory device, the method comprising: Providing a plurality of nonvolatile memory cells; Providing means for reading the selected cell by comparing the performance of the selected cell with the performance of the reference cell, wherein the read state of the selected cell is high when the selected cell exceeds the reference cell; The providing state of the selected cell is low when the selected cell is less than the reference cell; Biasing the reference cell to a first value to obtain a first read state by reading the selected cell; Biasing the reference cell to a second value greater than the first value to obtain a second read state by reading the selected cell; Flagging the selected cell weakly programmed, high when the first and second read states do not match; Biasing the reference cell to a third value less than the first value to obtain a third read state by reading the selected cell; Flagging the selected cell low programmed, low when the first and third read states do not match; Refreshing the selected cell when the selected cell is weakly programmed. The method of claim 1, The step of obtaining the first read state is always performed and all other said steps are performed only in the test mode. The method of claim 2, Wherein the test mode is controlled by a microprocessor device. The method of claim 1, Flagging the selected cell weakly programmed when the first and second read states do not match, and weakly programmed the selected cell when the first and third read states do not match, Flagging low is performed by a microprocessor device. The method of claim 1, Each of the nonvolatile memory cells can store more than two memory states, the steps of obtaining first, second, and third read states, the weakly programmed, flagging the selected cell high, and Flagging the selected cell as a weakly programmed, low row is performed for more than two respective memory states. The method of claim 1, Storing the first read state of the selected cell in a separate memory device prior to obtaining the second read state. The method of claim 1, Determining the filtered read state of the selected cell by a majority vote of the first, second, and third read states. The method of claim 7, wherein And determining the filtered read state of the selected cell by the majority of the first, second, and third read states is performed by a microprocessor device. The method of claim 7, wherein Wherein each of the nonvolatile memory cells can store more than two memory states, and wherein determining the filtered read state is repeated for more than two respective memory states. The method of claim 1, The means for reading the selected cell is: A first said reference cell having a gate set to said first value; A first comparator coupled to the reference cell and the selected cell, wherein the first read state is the output of the first comparator; A second said reference cell having said gate set to said second value; A second comparator coupled to the reference cell and the selected cell, wherein the second read state is the output of the second comparator; A third said reference cell having said gate set to said third value; A third comparator coupled to the reference cell and the selected cell, wherein the third read state is by a circuit comprising the third comparator, the output of the third comparator. The method of claim 1, Wherein the first, second, and third read states are selectively output from the nonvolatile memory device to the microprocessor device during a read operation based on a signal from a microprocessor device. The method of claim 1, Wherein the first, second, and third read states are always output from the nonvolatile memory device to a microprocessor device during a read operation. In a nonvolatile memory device: A plurality of nonvolatile memory cells; Means for determining the read state of the selected cell by comparing the capabilities of the selected cell and the reference cell, wherein the reference cell has a gate biased with a read value, wherein the read state of the selected cell is determined by the selected cell being the reference; Includes said determining means, high when exceeding a cell, said read state of said selected cell being low when said selected cell is less than said reference cell, A first said reference cell having said gate set to said first value; A first comparator coupled to the reference cell and the selected cell, wherein the first read state is the output of the first comparator; A second said reference cell having said gate set to said second value; A second comparator coupled to the reference cell and the selected cell, wherein the second read state is the output of the second comparator; A third said reference cell having said gate set to said third value; A third comparator coupled to the reference cell and the selected cell, wherein the third read state is the output of the third comparator; And a microprocessor device capable of flagging any of the cells for which the second read state does not match the first read state as a weakly programmed high. The method of claim 13, Wherein the nonvolatile memory cells can each store more than two memory states, and means for determining the read state is included for more than two respective memory states. The method of claim 13, Means for selectively outputting the first, second, and third read states from the nonvolatile memory device to the microprocessor device during a read operation based on an external signal from a microprocessor device. Memory device. The method of claim 13, And the first, second, and third read states are always output from the nonvolatile memory device to a microprocessor device during a read operation. (delete) (delete) The method of claim 13, And the microprocessor device may flag any of the cells as the weakly programmed row in which the third read state does not match the first read state. The method of claim 13, And the microprocessor device is capable of storing the first read states of the cells in a separate memory device. The method of claim 13, And the microprocessor device is capable of determining the filtered read state of any of the selected cells by a majority of the first, second, and third read states. The method of claim 21, Wherein the nonvolatile memory cells can each store more than two memory states, and the majority vote is performed for more than two respective memory states. In a circuit device: A nonvolatile memory device, A plurality of nonvolatile memory cells; Means for determining the read state of the selected cell by comparing the capabilities of the selected cell and the reference cell, wherein the reference cell has a gate biased with a read value, wherein the read state of the selected cell is determined by the selected cell being the reference; And said determining means, high when exceeding a cell, said read state of said selected cell being low when said selected cell is less than said reference, and further comprising: A first said reference cell having said gate set to said first value; A first comparator coupled to the reference cell and the selected cell, wherein the first read state is the output of the first comparator; A second said reference cell having said gate set to said second value; A second comparator coupled to the reference cell and the selected cell, wherein the second read state is the output of the second comparator; A third said reference cell having said gate set to said third value; A third comparator coupled to the reference cell and the selected cell, wherein the third read state comprises the third comparator, the output of the third comparator; And A microprocessor device capable of flagging any of the selected cells, the microprocessor device being capable of flagging any of the cells for which the second read state does not match the first read state as a weakly programmed high and the third read state. And the microprocessor device may flag any of the cells that do not match the first read state as a weakly programmed row. The method of claim 23, And the nonvolatile memory cells can each store more than two memory states, and means for determining the read state is included for more than two respective memory states. The method of claim 23, Means for selectively outputting the first, second, and third read states from the nonvolatile memory device to a microprocessor device during a read operation based on a signal from the microprocessor device. The method of claim 23, Wherein the first, second, and third read states are always output from the nonvolatile memory device to the microprocessor device during a read operation. The method of claim 23, And a separate memory device coupled to the microprocessor device. 24. The circuit device of claim 23, wherein the microprocessor device is capable of comparing the second and third read states with data stored in the separate memory device. The method of claim 23, And the microprocessor device is capable of determining the filtered read state of any of the selected cell by a majority of the first, second, and third read states. The method of claim 21, Wherein the nonvolatile memory cells can each store more than two memory states, and additional majority majority is performed for each of the more than two respective memory states.

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