KR100342526B1 - Apparatus for encrypting and decrypting data - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to an apparatus for performing encryption and decryption.

I. The technical problem to be solved by the invention

According to the DES standard, a hardware device capable of processing encryption and decryption in real time is provided.

All. Summary of Solution of the Invention

An apparatus of the present invention is an apparatus for performing encryption and decryption, comprising: a CPU interface unit connected to a central processing unit, a decoder for decoding and outputting a key value received through the CPU interface unit, and an output of the decoder. A memory unit for outputting data of a set code by checking a user, an input / output buffer for transmitting / receiving data between the CPU interface unit, and an engine unit performing an encryption and decryption process, data received from the input / output buffer, and a code of the memory unit An engine controller that performs encryption and decryption according to a value, an interrupt controller that detects and outputs a state of the engine unit, and a state register that outputs a state to a central processing unit through the CPU interface unit according to the output of the interrupt controller. Characterized in that configured.

la. Important uses of the invention

Used for all systems that perform encryption and decryption.

Description

Encryption and decryption device {APPARATUS FOR ENCRYPTING AND DECRYPTING DATA}

The present invention relates to an encryption and decryption apparatus, and more particularly, to a decryption apparatus of DES (Data Encryption Standard) which is a standard algorithm for encrypting and decrypting.

In general, encryption and decryption are one technical method used to securely transmit personal information as information communication advances. Such encryption and decryption methods are widely used to protect user's identity user information in electronic commerce and the like, and as user demand for information communication increases, more user information is moved to data communication using a communication network. If you send your company's confidential information or personal information directly in plain text without going through such encryption and decryption, these data will be exposed to the outside, and your personal information will be protected. Therefore, companies that perform most data communications or companies with communication servers with multiple subscribers are required to perform encryption and decryption operations during data communications.

Such encryption and decryption is generally performed in accordance with the standard of the standard (hereinafter referred to as DES) standardized and used in the United States to perform encryption and decryption. According to the DES standard, encryption and decryption are performed in a central processing unit (CPU) of a communication system and are performed by executing a program that satisfies this standard. In addition, since the DES standard is configured to encrypt and decrypt the same algorithm 16 times, there is a problem that it takes a lot of time to perform such a task with a program.

It takes a long time to generate and decrypt a single ciphertext. That is, even if the data is transmitted or received in real time, since the encryption and decryption process is performed by the program, a lot of time is required during processing. In addition, even if the transmission and reception of the data is made in real time, there is a problem that the user does not recognize that the data is actually transmitted and received in real time due to the time delay of encryption and decryption. Also, in general, it is difficult to perform encryption on a personal computer, so there are often servers that generate and process cipher text. In this case, since the server processes encryption and decryption by a program, it takes a long time to encrypt and decrypt, which causes a problem that the processing speed of other tasks is very low.

Accordingly, an object of the present invention is to provide an apparatus for performing encryption and decryption at a high speed.

Another object of the present invention is to provide an apparatus that satisfies the DES algorithm and performs encryption and decryption.

The apparatus of the present invention for achieving the above objects is a device for performing encryption and decryption, the CPU interface unit and the key value and data received through the CPU interface unit A decoder which decodes and outputs a memory, a memory unit which outputs data of a set code by identifying a user by an output of the decoder, an input / output buffer which transmits and receives data between the CPI interface unit and an engine unit which performs an encryption and decryption process; An engine unit that performs encryption and decryption according to data received from the input / output buffer and a code value of the memory unit, an interrupt controller that detects and outputs a state of the engine unit, and the CPI interface unit according to an output of the interrupt controller. Status registers that output status to the central processing unit Characterized by configured.

1 is a block diagram of an apparatus for performing encryption and decryption according to a preferred embodiment of the present invention;

FIG. 2 is a detailed block diagram showing an example of the decoder 12 shown in FIG.

3 is a detailed block diagram of an input buffer in the structure of the input / output buffer of FIG. 1;

4 is a detailed block diagram of an output buffer in the structure of the input / output buffer of FIG. 1;

FIG. 5 is a block diagram illustrating an initial replacement process of the DES engine of FIG. 1. FIG.

6 is a detailed block diagram of a DES engine;

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for performing encryption and decryption according to a preferred embodiment of the present invention. Hereinafter, a configuration and an operation of an apparatus for performing each encryption and decryption will be described in detail with reference to FIG. 1.

The processor connection unit 10 includes a CPU interface unit 11, a decoder 12, an input / output buffer 13, and a state register 14. First, the CPU interface unit 11 is connected to a CPU (central processing unit) and performs an interface for receiving a control signal, data to be encrypted, and transferring data to be decrypted to the CPU. In addition, the CPU interface unit 11 includes a signal latch and a driver therein. The signal latch latches an input signal and transfers the signal to the input / output buffer 13, and the driver drives data transmitted and received between the CUP and the input / output buffer 13. The decoder 12 decodes the input data according to the key signal received from the CPU interface unit 11 and outputs the decoded data to the memory unit 30. At this time, the key signal is a key signal input by the user. The key signal input by the user is a code value for selecting a password and a code for encryption and decryption. The decoder 12 includes a memory having a predetermined size and a register. In addition, the input / output buffer 13 is composed of a memory of First In First Out (FIFO). The input / output buffer 13 receives and stores the data to be encrypted or the data to be decrypted received from the CPU interface unit 11 and outputs the data according to the input order. In addition, the input / output buffer 13 has a structure for receiving data received in 64-bit in parallel and outputting in parallel. Therefore, the input / output buffer 13 performs an interface of data to be encrypted and decrypted between the CPU interface unit 11 and the DES engine unit 40. The state register 14 receives a control signal and a state signal to inform the state between the CPU interface unit 11 and the DES engine unit 40. The interrupt controller 20 receives a status signal of the DES engine unit 40, generates a signal corresponding to encryption, encryption termination, decryption, or decryption termination, and outputs the signal to the state register 14.

The memory unit 30 is composed of a key memory 31 and a code memory 32. The key memory 31 has a key value for each user, that is, stores a password. In addition, the code memory 32 has a plurality of code values, selects a code to encrypt or decrypt according to the key value received from the decoder 12, and enables the selected code. The code enabled in the code memory 32 is input to the DES engine unit 40. The DES engine unit 40 is composed of a state output unit 41, a DES engine 42, and a key moving memory 43. First, the state output unit 41 inspects the state of the engine and outputs a state according to the result of the inspection. That is, the state output unit 41 checks the states of the DES engine 42 during encryption, decryption, encryption termination, and decryption termination, and outputs the corresponding state to the interrupt controller 20. The DES engine 42 encrypts and decrypts the data received from the input / output buffer 13 according to the code value received from the code memory 42. That is, the encryption and decryption methods are encrypted or decrypted in different ways according to the code received from the code memory 32. The key shift memory 43 has a shift table for shifting the received data to the right or the left, and is shown as a table according to the DES standard.

En / De q1 q2 q3 q4 c0 c1 c3 c4 out One 0 0 0 0 0 0 0 0 One One 0 0 0 One 0 0 0 One One One 0 0 0 One 0 0 One 0 2 One 0 0 0 One 0 0 One One 2 One 0 0 0 One 0 One 0 0 2 One 0 0 0 One 0 One 0 One 2 One 0 0 0 0 0 One One 0 2

As shown in Table 1, the value of the key shift memory 43 is read and the received data is shifted left or right and used for encryption and decryption. The block configuration of FIG. 1 described above is configured as a gate array (FPGA) device that is programmable to solve the problem that the processing speed is reduced due to an increase in the load of the system because the program is processed as a problem mentioned in the related art. can do.

2 is a detailed block diagram illustrating an example of the decoder 12 illustrated in FIG. 1. Hereinafter, the configuration and operation of the decoder 12 will be described in detail with reference to FIG. 2.

The decoder 101 receives three bits of data A0 to A2, a CS signal, and a reset signal RESET. Therefore, the decoder 101 stores the received data, the signal output according to the CS signal, and the reset signal, in the control register 102 and the state register 103, and the input buffer counter 104 is 4 to 00-11. It is configured to accept bits. The output buffer counter 105 also has the same configuration as the input buffer counter 104. The value decoded by the decoder 101 is output to the memory unit 30 through the data port 106. That is, when data is input to the decoder 101, the input command value is stored in the control register 102, and the state value of the decoder is stored in the state register 103. The input buffer counter 104 counters the input data, and the output buffer counter 105 counters the data that has been processed and outputted by the decoder 101. That is, since the input data and the output data must be the same, the state of the input data and the output data can be checked with the buffer value accordingly.

3 is a detailed block diagram illustrating an input buffer in the structure of the input / output buffer of FIG. 1. Hereinafter, the configuration and operation of the input buffer will be described in detail with reference to FIG. 3.

The data received from the CPU interface unit 11 by 64 bits is sequentially stored in the FIFO 110 in accordance with the address indicated by the write pointer 111. The data is read from the FIFO 110 according to the address indicated by the read pointer 113 and input to the four operators 115a, 115b, 115c, and 115d which are exclusively divided. That is, the input data is input to the exclusive OR operators 115a, 115b, 115c, and 115d by 16 bits, respectively. On the other hand, the code buffer 114 receives data from the code memory 32 and inputs it to each of the calculators 115a, 115b, 115c, and 115d. Each of the operators 115a, 115b, 115c, and 115d outputs the data received from the code buffer 114 and the data received from the FIFO 110 to the input register 116. The input register 116 is composed of a left register 116a and a right register 116b, and the left register 116a receives and stores the data input by the exclusive truncation from two operators 115a and 115b. The right register 116b receives and stores data input from the other two calculators 115c and 115d. Through this process, a process for encrypting data input from the CPU interface unit 11 into the input / output buffer is performed. As such, the data stored in each of the buffers 124a and 124b is input to the DES engine unit 40. In addition, the read / write controller 112 examines the state of the FIFO 110 to output a full and empty signals, receives a read and write signal R / W, and writes an address accordingly. Output to 111 or output to read pointer 113.

4 is a detailed block diagram illustrating an output buffer in the structure of the input / output buffer of FIG. 1. Hereinafter, the configuration and operation of the output buffer will be described in detail with reference to FIG. 4.

After the engine unit 30 ends 16 repetitive operations, the decoded data is stored in registers 124a and 124b composed of two parts. The decoded data stored in each part of the register 124 is stored in the FIFO 120 for output. The FIFO 120 has a structure capable of storing a plurality of columns of data having rows of 64 bits each. The read / write controller 122 writes data at an address indicated by the write pointer 121. At this time, the right register 124a stores data from 0 to 31 bits of the 64 bits of the FIFO 120, and the left register 124b stores data from 32 to 63 bits of the FIFO 120. In addition, under the control of the read / write pointer 122, the read pointer 123 indicates an address of data to be output, and the data of the indicated address is output to the CPU interface unit 11. In addition, the read / write controller 112 examines the state of the FIFO 110 and outputs a full and empty signals, receives the read and write signals R / W, and records the address accordingly. The output is performed by the pointer 121 or the read pointer 123.

5 is a block diagram of a part of a DES engine for explaining an initial replacement process of the DES engine. Hereinafter, an initial substitution process of the DES engine will be described in detail with reference to FIG. 5.

The FIFO 130 storing 64-bit data outputs data by 16 bits to the exclusive ora calculators 133a, 133b, 133c, and 133d. In addition, the mode signal EBC / CBC is input to the AND gate 131, and the other input terminal of the AND gate 131 is connected to the output terminal of the code buffer 132. The code buffer 132 outputs data according to the step to the AND gate 131. The AND gate 131 combines the two signals and inputs them to each exclusive OR operator 133a, 133b, 133c, and 133d. That is, the code buffer 132 outputs a code value corresponding to the current step. This code value becomes the code value of your choice. The code value is ORed with the mode signal. The mode signal is a signal according to encryption or decryption. The logical sum is thus delivered to each exclusive OR operator 133a, 133b, 133c, and 133d. Therefore, when the output value of the AND gate 131 is "0", the output of each of the exclusive OR calculators 133a, 133b, 133c, and 133d is not affected. The output of the exclusive ora operation is input to the multiplexer 134 to each of the exclusive ora calculators 133a, 133b, 133c, and 133d. Therefore, the multiplexer 134 receives and multiplexes the exclusive data together with the value of the previous step. Accordingly, the multiplexed data is stored in the register 135. The register 135 is composed of a left register 135a and a right register 135b, each composed of 32 bits.

6 is a detailed block diagram of a DES engine. Hereinafter, the block configuration and operation of the DES engine will be described in detail with reference to FIG. 6.

Data output from the output memory portion 200 of the input / output buffer 13 is connected to one input terminal of four exclusive OR calculators 215a, 215b, 215c, and 215d, and the mode signal 201 and the code buffer An output terminal of the AND gate 203 for ORing and outputting the data of 204 is connected to the other input terminal of each of the exclusive OR operators 215a, 215b, 215c, and 215d. Accordingly, each of the exclusive ora calculators 215a, 215b, 215c, and 215d performs an exclusive oar on the input signal, and then multiplexes it again in the multiplexer 216, and then the left register 217 and the right register 218 Enter each as The right register 218 and the left register 217 combine the input data with the stored data and output the same to the second operator 224. In addition, the right register 218 is extended by the expansion substituent 219 and is input to the first operator 220.

Meanwhile, 56 bits of data output from the key memory 206 are separated into 28 bits and input to the left buffer 207 and the right buffer 208. Output data of the respective buffers 207 and 208 is input to the movers 210 and 211, respectively. Each of the mobile devices 210 and 211 moves and outputs the output signal of the key memory 205 to each of the buffers 212 and 213 according to a shift value input from the key shift memory. The data stored in each of the buffers 212 is selectively substituted by only 48 bits in the substitution selector 214 and output to the first operator. The first operator 220 then outputs the 48-bit data input from the expansion substituent 219 and the 47-bit data input from the substitution selector 214 by using an exclusive or output. The data thus output is stored in the comparison buffer 221 by 6 bits, and is demodulated using the code memory 222 input and selected by the key value input by the user. The decoded data is primarily stored in the buffer 223, and the data stored in the buffer 223 is input to the second operator 224. Accordingly, the second operator 224 inputs exclusively 32 bits of data into the step buffer (step (i-1)) 202.

The encryption and decryption operations according to the above configuration will be described in more detail.

The device performing initial encryption and decryption remains in a standby state. At this time, when data to be encrypted and decrypted is received through the CPU interface unit 11, the engine unit 40 reads a key value from the memory unit 30 through the decoder 12. The key value is input in advance through the CPU interlace section 11 to become a value held by the key memory 31 and the code memory 32. After that, the data received in 64 bits is extracted as fixed bits of 32 bits. After performing the exclusive OR operation, the code is read from the code memory 32 of the memory unit 30. The memory address is extracted from the read code, and data stored in the input / output buffer 13 is read. Then, the read data is shifted to the right or left by the value set in the key shift memory 43. Thereafter, the value of Ri is stored in Li, and the procedure proceeds to step 318 where the counter value CT is incremented by one and stored. Then check whether the incremented counter value is 15. In this case, 15 is a case in which 16 times of encryption or decryption are performed from 0 to 15 by repeating 16 times when performing DES encryption and decryption. If the counter value is 15, it is stored in the input / output buffer 13. Then, the data stored in the input / output buffer 13 is output to the CPU through the CPU interface unit 11. However, if the counter value is less than 15, 16 operations are performed starting again from the fixed extraction process. The devices of the block diagram described above may be configured in a circuit or otherwise processed through a program. This can be achieved with the FPGA.

As described above, by using a gate array in which an apparatus for performing encryption and decryption is programmable, a load on the CPU for performing encryption and decryption is reduced, and there is an advantage that encryption and encryption can be performed in near real time.

Claims (3)

An apparatus for performing encryption and decryption, CPU interface unit connected to the central processing unit, A decoder for decoding the key value received through the CPI interface unit and decoding and outputting data; A memory unit for identifying a user by the output of the decoder and outputting data of a set code; An input / output buffer for transmitting and receiving data between the engine unit performing an encryption and decryption process with the CPI interface unit; An engine unit for performing encryption and decryption according to data received from the input / output buffer and code values of the memory unit; An interrupt controller for detecting and outputting a state of the engine unit; And a state register configured to output a state to the central processing unit through the CPI interface unit according to the output of the interrupt controller. The method of claim 1, wherein the memory, An encryption and decryption device comprising a key memory storing a key value and a code memory for selecting a code value. delete