JPWO2001003186A1 - Semiconductor device, manufacturing method thereof, and semiconductor device mounting structure - Google Patents

Abstract

(57) [Abstract] A semiconductor chip (8) is provided with a tab (5) supporting the semiconductor chip (8), a sealing portion (12) formed by sealing the semiconductor chip (8) with resin, a tab suspension lead (4) supporting the tab (5), a plurality of leads (2) each having a connected portion exposed on the periphery of the rear surface of the sealing portion (12) and a thin portion formed at the end on the tab side that is thinner than the connected portion, and having an inner groove (2e) and an outer groove (2f) on a wire bonding surface (2d) arranged within the sealing portion (12) of the connected portion, and wires (10) connecting pads (7) of the semiconductor chip (8) and the leads (2), the thin portion of the leads (2) is covered with sealing resin, and the wires (10) are bonded to the connected portion between the outer groove (2f) and the inner groove (2e), and the thin portion of the leads (2), the outer groove (2f), and the inner groove (2e) prevent the leads from falling off.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to semiconductor manufacturing technology, and in particular to technology that is effective in applying to miniaturization, thinning, cost reduction, and reliability improvement. BACKGROUND ART The technology described below was investigated by the inventor when researching and completing the present invention, and is summarized as follows: The market for electronic devices that are becoming smaller and lighter is growing rapidly. Under these circumstances, improving LSI mounting technology, i.e., developing packaging technology that allows high-density mounting, has become an important issue in the field of such small electronic devices. Furthermore, as the market continues to grow, there is a demand for improved productivity and reduced manufacturing costs. As a first technology that can address these technical issues, JP 5-129473 A (2003) discloses a method for manufacturing semiconductor devices that uses a semiconductor manufacturing system.
29, this technology uses a lead frame 35 in which internally derived leads 33 and tabs 34 are on the same plane, and the internally derived leads 33 are electrically connected to a semiconductor chip 36 by bonding wires 37.
This is a resin-sealed surface-mount semiconductor device characterized in that the underside of the tab 34 functions as an external electrode that electrically connects the semiconductor device to the outside. However, in the first technique shown in Figure 29, the mounting substrate side of the tab 34 is exposed from the underside of the semiconductor device, so when the semiconductor device is mounted on the mounting substrate, there is a possibility that the tab 34 will come into contact with wiring on the mounting substrate, making it impossible to form wiring on the corresponding portion of the mounting substrate, thereby reducing the flexibility of board design. Furthermore, because only one side of the tab 34 is sealed with the sealing material 38, the contact area between the tab 34 and the sealing material 38 is reduced, resulting in a loss of adhesion and a decrease in the reliability of the semiconductor device. A second technique is disclosed in Japanese Patent Laid-Open Publication No. 10-189830. 30 , this technology is a resin-sealed semiconductor device comprising a semiconductor element 42 mounted on a tab 41 supported by suspension leads 40 of a lead frame 39, thin metal wires 45 electrically connecting electrodes 43 on the upper surface of the semiconductor element 42 to inner lead portions 44, a sealing resin 46 sealing the outer peripheral region of the semiconductor element 42 including the thin metal wire region on the upper surface of the semiconductor element 42, and external terminals 47 arranged in the bottom region of the sealing resin 46 and connected to the inner lead portions 44, wherein the suspension leads 40 are upset and have a step portion 48, and the sealing resin 46 is also formed below the tab 41 with a thickness equivalent to the upset. In this second technology, since the suspension leads 40 of the lead frame 39 are upset and have a step portion 48, the sealing resin 46 can be present below the tab 41 as well, and the semiconductor device is essentially double-sided sealed with respect to the lead frame 39, and has the advantage of improved reliability compared to the first technology. Furthermore, since the mounting substrate side of the tab 41 is not exposed from the underside of the semiconductor device, when the semiconductor device is mounted on the mounting substrate, the tab 41 does not come into contact with the wiring on the mounting substrate, which has the advantage of allowing for greater freedom in the design of the mounting substrate. Another example of a semiconductor device with an upset tab (tab-raising process) is disclosed in Japanese Patent Laid-Open Publication No. 11-74440. However, the first technique has a structure in which only one side of the tab is sealed with a sealing material to improve thinning, which reduces the contact area between the sealing material and the tab, thereby impairing adhesion and reducing the reliability of the semiconductor device. The second technique and the technique described in Japanese Patent Laid-Open Publication No. 11-74440 are double-sided sealed semiconductor devices with respect to the lead frame, which has the advantage of improving reliability compared to the first technique. However, since the step portion is formed by the upset process, there are problems such as not being able to improve the thinning of the semiconductor device as much as the first technique, and tab location issues that arise during the upset process. That is, the inventors have found that the first and second conventional technologies have not succeeded in achieving both thinness and improved reliability. An object of the present invention is to provide a semiconductor device, a manufacturing method thereof, and a semiconductor device mounting structure that can achieve both thinness and high reliability. Another object of the present invention is to provide a semiconductor device, a manufacturing method thereof, and a semiconductor device mounting structure that can improve productivity and reduce manufacturing costs. Another object of the present invention is to provide a semiconductor device, a manufacturing method thereof, and a semiconductor device mounting structure that prevent short circuits and lead detachment during mounting. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings. Disclosure of the Invention Representative inventions disclosed in this application can be briefly outlined as follows. The semiconductor device according to the present invention is a semiconductor device comprising a tab supported by a plurality of suspension leads, a plurality of leads arranged so as to surround the periphery of the tab, a semiconductor chip mounted on one main surface of the tab and electrically connected to one main surface of the plurality of leads, and a sealing resin that seals the plurality of leads, the semiconductor chip, and the tab, wherein the other main surface of the plurality of leads opposite to the one main surface is exposed from the sealing resin, and further, the thickness of the tab is formed smaller than the thickness of the plurality of leads. In addition, the method for manufacturing a semiconductor device of the present invention includes the steps of preparing a matrix lead frame having a plurality of lead frames each consisting of a plurality of leads, a tab formed thinner than the plurality of leads, and a suspension lead supporting the tab; a die bonding step of mounting a semiconductor chip on the tab of the lead frame; a wire bonding step of connecting the semiconductor chip and the plurality of leads of the lead frame with wires; a resin sealing step of sealing the lead frame, the semiconductor chip, and the wires with sealing resin so that the undersides of the plurality of leads are exposed; and a cutting step of obtaining a plurality of semiconductor devices by cutting the matrix lead frame into a plurality of unit lead portions near the sealing area sealed in the resin sealing step. Furthermore, the mounting structure of the semiconductor device of the present invention is a semiconductor device comprising a tab supported by wiring on a mounting board and a plurality of suspension leads, a plurality of leads arranged to surround the periphery of the tab, a semiconductor chip mounted on one main surface of the tab and electrically connected to one main surface of the plurality of leads, and a sealing resin that seals the plurality of leads, the semiconductor chip, and the tab, wherein other main surfaces of the plurality of leads opposite to the one main surface are exposed from the sealing resin, and further, the thickness of the tab is formed smaller than the thickness of the plurality of leads, and the other main surfaces of the leads of the semiconductor device are connected with a bonding material. The semiconductor device of the present invention includes a tab supporting a semiconductor chip, a sealing portion formed by sealing the semiconductor chip with resin, a support portion supporting the tab and an exposed portion connected to the support portion and exposed on the semiconductor device mounting surface of the sealing portion, a plurality of tab hanging leads each having a thinner support portion than the exposed portion, a plurality of leads arranged around the tab and exposed on the semiconductor device mounting surface of the sealing portion, and a connecting member connecting the surface electrodes of the semiconductor chip to the corresponding leads, and the plurality of tab hanging leads are connected via the tab. According to the present invention, the tab supporting portion of the tab hanging lead is formed thin, so that the supporting portion can be covered with sealing resin and embedded in the sealing portion, thereby achieving a structure in which the exposed portion of the tab hanging lead is exposed only at the end of a corner on the back surface of the sealing portion. As a result, a large clearance can be formed between the exposed portion of the tab hanging lead and the adjacent lead on the back surface of the sealing portion, and because the tab is embedded in the sealing portion, short circuits can be prevented when the semiconductor device is mounted on a mounting board or the like. Furthermore, the semiconductor device of the present invention includes a tab that supports a semiconductor chip and is smaller than the semiconductor chip, a sealing portion formed by sealing the semiconductor chip with resin, a tab suspension lead that supports the tab, a plurality of leads arranged around the tab and exposed on the surface of the sealing portion on the semiconductor device mounting side, and a connecting member that connects the surface electrodes of the semiconductor chip to the corresponding leads, and the tab and the semiconductor chip are bonded at a location inside the surface electrodes of the semiconductor chip. According to the present invention, the bonding stage can support the vicinity of the edge of the back surface of the semiconductor chip during wire bonding. This allows appropriate ultrasonic waves and heat to be applied to the bonding wire during wire bonding, resulting in improved reliability and bondability of wire bonding. Furthermore, the manufacturing method of the semiconductor device of the present invention includes a tab that can support a semiconductor chip,
The method includes the steps of: preparing a lead frame having a plurality of tab suspension leads, each of which has a support portion for supporting the tab and an exposed portion connected to the support portion, the support portion being thinner than the exposed portion, and a plurality of leads arranged around the tab; joining the tab to the semiconductor chip; connecting surface electrodes of the semiconductor chip to the corresponding leads with connecting members; applying a sealing resin to the surface of the tab opposite the chip support surface and covering the thin portions of the tab suspension leads with the sealing resin, arranging the plurality of leads and the exposed portions of the tab suspension leads on the surface on which the semiconductor device is mounted, and resin-molding the semiconductor chip to form a sealing portion; and dividing the tab suspension leads at the exposed portions of the tab suspension leads and separating the plurality of leads from the frame of the lead frame. Furthermore, in the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one may incorporate some or all of the modifications, details, or advantages of the other.
The present invention relates to supplementary explanations and the like. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same function are designated by the same reference numerals, and repeated explanations will be omitted. (Embodiment 1) FIG. 1 is an external perspective view of a semiconductor device according to this embodiment 1, FIG. 2 is a plan view (underside) of the semiconductor device, and FIG. 3 is a plan view of a unit lead portion (details of which will be described later) according to this embodiment 1. In FIG. 3, a broken line indicates a sealing region. FIG. 4 is a cross-sectional view of the unit lead portion of FIG. 3 taken along the line A-A, FIG. 5 is a cross-sectional view of the unit lead portion of FIG. 3 taken along the line B-B, FIG. 6 is a partial perspective view of the semiconductor device of FIG. 1, and FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6.
FIG. 1 is a cross-sectional view taken along the line -C, FIG. 8 is a cross-sectional view taken along the line D-D of the semiconductor device of FIG. 6, and FIG. 9 is a cross-sectional view taken along the line E-E of the semiconductor device of FIG. 6. As shown in FIGS. 1 and 2, the semiconductor device 1 of the first embodiment is a surface-mount semiconductor device having a structure in which a portion of the leads 2 is exposed on the peripheral edge of the underside of the semiconductor device as a terminal for external connection. The semiconductor device 1 includes a thin plate made of copper or iron and processed into an arbitrary shape. As shown in FIGS. 3, 4, and 5, the thin plate has a tab (chip support portion) 5 supported (integrally formed with) four suspension leads (hereinafter referred to as tab suspension leads 4) in the center, and a plurality of leads 2 surrounding the tab 5 near the peripheral edge of the tab 5. Hereinafter, this thin plate will be referred to as a unit lead portion 3. The tab suspension leads 4 (excluding the outer ends) and the underside of the tab 5 are etched to a thickness approximately half that of the remaining portion of the unit lead portion 3. This process is generally referred to as half-etching. In this way, the first embodiment
The unit lead portion 3 has a step portion 6 formed by half etching on the lower surface side.
As shown in FIGS. 6, 7 and 8, a microcomputer, an ASIC (Application Specific Integrated Circuit) and the like are mounted on the upper surface (one main surface) of the tab 5 of the unit lead portion 3.
Integrated Circuit), Gate Array, System LSI (Large
A semiconductor chip 8 is formed with predetermined integrated circuits such as a memory and a plurality of pads 7 made of aluminum or the like that serve as external terminals of the integrated circuits, and is fixed with the integrated circuits facing up by an adhesive 9 such as a non-conductive paste or a non-conductive film. Each pad 7 of the semiconductor chip 8 is connected to a conductive wire 1 made of gold, aluminum, or the like.
The semiconductor chip 8, the wire 10, the tab 5, the tab suspension lead 4, the lead 2 (top surface and side surface) are electrically connected to one main surface of the lead 2 via the wire 10.
For the purpose of protection and improvement of moisture resistance, sealing resin such as epoxy resin or silicon resin is used.
1. However, the lower surface (other main surface) of the lead 2 is exposed on the lower surface side of the semiconductor device as a terminal for external connection. Hereinafter, the portion sealed with the sealing resin 11 will be referred to as the sealing portion 12. As shown in FIG. 9, the lead 2 is formed so that the area of the sealed upper surface is larger than the exposed lower surface to prevent the lead 2 from coming off the sealing portion 12. Furthermore, in order to improve moisture resistance and the mountability when the semiconductor device 1 is mounted on a mounting board, the exposed lead 2 from the semiconductor device is subjected to an exterior treatment such as solder plating using Pb-Sn solder. Hereinafter, the thin film formed by the exterior treatment will be referred to as the plated portion 13. The exterior treatment may be plating using Pb-free solder such as Sn-Ag or Sn-Zn solder. By setting the thickness of the plated portion to about 10 μm, the semiconductor device 1 can be formed without the sealing portion 1
2, a standoff of the thickness of the plated portion 13 is ensured from the underside of the tab 5. The plated portion 13 is omitted from FIGS. 2 and 4 for convenience. As described above, the semiconductor device 1 of this embodiment does not have the step portion 6 formed by bending (upset processing) as in the conventional method, but rather by half-etching, whereby the sealing resin 11 is placed. This allows the tab 5 and tab suspension lead 4 to be sealed with the sealing resin 11 while achieving a thin structure. This eliminates the problem of reduced adhesion and impaired reliability due to a reduced contact area between the sealing resin 11 and the tab 5. Furthermore, the lower surfaces of the leads 2 are exposed from the underside of the sealing portion 12 of the semiconductor device 1 and serve as terminals for external connection, preventing lead deformation during transportation, mounting, etc., and improving reliability. Furthermore, because the leads 2 protrude only slightly beyond the side surfaces of the sealing portion 12, the planar dimensions of the semiconductor device 1 can be reduced.
Furthermore, since the area of the sealed upper surface of the lead 2 is larger than the exposed lower surface, sufficient adhesion can be ensured and reliability can be maintained even though the bonding surfaces with the sealing resin 11 are only the upper and side surfaces. Next, an example of a manufacturing method for the semiconductor device 1 of the first embodiment will be described with reference to the cross-sectional flow diagram of FIG. 10 and FIGS. 11 to 21. FIG. 11 is a plan view of a matrix lead frame used in manufacturing the semiconductor device 1 of the first embodiment. FIG. 12 is an enlarged view (top side) of a main portion of a unit lead frame (details of which will be described later) of the matrix lead frame of FIG. 11. FIG. 13 is an enlarged view (bottom side) of a main portion of the unit lead frame of the matrix lead frame of FIG. 11. FIG. 14 is a cross-sectional view taken along the line F-F in FIG. 12. FIG. 15 is a cross-sectional view taken along the line G-G in FIG. 12. The matrix lead frame 14 is formed by patterning a copper-based or iron-based metal plate by etching. As shown in Figure 11, the matrix lead frame 14 has ten regions (hereinafter referred to as unit lead frames 15) each corresponding to one semiconductor device formed at regular intervals, for example, five rows along the long side and two rows along the short side. Each unit lead frame 15 has a slit (hereinafter referred to as a stress relief slit 16) formed around its periphery to relieve stress applied to the matrix lead frame 14 during the manufacturing process, and guide pins 17 used as holding and alignment pins during the manufacturing process formed on its long sides. As shown in Figures 12 and 13, the unit lead frame 15 has a tab 5 supported by four tab suspension leads 4 in its central portion, and multiple leads 2 surrounding the tab 5 near its periphery, supported by a frame. The tab suspension leads 4 (excluding the outer ends) and the underside of the tab 5 are half-etched to have a thickness approximately half that of the rest of the unit lead frame 15. As described above, the unit lead frame 15 of the first embodiment has a step 6 on the lower surface side as shown in Figures 14 and 15. This step 6 is not formed in a separate process after patterning by punching or etching as in the conventional method (hereinafter referred to as post-processing), but is formed by simultaneously performing patterning and half-etching, thereby reducing the manufacturing cost of the matrix lead frame 14.
The matrix lead frame 14 of the first embodiment does not require bending of the matrix lead frame after patterning as in the conventional method, and therefore it is possible to prevent problems such as tab location caused by bending. Next, a manufacturing process using the matrix lead frame 14 shown in Figures 11 to 15 will be described. Figure 16 is a conceptual diagram showing a method of applying adhesive to the tabs, Figure 17 is a conceptual diagram showing a method of mounting a semiconductor chip on the tabs, Figure 18 is a conceptual diagram showing a wire bonding method, Figure 19 is a conceptual diagram showing a state in which the mold and the matrix lead frame are aligned in the resin sealing process, Figure 20 is a conceptual diagram showing a state in which the mold is clamped in the resin sealing process, and Figure 21 is a conceptual diagram showing a state in which the mold is opened in the resin sealing process. First, as shown in Figure 10(a), an adhesive 9 such as a conductive paste, a non-conductive paste, or a non-conductive film is applied to each tab 5 of the matrix lead frame 14.
First, as shown in FIG. 16, adhesive 9 is applied onto each tab 5 using a syringe 18, and then, as shown in FIG. 17, a collet 19 is inserted.
The semiconductor chip 8 is mounted on each tab 5 to which adhesive 9 has been applied by a wire bonding method. Hereinafter, this process will be referred to as the die bonding process. Next, as shown in FIG. 10(b), each pad 7 of the semiconductor chip 8 and its corresponding lead 2 are electrically connected by a conductive wire 10 made of Au or the like. First, as shown in FIG. 18, the matrix lead frame 14 on which the semiconductor chip 8 is mounted is fixed on a bonding stage 20 heated to a high temperature. Next, while fixed, each pad 7 of the semiconductor chip 8 and its corresponding lead 2 of the unit lead frame 15 are electrically connected by a wire 10 made of Au or the like using a capillary 21. Hereinafter, this process will be referred to as the wire bonding process. Next, as shown in FIG. 10(c), the semiconductor chip 8, the wire 10, the tab 5,
The tab hanging leads 4 (not shown) and the top and side areas of the leads 2 are sealed with sealing resin 11 such as epoxy resin or silicone resin by transfer molding. First, as shown in FIG. 19, the matrix lead frame 14 after wire bonding is placed at a predetermined position on the lower mold 22 of a transfer molding machine.
The upper mold 23 and the lower mold 22 are clamped together. A space (hereinafter referred to as a cavity 24) is formed between the mating surfaces of the clamped molds, allowing the semiconductor chip 8, wire 10, tab 5, tab support lead 4 (not shown), and leads 2 (top and side surfaces) to be sealed with sealing resin 11 for each unit lead frame 15. Next, as shown in FIG. 20 , with the molds clamped, sealing resin 11 is filled into each cavity 24 through runners 25 and gates 26, which serve as resin flow paths. The filled sealing resin 11 flows around the stepped portions 6 on the lower surfaces of the half-etched tabs 5 and tab support leads 4 (not shown), reliably hermetically sealing the semiconductor chip 8, wire 10, tab 5, tab support lead 4 (not shown), and leads 2 (top and side surfaces). At this time, the lower surfaces of the leads 2 and the sealing portion 12 are flush with each other, and the lower surfaces of the leads 2 are exposed from the lower surface of the sealing portion 12. Furthermore, it is desirable that the outer ends of the leads 2 protrude from the side of the sealing portion 12 to facilitate cutting in the cutting process. Then, as shown in FIG. 21 , the mold is opened. Hereinafter, this process will be referred to as the resin sealing process. Furthermore, although the above-described resin sealing process employs a transfer molding method, it may also be performed using a sheet molding method in which a heat-resistant sheet is uniformly spread over the surfaces of the upper mold 23 and the lower mold 22 while being sealed with resin. In this case, the leads 2 protrude from the sealing portion 12 by the amount that they sink into the sheet. Next, as shown in FIG. 10(d), an exterior treatment is performed on the leads 2 exposed from the sealing portion 12 to improve moisture resistance and ease of mounting when the semiconductor device is mounted on a mounting board. The exterior treatment is preferably a solder plating process using Pb-Sn solder, but plating with Pb-free solder such as Sn-Ag or Sn-Zn solder may also be used. By setting the thickness of the plating portion 13 to approximately 10 μm, the semiconductor device 1 can be
A standoff equivalent to the thickness of the plated portion 13 is ensured. Hereinafter, this process will be referred to as the packaging process. Next, as shown in FIG. 10(e), the matrix lead frame 14 is cut using a cutting die (not shown) at a position slightly outside each sealing portion 12 to divide it into a plurality of unit lead portions 3 (the portion of the unit lead frame 15 excluding the frame), thereby obtaining the semiconductor device 1 shown in FIG. 1. Hereinafter, this process will be referred to as the cutting process. The semiconductor device 1 manufactured as described above is sorted into good and bad products through a predetermined inspection and shipped. As described above, the above-described manufacturing method does not require bending of the external terminals of the semiconductor device as in the conventional method, thereby reducing the number of processes, facilitating process management and improving productivity. Another advantage is that existing semiconductor manufacturing equipment can be reused for all processes, eliminating the need for new capital investment. While the above-described manufacturing method describes packaging treatment using solder plating,
However, the present invention is not limited to this, and a matrix lead frame 14 may be prepared in advance by applying an exterior treatment such as Pd plating to the lead areas exposed from the semiconductor device. In this case, the exterior treatment is not required in the manufacturing process of the semiconductor device 1, so the number of steps is reduced and productivity is improved. Furthermore, in the above-mentioned cutting process, a cutting method using a cutting die was explained, but after dicing tape is attached to the underside of the matrix lead frame 14, a dicing blade may be used to separate each unit lead portion 3, just like when separating semiconductor chips from a wafer.
In this case, since there are no structural restrictions on the device compared to when cutting with a cutting die, cutting is possible near the sealing portion 12, allowing the gaps between unit lead frames 15 to be narrowed and improving the utilization efficiency of the matrix lead frame 14. In addition, in this case, since the leads 2 do not protrude beyond the side surfaces of the sealing portion 12, the planar dimensions of the semiconductor device can be made smaller than when cutting with a cutting die. In addition, in the above-mentioned manufacturing method, the matrix lead frame 14 having the step portion 6 formed by half-etching is prepared, but this is not necessarily limited to this, and the matrix lead frame 14 having the step portion 6 formed by coining may also be prepared. FIG. 22 is an external perspective view showing the semiconductor device of this embodiment 1 mounted on a mounting substrate, and FIG. 23 is a cross-sectional view taken along the H-H cutting line in FIG. 22. This semiconductor device 1
To mount the semiconductor device 1 on the mounting substrate 27, a bonding material 29 such as cream solder is applied to the wiring 28 of the mounting substrate 27 that corresponds to the leads 2 on the underside of the sealing portion 12 of the semiconductor device 1, and the semiconductor device 1 is temporarily attached to the wiring 28 of the mounting substrate 27 to which the bonding material 29 has been applied.
The semiconductor device 1 of the first embodiment has a height of 1 mm when mounted, as shown in FIG.
It is very thin from front to back, and the plane dimensions are the same as QFP (Quad Flat Package).
e), in which the leads protrude from the side of the sealing portion, making it possible to achieve high-density packaging. Furthermore, since the tabs are not exposed from the underside of the semiconductor device as in the prior art, it is possible to prevent short circuits between the tabs and the wiring on the mounting board. (Embodiment 2) Fig. 24 is a plan view of a unit lead portion of embodiment 2. In Fig. 24, the dashed line indicates the sealing region. Fig. 25 is a cross-sectional view of the unit lead portion of Fig. 24 taken along line I-I, Fig. 26 is a cross-sectional view of the unit lead portion of Fig. 24 taken along line J-J, Fig. 27 is a partial perspective view of the semiconductor device of embodiment 2, and Fig. 28 is a cross-sectional view of the semiconductor device of Fig. 27 taken along line K-K. The difference between the first and second embodiments is that in the first embodiment, the tab hanging leads 4 (excluding the outer end) and the tab 5 have step portions 6 on their undersides, so that the tab 5 and the tab hanging leads 4 can be sealed with sealing resin 11. However, in the second embodiment, in addition to the tab hanging leads 4 (excluding the outer end) and the underside of the tab 5, the leading ends of the leads 2 on the tab 5 side (hereinafter referred to as inner ends 31) are sealed with sealing resin 11.
) also has a step portion 6, so that in addition to the tab 5 and tab suspension leads 4, the inner end portion 31 of the lead 2 can also be sealed with the sealing resin 11. Other than this, the second embodiment is almost the same as the first embodiment, so only the differences will be described and the same points will not be described again. As shown in Figures 24, 25 and 26, the unit lead portion 3 of the second embodiment has a tab 5 supported by four tab suspension leads 4 in the center, and the tab 5
27 and 28, a semiconductor chip 8 is fixed on the tab 5 of the unit lead portion 3 with an adhesive 9 such as a non-conductive paste or a non-conductive film. Each pad 7 of the semiconductor chip 8 is electrically connected to the plurality of leads 2 via a conductive wire 10 made of Au, Al, or the like. The semiconductor chip 8, wire 10, tab 5, tab suspension lead 4, and leads 2 (excluding the outer end) are all half-etched on their undersides, making them about half as thick as the remaining portions of the unit lead portion 3. To prevent contact between the leads 2 and the tab suspension lead 4, a corner 32 of each lead 2 closest to the tab suspension lead 4 that faces the tab suspension lead 4 is chamfered. As shown in FIGS. 27 and 28, a semiconductor chip 8 is fixed on the tab 5 of the unit lead portion 3 with an adhesive 9 such as a non-conductive paste or a non-conductive film. Each pad 7 of the semiconductor chip 8 is electrically connected to the plurality of leads 2 via a conductive wire 10 made of Au, Al, or the like.
The upper surface, side surface and underside of the inner end portion are sealed with sealing resin 11 such as epoxy resin or silicone resin for the purpose of protection and improving moisture resistance. However, the underside of the outer end portion 30 of the lead 2 is exposed on the underside of the semiconductor device 1 as a terminal for external connection. In this way, in the semiconductor device 1 of the second embodiment, a step portion 6 is formed on the underside of the inner end portion 31 of the lead 2 by half etching, and this step portion 6 is sealed with sealing resin 11, so that the inner end portion 31 of the lead 2 can have a relatively free shape. In other words, the underside of the lead 2 exposed from sealing portion 12 is sealed with sealing resin 11 as specified by the Electronic Industries Association of Japan.
However, the leads 2 in the sealing portion 12 are not standardized, and their shape and lead pitch can be designed to be optimal depending on the size of the semiconductor chip 8 and the number of pads. In addition to the effects of the first embodiment in that the semiconductor device 1 has a stepped portion 6 formed by half-etching, that the sealing resin 11 can be placed there, that the lower surfaces of the leads 2 are exposed from the lower surface of the semiconductor device 1 and used as terminals for external connection, and that the leads 2 only slightly protrude from the side surfaces of the sealing portion 12, the second embodiment has the same effects as the first embodiment in that the stepped portion 6 is formed by half-etching on the lower surface of the inner end 31 of the lead 2 and the stepped portion 6 is sealed with the sealing resin 11, and therefore the shape and lead pitch of the inner end 31 of the lead 2 can be designed to be optimal depending on the size of the semiconductor chip 8 and the number of pads. 31 is a plan view showing the internal structure of an example of a semiconductor device according to a third embodiment of the present invention, with the sealing portion broken away; FIG. 32 is a cross-sectional view of the semiconductor device shown in FIG. 31 taken along the L-L cutting line; FIG. 33 is a process flow diagram showing an example of the assembly procedure of the semiconductor device shown in FIG. 31; and FIGS. 34(a) to 34(e) are cross-sectional flow diagrams showing an example of the structure of each of the main steps in the assembly of the semiconductor device shown in FIG. 31. The semiconductor device according to the third embodiment is similar to the semiconductor device described in the second embodiment, and is a peripheral type QFN (Quad Flat Nozzle) package in which a plurality of leads 2 are arranged on the periphery of the back surface 12a of the sealing portion 12 (the surface on which the semiconductor device is mounted).
The present embodiment is a QFN (Quasi-Functional Flat Network) Package (QFN) 49. Therefore, only the characteristic features of the QFN 49 will be described here, and descriptions of parts overlapping with those of the second embodiment will be omitted. The structure of the QFN 49 includes a tab 5 that supports a semiconductor chip 8, a sealing portion 12 formed by sealing the semiconductor chip 8 with resin, tab suspension leads 4 that support the tab 5, a plurality of leads 2 that are arranged around the tab 5 and exposed on the back surface 12a of the sealing portion 12, and that have thick portions 2a and thinner portions 2b that form a step in the thickness direction, wires 10 that are connecting members that connect pads (surface electrodes) 7 of the semiconductor chip 8 to the corresponding leads 2, and an adhesive 9 such as silver paste that bonds the semiconductor chip 8 to the tab 5. 31 and 32, each lead 2 arranged on the peripheral portion of the back surface 12a of the sealing portion 12 is provided with a thick portion 2a and a thin portion 2b, and the thick portion 2a of the lead 2 is exposed on the peripheral portion of the back surface 12a of the sealing portion 12, while the thin portion 2b is covered with the sealing resin 11. That is, the lead 2 is formed with a thin portion 2b that is thinner than the thick portion 2a, and the thin portion 2b to which the wire 10 is connected is embedded in the sealing portion 12 and serves as an inner lead, while the surface of the thick portion 2a exposed on the back surface 12a of the sealing portion 12 serves as a connected portion 2c and serves as an outer lead. Also, in the QFN 49, the tab 5 is supported by a plurality of tab suspension leads 4, and as shown in FIG. 37 of a fourth embodiment described later, the tab suspension lead 4 has a supporting portion 4a that supports the tab 5 and a connecting portion 4a that is connected to the supporting portion 4a and is connected to the connecting portion 4a and is covered with the back surface 12a of the sealing portion 12.
a) and an exposed portion 4b exposed at the lead 2a, and the supporting portion 4a is thinner than the exposed portion 4b. The plurality of tab hanging leads 4 are connected via tabs 5, and the exposed portion 4b of the tab hanging leads 4 and the thick portion 2a of the lead 2 are formed to have the same thickness. That is, each of the plurality of tab hanging leads 4 consists of a supporting portion 4a connected to the tab 5 and having approximately the same thickness as the tab 5, and an exposed portion 4b connected to the supporting portion 4a and thicker than the supporting portion 4a, and the plurality of tab hanging leads 4 are connected together via the tabs 5. Therefore, the tab hanging leads 4 have thick portions (exposed portions 4b)
) and a thin portion (supporting portion 4a), and a plurality of tab hanging leads 4 are connected via tabs 5. As a result, the supporting portion 4a of the tab hanging lead 4 is embedded in the sealing portion 12, and the exposed portion 4b is exposed at the end of the corner of the back surface 12a of the sealing portion 12. Note that the processing of the step between the thick portion 2a and the thin portion 2b of the lead 2 of the QFN49 (processing to form the thin portion 2b) and the processing of the supporting portion 4a of the tab hanging lead 4
The processing of the step between the support portion 4a and the exposed portion 4b (processing to form the support portion 4a) can be performed, for example, as follows:
This can be done by etching (half etching) as described in the eleventh embodiment or by pressing such as coining as described in the eleventh embodiment. Next, the assembly method of the QFN 49 will be described with reference to the process flow diagram shown in FIG. 33 and the process flow diagram shown in FIG.
The process will be described with reference to the cross-sectional flow diagram shown in FIG. 4. First, a matrix lead frame 14 (see FIG. 11) is prepared, which is a lead frame having a tab 5 capable of supporting a semiconductor chip 8, a tab suspension lead 4 having a support portion 4a supporting the tab 5 and an exposed portion 4b connected to the support portion 4a and thicker than the support portion 4a, and a plurality of leads 2 arranged around the tab 5 and having a thick portion 2a forming a step in the thickness direction and a thin portion 2b thinner than the thick portion 2a (see FIG. 11).
Step S1). Next, after applying adhesive 9 to the tab 5, as shown in FIG.
The semiconductor chip 8 is bonded to the tab 5 via the adhesive 9 applied to the tab 5, that is, die bonding is performed to fix the semiconductor chip 8 to the tab 5 (step S2).
34(b), wire bonding is performed as shown in step S3, in which the pads 7 of the semiconductor chip 8 are connected to the corresponding leads 2 by wires 10, which are connecting members.
and are connected by wire bonding using wires 10 such as gold wires. Thereafter, molding is performed as shown in step S4 to form a sealing portion 12 as shown in Fig. 34(c). During the molding, sealing resin 11 is made to flow around the surface of the tab 5 opposite the chip support surface 5a (hereinafter referred to as back surface 5b), and the thin portions 2b of the leads 2 and the support portions 4a of the tab hanging leads 4 are covered with sealing resin 11.
The semiconductor chip 8 is resin-molded with the thick portions 2a of the leads 2 and the exposed portions 4b of the tab support leads 4 arranged around the periphery of the semiconductor chip 8. This embeds the semiconductor chip 8, wires 10, tabs 5, support portions 4a supporting the tabs 5, and thin portions 2b of the leads 2 in the sealing portion 12. Then, as shown in FIG. 34(d), the leads 2 exposed on the back surface 12a of the sealing portion 12 are subjected to an exterior treatment to improve mountability when the QFN 49 is mounted on a mounting substrate 27 (see FIG. 23). This ensures a standoff equivalent to the thickness of the plated portion 13. While solder plating using Pb-Sn solder is preferable for this exterior treatment, plating using Pb-free solder such as Sn-Ag or Sn-Zn solder may also be used. Then, cutting is performed as shown in step S5. Here, the tab suspension leads 4 are divided at the exposed portions 4b of the tab suspension leads 4, and the plurality of leads 2 are separated from the frame portion 14a of the matrix lead frame 14 (lead frame), thereby completing the QFN 49 shown in Fig. 34(e) (step S6). According to the QFN 49 and its manufacturing method of the third embodiment, the leads 2 are provided with steps, i.e., thin portions 2b and thick portions 2a, and the thin portions 2b are formed in the sealing portion 12.
By embedding the lead 2 in the sealing portion 12, it is possible to prevent the lead 2 from falling off from the sealing portion 12 in the QFN height direction, and therefore to prevent the lead 2 from being pulled out of the sealing portion 12. Furthermore, by forming the exposed portion 4b of the tab hanging lead 4 and the exposed portion 2a of the lead 2 to the same thickness, the mold clamping surface can be flush during molding. That is, if the exposed portion 4b of the tab hanging lead 4 and the exposed portion 2a of the lead 2 have different thicknesses, the sealing resin 11 will get into the thinner side, and the metal and resin (sealing resin 11) will have to be cut together when the lead is cut. This is likely to cause problems. However, if the exposed portion 4b of the tab hanging lead 4 and the thick portion 2a of the lead 2 are formed to the same thickness, the sealing resin 11 will not be present at the cut location, and the lead can be cut smoothly. This reduces the occurrence of problems when the lead is cut. (Embodiment 4) FIG. 35 is an external perspective view showing an example of the structure of a semiconductor device according to embodiment 4 of the present invention.
36 is a bottom view showing the structure of the semiconductor device shown in FIG. 35, FIG. 37 is a cross-sectional view taken along the line M--M of the semiconductor device shown in FIG. 35, and FIG. 38 is a cross-sectional view of the N--N section of the semiconductor device shown in FIG.
39 is a cross-sectional view taken along the -N cutting line, and FIG. 39 is a partial cross-sectional view showing an example of a state during wire bonding in the assembly of the semiconductor device shown in FIG. 35. The semiconductor device of the fourth embodiment is a QFN 50 substantially similar to the semiconductor device described in the third embodiment. The QFN 50 shown in FIGS. 35 to 38 is characterized in that the plurality of tab suspension leads 4 include a support portion 4a that supports the tab 5 and an exposed portion 4b that is connected thereto and exposed on the back surface 12a of the sealing portion 12, and the support portion 4a is formed thinner than the exposed portion 4b, and the plurality of tab suspension leads 4 are connected via the tab 5. That is, as shown in FIG. 37, the plurality of tab suspension leads 4 are connected to each other via the tab 5 in an integrated state, and the tab suspension leads 4 are formed with the support portion 4a, which is a thin portion, and the exposed portion 4b, which is a thick portion.
36, exposed portions 4b, which are thick portions of the tab hanging lead 4, are arranged at the ends of the four corners of the back surface 12a of the sealing portion 12. As a result, the support portions 4a of the tab hanging lead 4 are covered with the sealing resin 11, and the exposed portions 4b are arranged at the ends of the corners of the back surface 12a of the sealing portion 12. Also, as shown in FIG. 37, the chip support surface 5a of the tab 5 and the surface 4c of the tab hanging lead 4 on the chip placement side are formed on the same flat surface. In other words, the QFN 50 of this fourth embodiment minimizes the exposure of the tab hanging lead 4 to the back surface 12a of the sealing portion 12 to prevent an electrical short circuit between the tab hanging lead 4 and the adjacent lead 2 when mounted on a mounting board, and therefore,
The portion (support portion 4a) of the tab hanging lead 4 other than the exposed portion 4b exposed at the end of the corner of the sealing portion 12 is embedded in the sealing portion 12. Therefore, the exposed portion 4b, which is the thick portion of the tab hanging lead 4, has a portion made of metal only without the sealing resin 11 disposed therein, and the tab hanging lead 4 is cut off here. Note that the chip support surface 5a of the tab 5 and the surface 4c of the tab hanging lead 4 on the chip placement side
In order to form the supporting portion 4a of the tab hanging lead 4 on the same flat surface, the supporting portion 4a is formed thinner than the exposed portion 4b by a press process such as etching (half etching) or coining, rather than by a tab raising process using a bending process.
Therefore, as shown in FIG. 37, the tab 5 and the support portion 4a of the tab suspension lead 4 are formed with the same thickness. For example, if the thickness of the exposed portion 4b of the tab suspension lead 4 is about 0.2 mm, the thickness of the tab 5 and the support portion 4a, which has the same thickness, is about 0.08 to 0.1 mm (amount of removal: 0.1 to 0.12 mm). Furthermore, as shown in FIG. 38, the tab 5 supporting the semiconductor chip 8 is formed smaller than the semiconductor chip 8. In other words, the QFN 50 has a small tab structure. Therefore, in the QFN 50, the tab 5 and the semiconductor chip 8 are joined (die-bonded) at a location (position) inside the pad 7 of the semiconductor chip 8 via an adhesive 9 such as silver paste. As a result, as shown in FIG. 39, the semiconductor chip 8 is easily attached to the tab 5 during wire bonding.
The peripheral edge of the back surface 8b (the surface opposite to the main surface 8a on which the semiconductor integrated circuit is formed) of the QFN 50 can be reliably supported by the bonding stage 20.
1. The fourth embodiment is substantially the same as the first embodiment, except that when the semiconductor chip 8 and the tab 5 are bonded in the die bonding process, the semiconductor chip 8 is bonded to the tab 5 at a location (region) inside the pad 7. Furthermore, when the tab hanging leads 4 are broken (cut) in the lead cutting process, only the metal not containing the sealing resin 11 is broken in the exposed portions 4b of the tab hanging leads 4. According to the QFN 50 of the fourth embodiment, the support portions 4a of the tab 5 in the tab hanging leads 4 are formed thinner than the exposed portions 4b, so that the support portions 4a can be covered with the sealing resin 11 and embedded in the sealing portion 12. Therefore, a structure can be achieved in which the exposed portions 4b are exposed only at the corner ends of the back surface 12a of the sealing portion 12. As a result, the exposed portions 4b of the tab hanging leads 4 are broken in the back surface 12a of the sealing portion 12.
, a large clearance can be formed between the adjacent leads 2, and since the tab 5 is embedded in the sealing portion 12, electrical shorts can be prevented when the QFN 50 (semiconductor device) is mounted on a mounting board 27 (see FIG. 23) or the like. Also, since the exposed portion 4b of the tab hanging lead 4 is thicker than the supporting portion 4a, no sealing resin 11 is disposed on the exposed portion 4b, so when the tab hanging lead 4 is cut, only the metal of the exposed portion 4b, which does not contain the sealing resin 11, is cut, preventing the occurrence of dent defects and thereby improving cuttability when cutting the tab hanging lead. Also, since multiple tab hanging leads 4 are connected via the tab 5,
Since the tab 5 and the tab suspension lead 4 are integrally connected and the chip support side surfaces thereof are formed by a flat surface, the flatness of the tab 5 itself can be improved. As a result, the semiconductor chip 8 can be easily mounted on the tab 5 during bonding, and chip bonding performance can be improved. Furthermore, since the tab 5 and the semiconductor chip 8 are bonded at a location inside the pads 7 of the semiconductor chip 8, the bonding stage 20 can support the vicinity of the end of the back surface 8b of the semiconductor chip 8 during wire bonding. Therefore, appropriate ultrasonic waves and heat can be applied to the bonding wires 10 during wire bonding, thereby improving the reliability and bonding performance of wire bonding. (Embodiment 5) Figure 40 is a partial plan view showing the interior of an example of the structure of a semiconductor device according to embodiment 5 of the present invention after molding, seen through the sealing portion; Figure 41 is a cross-sectional view of the semiconductor device shown in Figure 40 taken along the P-P cutting line; Figure 42 is a partial plan view showing an example of the structure of a lead frame used in assembling the semiconductor device shown in Figure 40; Figure 43 is a partial plan view showing the interior of the semiconductor device shown in Figure 40;
44 is an enlarged partial cross-sectional view showing an example of a lead cutting method at the T portion of FIG. 41; FIG. 45 is a diagram showing the lead structure at the Q portion of FIG. 40, where (a) is a bottom view, (b) is a plan view, (c) is a cross-sectional view of the groove, and (d) is a diagram showing the lead structure at the Q portion of FIG.
40. FIG. 40 shows a cross-sectional view of the lead 2 in the QFN 50 and the like described in the fourth embodiment, taken along line U-U in FIG. 40b, a cross-sectional view of the lead 2 in the QFN 50 and the like, taken along line V-V in FIG. 40b, and a plan view showing a modified example of the lead structure of the Q portion in FIG. 40. In the fifth embodiment, the shape of the lead 2 in the QFN 50 and the like described in the fourth embodiment will be described together with its effects. FIG. 40 shows the structure inside the sealing portion 12 after molding is completed, with the sealing portion 12 and the semiconductor chip 8 both visible through the sealing portion 12. The tab 5 shown in FIG. 40 has a small cross-shaped tab structure (the tab 5 is in contact with the semiconductor chip 8).
In the semiconductor device of the fifth embodiment, each of the leads 2 is provided with a sealing portion 12.
The connecting portion 2c is exposed at the peripheral edge of the rear surface 12a of the
and a flange-shaped thin portion 2b formed thinner than the lead 2c, and a surface opposite to the exposed side disposed in the sealing portion 12 of the connected portion 2c of each lead 2 (hereinafter,
The pads 7 of the semiconductor chip 8 and the wire bonding surfaces 2d of the corresponding connected portions 2c of the leads 2 are connected by wires 10. Furthermore, the thin portions 2b of the leads 2 are covered with sealing resin 11, and the wires 10 are bonded to the connected portions 2c of the leads 2 by wires 10.
The thin portion 2b of the lead 2 in this fifth embodiment is formed in a flange-like shape so that its tab-side end slightly protrudes toward the tab 5. This is formed by etching (half-etching) or press processing such as coining. The protrusion amount is, for example, about 50 to 150 μm. This thin portion 2b prevents the lead 2 from falling off in the QFN height direction. In other words, it prevents the lead 2 from being pulled out in the QFN height direction. Furthermore, the inner groove 2e provided on the wire bonding surface 2d of the lead 2 serves as a marker for the bonding point during wire bonding. In other words, by forming the inner groove 2e in an area on the wire bonding surface 2d of the lead 2 outside the thin portion 2b, it is possible to prevent the wire 10 from being bonded at the thin portion 2b. Note that the inner groove 2e serves as a marker for the bonding point, and is therefore smaller than the outer groove 2f, as shown in FIG. 45 . On the other hand, the outer groove 2f is a portion that receives the cutting stress when the lead 2 is cut. When the lead is cut as shown in FIG. 44, the cutting stress is concentrated in this outer groove 2f to prevent stress from being applied to the bonded portion of the wire 10. Furthermore, the outer groove 2f also prevents plating from flowing when forming the plating layer 21, such as silver plating for wire bonding, shown in FIG. 43, on the wire bonding surface 2d of the lead 2. That is, the groove shape formed by the outer groove 2f can have a longer absolute distance than a flat surface, thereby increasing the leak path length when forming the plating, thereby preventing plating from flowing. Furthermore, the groove shape formed by the outer groove 2f can have a longer absolute distance than a flat surface, thereby preventing moisture from penetrating into the sealing portion 12. As shown in FIG. 45(b), the outer groove 2f is larger than the inner groove 2e. This ensures stress concentration when the lead is cut and prevention of plating from flowing when forming the plating layer. However, the size and shape of the outer groove 2f and the inner groove 2e are not particularly limited. For example, as shown in FIG. 46, both grooves may be oval grooves of approximately the same size. Furthermore, as shown in FIGS. 45(d) and 45(e), a flange 2g that protrudes slightly in the width direction is provided on the side of the lead 2. This flange 2g prevents the lead 2 from falling off in the QFN height direction. That is, it is possible to prevent the lead 2 from being pulled out in the QFN height direction. Furthermore, since the inner groove 2e and the outer groove 2f are provided on the wire bonding surface 2d of the lead 2, the sealing resin 11 fills both grooves, preventing the lead 2 from falling off in its extension direction (the horizontal direction of the QFN perpendicular to the QFN height direction). That is, it is possible to prevent the lead 2 from being pulled out in its extension direction. In the manufacturing method of the semiconductor device according to the fifth embodiment, when connecting the pad 7 of the semiconductor chip 8 to the corresponding connected portion 2c of the lead 2 by wire bonding in the wire bonding step, the pad 7 of the semiconductor chip 8 is connected to the portion 2c of the lead 2 between the inner groove 2e and the outer groove 2f by the wire 10, as shown in Fig. 41. It is not necessary to provide both the inner groove 2e and the outer groove 2f, and either one of the grooves may be provided. For example, only one groove, the outer groove 2f, may be provided on the wire bonding surface 2d of the lead 2, and in that case, the wire 10 is connected to the connected portion 2c by the outer groove 2f.
As a result, as in the above, it is possible to obtain the effects of concentrating stress when the lead is cut and preventing plating from flowing when the plating layer is formed. Also, only one groove, the inner groove 2e, may be provided on the wire bonding surface 2d of the lead 2. In this case, the wire 10 is connected to the connection portion 2c through the inner groove 2e.
As a result, the inner groove 2e can be used as a mark for the bonding point during wire bonding, allowing wire bonding to be performed at an accurate location. (Embodiment 6) Figure 47 is an enlarged partial plan view showing the structure of the R portion of Figure 40 described in embodiment 5. In this embodiment 6, as in embodiment 5, the QFN described in embodiment 4 is used.
The shape of the leads 2 in the pins 50 and 51 will be described together with their effects. In this sixth embodiment, among the multiple leads 2, the leads 2 arranged adjacent to the tab suspension lead 4 on both sides thereof are taken up, and a tapered portion (notch) 2h is provided at the tip of the lead 2 on the tab suspension lead side, forming a gap 2i along the tapered portion 2h between the tab suspension lead 4 and the lead 4. This tapered portion 2h is a notch for forming the gap 2i required for processing when forming a lead pattern by etching, press processing, or the like, and a gap of, for example, about 80% of the lead thickness is required for processing. In particular, when the number of pins increases and the density of the leads 2 arranged between the tab suspension leads increases, the tip of the lead 2 adjacent to the tab suspension lead 4 on the tab suspension lead side comes close to the tab suspension lead 4, making it impossible to pattern the tab suspension lead 4 or the leads 2 adjacent to it. Therefore, by providing a tapered portion (notch) 2h that forms a gap 2i at the tip of the lead 2 adjacent to the tab suspension lead 4 on the tab suspension lead side, it is possible to form a lead pattern for the lead 2 that is arranged adjacent to the tab suspension lead 4, and also to accommodate an increase in the number of pins. (Embodiment 7) Figure 48 is a diagram showing the structure of portion S in Figure 40 described in embodiment 5, and (a
48(a) is an enlarged partial plan view, (b) is a cross-sectional view taken along the X-X cutting line in (a), FIG. 49 is a diagram showing the structure of the W portion in FIG. 48(a), (a) is an enlarged partial bottom view, (b)
19 is a cross-sectional view of the groove portion of FIG. 7A. In this seventh embodiment, the shape of the tab suspension lead 4 in the QFN 50 and the like described in the fourth embodiment will be described together with its effects. In this seventh embodiment, with respect to the multiple (four) tab suspension leads 4 supporting the tab 5, each tab suspension lead 4 has an exposed portion 4b exposed at the end of the back surface 12a of the sealing portion 12 and a groove portion 4d, which is a thin portion extending both inside and outside the mold line 12b (outer periphery) of the sealing portion 12. Note that a gate 26 of the molding die (see FIG. 19) is formed in the vicinity of the mold line 12b of the tab suspension lead 4. Therefore, since the sealing resin 11 is formed thick in this vicinity, the tab suspension lead 4 is cut in a manner close to breaking (tearing) in the lead cutting process. Therefore, this groove portion 4d is a notch (cutout) for concentrating stress so that the tab suspension lead 4 can be easily broken (cut) in the lead cutting process.
The groove 4d is formed in a position corresponding to the mold line 12b of the sealing portion 12 of the tab hanging lead 4 (a region spanning both the inside and outside of the mold line 12b) to provide a trigger for breaking the tab hanging lead.
The groove 4d is formed on the exposed surface opposite the chip-mounting surface 4c of the tab hanging lead 4. That is, the groove 4d is formed on the surface corresponding to the back surface 12a (rear side) of the sealing portion 12 of the tab hanging lead 4. This prevents the sealing resin 11 from entering the groove 4d, thereby preventing dent defects due to floating resin (sealing resin 11) scraps and punch wear due to resin cutting. This also extends the life of the lead cutting punch 54 (see FIG. 44). As shown in FIGS. 49(a) and 49(b), the groove 4d is formed in an oval shape elongated in the extension direction of the tab hanging lead 4 and is further surrounded by a sidewall 4e. This takes into account the misalignment of the sealing portion 12 during molding. By forming the groove 4d in an oval shape elongated in the extension direction of the tab hanging lead 4 (as shown in FIG. 49(a) , the groove 4d is elongated in the lead extension direction so that CD > EF), the groove 4d is reliably positioned on the mold line 12b. Furthermore, by forming side walls 4e (JK) shown in Figure 49(a) on both sides of the oval groove 4d in the lead width direction, it is possible to prevent the occurrence of trigger interference when cutting the lead due to resin debris getting into the groove 4d. Furthermore, since the side walls 4e can prevent resin debris from getting into the groove 4d, it is possible to prevent the occurrence of dent defects due to floating resin debris and punch wear due to resin cutting, as described above. In the manufacturing method for a semiconductor device according to this seventh embodiment, in the molding process,
The groove 4d of the tab hanging lead 4 and the mold line 12b (periphery) of the sealing portion 12
The tab hanging leads 4 are molded with resin to form the sealing portion 12. That is, the oval grooves 4d in the tab hanging leads 4 are aligned with the molding lines 12.
The sealing portion 12 is formed so as to be disposed across the inside and outside of the groove 4d. This allows the groove 4d to act as a trigger for the lead to be cut (broken). (Embodiment 8) Figure 50 is a diagram showing an example of the structure of a semiconductor device according to embodiment 8 of the present invention.
50(a) is a plan view, (b) is a side view, (c) is a bottom view, and FIG. 51 is an enlarged partial bottom view showing the structure of the Y portion of FIG. 50(c). In the eighth embodiment, the same QFN 50 as that of FIG. 50(a) described in the fourth embodiment is used.
2, (b), and (c) show the back surface 12 of the sealing portion 12 of the lead 2 in the QFN 51.
The relationship between the length of the connected portion 2c exposed at the peripheral edge of the tab support lead 4a and the length of the exposed portion 4b exposed at the end of the corner of the back surface 12a of the sealing portion 12 of the tab support lead 4, along with the effects thereof, will be described below. In this eighth embodiment, the length in the extending direction of the exposed portion 4b of the tab support lead 4 is formed shorter than the length in the extending direction of the connected portion 2c of the lead 2, as shown in FIG.
) should be as short as possible. This is because increasing the number of leads in the same package size
This is to prevent the possibility of an electrical short circuit occurring when the lead 2 is mounted on a mounting board due to the close distance between the exposed portion 4b of the tab hanging lead 4 and the leads 2 arranged adjacent to it on both sides. Therefore, the length (LX) of the exposed portion 4b of the tab hanging lead 4 is made shorter than the length (LP) of the connected portion 2c of the lead 2 (LX<LP). Furthermore, it is preferable that the relationship between the distance (LY) between the connected portion 2c of the lead 2 adjacent to the tab hanging lead 4 and the exposed portion 4b of the tab hanging lead 4 and the distance (LZ) between the adjacent leads is (
This prevents electrical short circuits (
52 is a partial plan view showing the inside of an example of the structure of a semiconductor device according to a ninth embodiment of the present invention after molding is completed, seen through the sealing portion; FIG. 53 is a cross-sectional view of the semiconductor device shown in FIG. 52 taken along the Z-Z cutting line; FIG. 54 is an enlarged partial cross-sectional view showing the structure of part AB in FIG. 53; and FIG. 55 is an enlarged partial cross-sectional view showing an example of a method for cutting the leads of part AB in FIG. 53. In this ninth embodiment, the shape of the leads 2 in a semiconductor device having a plurality of leads 2 with extensions 2j arranged close to and toward the center of the tab 5 will be described together with the effects thereof. Note that FIG. 52 shows the structure inside the sealing portion 12 after molding is completed, seen through the sealing portion 12 and the semiconductor chip 8. In the semiconductor device according to the ninth embodiment, the shape of the leads 2 arranged around the tab 5 will be described together with the effects thereof.
Each of the leads 2 has an extending portion 2j arranged close to the tab 5 toward the center of the tab 5, and a connected portion 2c exposed at the peripheral edge of the back surface 12a of the sealing portion 12. Furthermore, the extending portion 2j of each lead 2 is formed thinner than the connected portion 2c and is covered with the sealing resin 11. Also, a lead groove (groove) 2 is formed on the wire bonding surface 2d, which is the surface opposite to the exposed side arranged in the sealing portion 12 of the connected portion 2c.
k are formed. The semiconductor device of the ninth embodiment is configured such that when the distance between the leads 2 and the semiconductor chip 8 becomes longer due to the enlargement of the package caused by an increase in the number of pins or the miniaturization of the semiconductor chip 8, an extension portion 2j is provided at the tab-side end of each lead 2 to extend the lead 2, thereby preventing the distance between the leads 2 and the semiconductor chip 8 from becoming longer. Therefore, each lead 2 is provided at its tab-side end with an extension portion 2j toward the center of the tab 5 (toward the corresponding pad 7) to facilitate bonding of the wire 10. That is, as shown in FIG. 52, each lead 2 has a shape that extends radially outward from the periphery near the tab 5. As a result, even if the package size increases or the semiconductor chip 8 is miniaturized, the wire length does not become longer, thereby suppressing an increase in costs. 54, the EIAJ standard specifies the length (LP) of the connected portion 2c exposed on the back surface 12a of the sealing portion 12, so when an extension portion 2j is provided on the lead 2, the extension portion 2j must be embedded in the sealing portion 12. In the semiconductor device of the ninth embodiment, the extension portion 2j is formed thinner than the connected portion 2c and embedded in the sealing portion 12 without raising the position of the extension portion 2j (without performing lead raising processing). That is, as shown in FIGS. 53 and 54, the extension portion 2j of each lead 2 is
The extension 2j is formed thinner than the connected portion 2c exposed on the back surface 12a of the sealing portion 12, and the extension 2j is covered with the sealing resin 11 together with the tab 5.
41, the extension 2j has a longer distance in the extension direction than the flange-shaped thin portion 2b. Therefore, it is possible to place the bonding stage 20 (see FIG. 39) below the extension 2j during wire bonding, and appropriate ultrasonic waves and heat can be applied to the wire 10 and the lead 2 during wire bonding. The extension 2j can be formed thin by etching (half etching) or press processing such as coining. In addition, the wire bonding surface 22 disposed within the sealing portion 12 of the connection portion 2c of each lead 2 is thin enough to be easily bonded.
As shown in Fig. 54, a lead groove (groove) 2k is formed at a location closer to the outside of the surface d (the surface opposite to the exposed side). This lead groove 2k is the same as the outer groove 2f (see Fig. 43) described in the fifth embodiment.
55, cutting stress can be concentrated on this lead groove 2k so that stress is not applied to the bonded portion of the wire 10. Furthermore, the lead groove 2k can also prevent plating from flowing when forming a plating layer 21, such as silver plating for wire bonding shown in FIG. 54, on the wire bonding surface 2d of the lead 2. Furthermore, since the groove shape of the lead groove 2k can have a longer absolute distance than a flat surface, it is possible to prevent moisture from penetrating into the sealing portion 12. Furthermore, since the sealing resin 11 enters the lead groove 2k by molding, it is possible to prevent the lead 2 from falling off in the direction in which the lead 2 extends. In other words, it is possible to prevent the lead 2 from being pulled out in the direction in which it extends. (Embodiment 10)
58(a), (b), (c), and (d) are partial cross-sectional views showing an etching method, which is one example of a method for processing a lead frame used in assembling a semiconductor device of the present invention. This embodiment 10 describes one example of a method for processing the leads 2 and tabs 5 of the semiconductor device described in embodiments 1 to 9, and here, etching processing (half etching processing) will be described. The etching solution 52 used in the etching processing of this embodiment 10 is, for example, a ferric chloride solution, but is not limited to this. Figures 56(a), (b), (c), and (d) show a method (procedure) for forming the cross-sectional shape of the leads 2 as shown in Figure 45(e), for example, and Figure 57(a)
, (b), (c), and (d) are methods (procedures) for forming the cross-sectional shape of the lead 2 as shown in Fig. 45(d), for example. That is, in Figs. 56 and 57, by changing the opening width (opening area) of the portions where the photoresist film 53 is not formed (portions A and B shown in Figs. 56 and 57), the amount of etching on the front and back surfaces of the lead 2 can be adjusted, thereby making it possible to obtain the respective cross-sectional shapes. In the processing shown in Fig. 56, A ≒ B and G ≒ H, so C ≒ D and E ≒
On the other hand, in the processing shown in FIG. 57, A<B and I>J, so C<D
, E>F. Also, FIGS. 58(a), (b), (c), and (d) show a method (
58(a), a photoresist film 53 is formed with a fine pitch (B) only on the processed surface side of the tab 5, etc., and as shown in FIG. 58(b), an etching solution 52 is applied only to the processed surface side, thereby realizing the back surface processing of the tab 5 and the thinning of the extension portion 2j of the lead 2 as shown in FIG. 53. (Embodiment 11) FIGS. 59(a), (b), (c), 60(a), (b), (c), and 61
59(a), (b), and (c) are partial cross-sectional views showing a press method, which is an example of a method for processing a lead frame used in assembling a semiconductor device of the present invention. This embodiment 11 describes an example of a method for processing the leads 2 and tabs 5 of the semiconductor device described in the first to ninth embodiments, and here, press processing such as coining will be described. 59(a), (b), and (c) show a method (procedure) using press processing when processing the back surface of the tab 5 as shown in FIG. 53, for example, and FIG. 60(a)
, (b), and (c) are methods (procedures) using press working when thinning the extension 2j of the lead 2 as shown in FIG.
The lead 2 and the like are coined with a punch 54 to be thinned. In this processing method, the coining may be performed at the beginning of material processing, or may be performed only on necessary locations after the lead frame pattern has been formed. Also, Figures 61(a), (b), and (c) show a method (procedure) using press processing when forming a lead cross-sectional shape such as that shown in Figure 45(d). That is, as shown in Figure 61(a), the lead 2 and the like supported by a pedestal 55 are coined with a punch 54 to be thinned, and then the lead 2 and the like are coined with a punch 54 to be thinned as shown in Figures 61(b) and (c).
As shown in Fig. 6, the required cross-sectional shape of the lead 2 can be obtained by cutting off the unnecessary portions. The invention made by the present inventor has been specifically described above based on the embodiments of the invention, but it goes without saying that the invention is not limited to the above-described embodiments of the invention and can be modified in various ways without departing from the gist of the invention. For example, in the above-described embodiments 1 to 11, circular or cross-shaped tabs 5 have been described, but the shape of the tab 5 is not particularly limited, and can be any of the shapes shown in Figs. 62 and 64.
62 and 63 show a small tab structure divided into four, in which case the flexibility of each tab 5 in the horizontal direction (the direction horizontal to the tab suspension lead 4) can be improved, and as a result, the temperature cycle resistance of the semiconductor device can be improved.
Chip cracks and package cracks can also be reduced. Furthermore, the tab 5 shown in FIG. 64 has a frame-shaped small tab structure. In this case, the bonding area between the sealing resin 11 and the back surface 8b of the semiconductor chip 8 can be increased, thereby reducing peeling of the semiconductor chip 8. While the first to eleventh embodiments describe a matrix lead frame 14, the lead frame may also be a multi-series lead frame with unit lead frames 15 arranged in a single row. Furthermore, while the first to eleventh embodiments describe a small QFN semiconductor device, the semiconductor device may be a peripheral type semiconductor device other than a QFN, as long as it is a resin-sealed type using a mold and assembled using a lead frame. INDUSTRIAL APPLICABILITY Selected effects of representative inventions disclosed in this application are briefly described below. (1) Instead of forming a step by bending (upset processing), a step is formed by half-etching, and the sealing resin can be placed there, which makes it possible to seal the tab and tab suspension lead with the sealing resin while achieving a thin structure, eliminating the problem of reduced adhesion and impaired reliability due to a reduced contact area between the sealing resin and the tab. (2) The lower surfaces of the leads are exposed from the underside of the semiconductor device and used as terminals for external connection, which prevents deformation of the leads during transportation or mounting, improving reliability. (3) Since the leads protrude only slightly from the side of the sealing portion,
This allows for miniaturization of the planar dimensions of semiconductor devices. (4) Because the area of the encapsulated top surface of the leads is larger than the exposed bottom surface, sufficient adhesion can be ensured, even though the bonding surface with the encapsulating resin is only the top and side surfaces, maintaining reliability. (5) The stepped portion of the matrix lead frame is not formed in a post-processing step after patterning by stamping or etching a metal plate, as in the conventional method, but rather is formed by patterning and half-etching simultaneously, thereby reducing the manufacturing cost of the matrix lead frame. (6) Because the matrix lead frame does not require bending after patterning, as in the conventional method, it is possible to prevent problems such as tab location caused by bending. (7) Because bending of the external terminals of the semiconductor device is not required, as in the conventional method, the number of processes is reduced, process management is simplified, and productivity is improved. (8) Existing semiconductor manufacturing equipment can be reused for all processes, which has the advantage of requiring almost no new capital investment. (9) A step is formed on the underside of the inner end of the lead by half-etching, and the step is sealed with sealing resin, allowing the shape and lead pitch to be optimally designed depending on the size of the semiconductor chip and the number of pads. (10) Because the support portion of the tab in the tab hanging lead is made thinner than the exposed portion, the support portion can be embedded in the sealing portion, resulting in a structure in which the exposed portion is exposed only at the end of the corner on the back surface of the sealing portion. This allows for a large clearance to be formed between the exposed portion of the tab hanging lead and the adjacent lead on the back surface of the sealing portion, and because the tab is embedded in the sealing portion, short circuits can be prevented when the semiconductor device is mounted on a mounting board, etc. (11) Because the exposed portion of the tab hanging lead is thicker than the support portion, no sealing resin is placed on the exposed portion. Therefore, when the tab hanging lead is cut, only the metal of the exposed portion, not including the sealing resin, is cut, resulting in improved cuttability when cutting the tab hanging lead. (12) Because multiple tab hanging leads are connected via tabs,
The tab and the tab suspension lead are integrally connected, and the surface on the chip support side is formed by a connected flat surface, so the flatness of the tab itself can be improved.
This facilitates mounting of the semiconductor chip on the tab during bonding and improves chip connectivity. (13) Because the tab and semiconductor chip are bonded at a location inside the surface electrodes of the semiconductor chip, the bonding stage can support the edge of the back surface of the semiconductor chip during wire bonding. Therefore, appropriate ultrasonic waves and heat can be applied to the bonding wire during wire bonding, thereby improving the reliability and connectivity of the wire bonding.

[Brief explanation of the drawings]

1 is an external perspective view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view (bottom side) of the semiconductor device shown in FIG. 1, FIG. 3 is a plan view of a unit lead portion according to the first embodiment of the present invention, FIG. 4 is a cross-sectional view of the unit lead portion shown in FIG. 3 taken along the A-A cutting line, FIG. 5 is a cross-sectional view of the unit lead portion shown in FIG. 3 taken along the B-B cutting line, FIG. 6 is a partial perspective view of the semiconductor device shown in FIG. 1, FIG. 7 is a cross-sectional view of the semiconductor device shown in FIG. 6 taken along the C-C cutting line, FIG. 8 is a cross-sectional view of the semiconductor device shown in FIG. 6 taken along the D-D cutting line, FIG. 9 is a cross-sectional view of the semiconductor device 1 shown in FIG. 6 taken along the E-E cutting line, and FIG.
11 is a cross-sectional flow diagram showing a method for manufacturing the semiconductor device of the first embodiment of the present invention, FIG. 12 is an enlarged view (upper surface side) of a main portion of a unit lead frame of the matrix lead frame shown in FIG. 11, FIG. 13 is an enlarged view (lower surface side) of a main portion of a unit lead frame of the matrix lead frame shown in FIG. 11, FIG. 14 is a cross-sectional view of the unit lead frame shown in FIG. 12 taken along the F-F cutting line, FIG. 15 is a cross-sectional view of the unit lead frame shown in FIG. 12 taken along the G-G cutting line, FIG. 16 is a conceptual diagram showing a method for applying adhesive to a tab in a die bonding step of the semiconductor device of the first embodiment of the present invention, FIG. 17 is a conceptual diagram showing a method for mounting a semiconductor chip on a tab in a die bonding step of the semiconductor device of the first embodiment of the present invention, and FIG. 21 is a conceptual diagram showing a state in which the mold is opened in the resin sealing process of the semiconductor device of the first embodiment of the present invention; FIG. 22 is an external perspective view showing a state in which the semiconductor device of the first embodiment of the present invention is mounted on a mounting board; FIG. 23 is a cross-sectional view taken along the H-H line in FIG. 22; FIG. 24 is a plan view of a unit lead portion of the second embodiment of the present invention;
30 is a cross-sectional view of a semiconductor device according to a second prior art technique; FIG. 31 is a plan view showing the internal structure of an example of a semiconductor device according to a third embodiment of the present invention, with the sealing portion broken away; FIG. 32 is a cross-sectional view of the semiconductor device according to the third embodiment of the present invention, taken along the line L-L; FIG. 33 is a process flow diagram showing an example of the assembly procedure of the semiconductor device shown in FIG. 31; FIGS. 34(a), (b), (c), (d), and (e) are cross-sectional flow diagrams showing an example of the structure of each main step in the assembly of the semiconductor device shown in FIG. 31; 41 is a cross-sectional view taken along the line P-P of the semiconductor device shown in FIG. 41; FIG. 42 is a partial plan view showing an example of the structure of a lead frame used in assembling the semiconductor device shown in FIG. 40; FIG. 43 is an enlarged partial cross-sectional view showing the structure of a T portion in FIG. 41; FIG. 44 is an enlarged partial cross-sectional view showing an example of a method of cutting the leads at the T portion in FIG. 41;
40. (a) is a plan view, (c) is a cross-sectional view of the groove, (d) is a cross-sectional view taken along the U-U line in (b), (e) is a cross-sectional view taken along the V-V line in (b), FIG. 46 is a plan view showing a modified example of the lead structure of the Q portion in FIG. 40, FIG. 47 is an enlarged partial plan view showing the structure of the R portion in FIG. 40, FIG. 48 is a view showing the structure of the S portion in FIG. 40, (a) is an enlarged partial plan view,
48(a) is a cross-sectional view taken along the line X-X of FIG. 48(a), FIG. 49 is a diagram showing the structure of the W portion of FIG. 48(a), (a) is an enlarged partial bottom view, (b) is a cross-sectional view of the groove portion of FIG. 48(a), and FIG. 50 is a diagram showing an example of the structure of a semiconductor device according to an eighth embodiment of the present invention, (a)
50(c) is a bottom view; FIG. 51 is an enlarged partial bottom view showing the structure of the Y portion of FIG. 50(c); FIG. 52 is a partial plan view showing the inside of an example of the structure of a semiconductor device according to a ninth embodiment of the present invention after molding is completed, seen through the sealing portion; FIG. 53 is a cross-sectional view of the semiconductor device shown in FIG. 52 taken along the Z-Z cutting line; and FIG. 54 is a cross-sectional view of the semiconductor device shown in FIG.
55 is an enlarged partial cross-sectional view showing an example of a lead cutting method for the portion AB of FIG. 53; FIGS. 56(a), (b), (c), (d), and FIG. 5
7(a), (b), (c), (d), and 58(a), (b), (c), and (d) are partial cross-sectional views showing an etching method which is an example of a method for processing a lead frame used in assembling a semiconductor device of the present invention.
61(a), (b), (c) are partial cross-sectional views showing a pressing method, which is an example of a method for processing a lead frame used in assembling a semiconductor device of the present invention; FIG. 62 is a partial plan view showing the inside of a structure of a semiconductor device of a modified example of the present invention at the end of molding, seen through the sealing portion; FIG. 63 is a cross-sectional view of the semiconductor device of a modified example of the present invention at the CC-CC cutting line; and FIG. 64 is a partial plan view showing the inside of a structure of a semiconductor device of a modified example of the present invention at the end of molding, seen through the sealing portion.

───────────────────────────────────────────────────── Continued from the front page (81) Designated Countries EP(AT,BE,CH,CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP(GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), UA(AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE , DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SK, SL, TJ, TM , TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW (Note) This publication is based on the international publication of the International Bureau (WIPO). Please note that the effect of the international publication of the Japanese-language patent application (Japanese-language utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act), and is unrelated to this publication.

Claims (45)

[Claims] [Claim 1] A semiconductor device comprising: a tab supported by a plurality of suspension leads; a plurality of leads arranged so as to surround the periphery of the tab; a semiconductor chip mounted on one main surface of the tab and electrically connected to one main surface of the plurality of leads; and a sealing resin that seals the plurality of leads, the semiconductor chip, and the tab,
a main surface of each of the leads opposite to the one main surface of the leads being exposed from the sealing resin; and a thickness of the tab being smaller than a thickness of the leads. [Claim 2] A semiconductor device comprising a tab supported by a plurality of suspension leads, a plurality of leads arranged to surround the periphery of the tab, a semiconductor chip mounted on the tab and electrically connected to the plurality of leads, and a sealing resin that seals the plurality of leads, the semiconductor chip, and the tab so that the undersides of the plurality of leads are exposed, characterized in that the underside of the tab is covered with the sealing resin by making the tab thinner than the leads. [Claim 3] A semiconductor device comprising a semiconductor chip mounted on a tab, a sealing resin that seals the tab and the semiconductor chip, and a lead that is electrically connected to the semiconductor chip and has a portion exposed from one surface of the sealing resin, characterized in that the tab is formed thinner than the lead. 4. A semiconductor device according to claim 1, 2 or 3, wherein said leads are flat. 5. A semiconductor device according to claim 1, 2, 3 or 4, wherein said tab is formed thin by half-etching. 6. A semiconductor device according to claim 1, 2, 3 or 4, wherein said tab is formed thin by coining. [Claim 7] A semiconductor device comprising a semiconductor chip mounted on a tab, a sealing resin that seals the tab and the semiconductor chip, and a lead exposed from the underside of the sealing resin and electrically connected to the semiconductor chip, characterized in that the tab and the end of the lead on the tab side are formed thinner than the other end of the lead. 8. A semiconductor device according to claim 1, 2 or 3, wherein the end of said lead on the tab side is formed thinner than the other end. 9. A semiconductor device according to claim 7, wherein said tab and the end of said lead on the tab side are thinned by half-etching. 10. A semiconductor device according to claim 7, wherein said tab and the end of said lead on the tab side are formed thin by coining. [Claim 11] A semiconductor device according to any one of claims 1 to 10, characterized in that the leads exposed from the sealing resin are plated with a Pb-Sn system, a Sn-Ag system, a Sn-Zn system, or Pd. 12. A plurality of leads; and a tab formed thinner than said plurality of leads.
a die bonding process for mounting a semiconductor chip on the tab of the lead frame; a wire bonding process for connecting the semiconductor chip and the plurality of leads of the lead frame with wires; a resin sealing process for sealing the lead frame, the semiconductor chip, and the wires with sealing resin so that the undersides of the plurality of leads are exposed; and a cutting process for obtaining a plurality of semiconductor devices by cutting the matrix lead frame into a plurality of unit lead parts near the sealing area sealed in the resin sealing process. 13. A method for manufacturing a semiconductor device according to claim 12, wherein the leads of said matrix lead frame are subjected to an exterior treatment. 14. A method for manufacturing a semiconductor device according to claim 13, wherein the exterior treatment is a Pd plating treatment. 15. A plurality of leads; and a tab formed thinner than said plurality of leads.
a die bonding process for mounting a semiconductor chip on the tab of the lead frame; a wire bonding process for connecting the semiconductor chip and the plurality of leads of the lead frame with wires; a resin sealing process for sealing the lead frame, the semiconductor chip, and the wires with sealing resin so that the undersides of the plurality of leads are exposed; an exterior processing process for performing exterior processing on the plurality of leads exposed from the sealing area sealed in the resin sealing process; and a cutting process for obtaining a plurality of semiconductor devices by cutting the matrix lead frame into a plurality of unit lead parts near the sealing area sealed in the resin sealing process. 16. A method for manufacturing a semiconductor device according to claim 12, 13, 14 or 15, wherein said resin sealing step is carried out by a transfer molding method. 17. A method for manufacturing a semiconductor device according to claim 12, 13, 14, 15 or 16, wherein said cutting step involves cutting using a cutting die. 18. A method for manufacturing a semiconductor device according to claim 12, 13, 14, 15 or 16, wherein the cutting step involves cutting with a dicing blade. 19. A method for manufacturing a semiconductor device according to claim 15, wherein the exterior treatment step is a plating treatment using a Pb--Sn system, a Sn--Ag system, a Sn--Zn system, or Pd. 20. A semiconductor device mounting structure, comprising: a mounting substrate; and a lead of the semiconductor device according to claim 1, 2, or 3, the other main surface of which is connected to the wiring of the mounting substrate by a bonding material. [Claim 21] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a support portion for supporting the tab and an exposed portion connected to the support portion and exposed on the surface of the sealing portion on which the semiconductor device is mounted, a plurality of tab suspension leads, the support portions being thinner than the exposed portions; a plurality of leads arranged around the tab and exposed on the surface of the sealing portion on which the semiconductor device is mounted; and connecting members connecting the surface electrodes of the semiconductor chip to the corresponding leads, wherein the plurality of tab suspension leads are connected via the tab. 22. A semiconductor device according to claim 21, wherein said exposed portion of said tab suspension lead is disposed at an end of said surface of said sealing portion on said semiconductor device mounting side. [Claim 23] A semiconductor device as described in claim 21, characterized in that the support portion of the tab hanging lead is covered with sealing resin and the exposed portion is located on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side, and the chip support surface of the tab and the surface of the tab hanging lead on the chip placement side are formed on the same flat surface. [Claim 24] A resin-sealed semiconductor device comprising: a tab that supports a semiconductor chip and is smaller than the semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead that supports the tab; a plurality of leads arranged around the tab and exposed on the surface of the sealing portion that is the semiconductor device mounting side; and a connecting member that connects the surface electrodes of the semiconductor chip to the corresponding leads, wherein the tab and the semiconductor chip are joined at a location inside the surface electrodes of the semiconductor chip. [Claim 25] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a plurality of leads arranged around the tab and exposed on the surface of the sealing portion on which the semiconductor device is mounted, the leads having a thick portion forming a step in the thickness direction and a thinner portion; and a connecting member for connecting the surface electrode of the semiconductor chip to the corresponding lead. 26. A semiconductor device according to claim 25, wherein the thick portion of the lead is exposed at the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side, and the thin portion is covered with sealing resin. [Claim 27] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a plurality of tab hanging leads each comprising a support portion for supporting the tab and an exposed portion connected to the support portion and exposed on the surface of the sealing portion on which the semiconductor device is mounted, the support portion being thinner than the exposed portion; a plurality of leads arranged around the tab and exposed on the surface of the sealing portion on which the semiconductor device is mounted, the leads having a thick portion forming a step in the thickness direction and a thinner portion; and a connecting member connecting the surface electrodes of the semiconductor chip to the corresponding leads, wherein the plurality of tab hanging leads are connected via the tab. 28. A semiconductor device according to claim 27, wherein said exposed portion of said tab suspension lead and said thick portion of said lead are formed to have the same thickness. [Claim 29] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a plurality of leads arranged around the tab and exposed on the surface of the sealing portion on the semiconductor device mounting side; and a connecting member for connecting the surface electrodes of the semiconductor chip to the corresponding leads, wherein a notch is provided at the tip of the tab suspension lead side of one of the plurality of leads that is arranged adjacent to the tab suspension lead, forming a gap along the notch between the tab suspension lead and the lead. [Claim 30] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab and having an exposed portion exposed at the end of the surface of the sealing portion on which the semiconductor device is mounted; a plurality of leads arranged around the tab and having connected portions exposed at the peripheral portion of the surface of the sealing portion on which the semiconductor device is mounted; and connecting members for connecting the surface electrodes of the semiconductor chip to the corresponding leads, wherein the length of the exposed portion of the tab suspension lead in the extension direction is formed shorter than the length of the connected portion of the lead in the extension direction. [Claim 31] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a plurality of leads arranged around the tab, each having an extending portion arranged close to the tab toward the center of the tab and a connected portion exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and a connecting member for connecting the surface electrode of the semiconductor chip to the corresponding extending portion of the lead, wherein the extending portion of the lead is formed thinner than the connected portion and is covered with sealing resin, and a groove portion is formed on the surface of the connected portion opposite to the exposed side arranged within the sealing portion. [Claim 32] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab hanging lead for supporting the tab; a connected portion exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and a thin portion formed at the end on the tab side and thinner than the connected portion, a plurality of leads having grooves on the surface opposite to the exposed side that is placed within the sealing portion of the connected portion; and a connecting member that connects the surface electrode of the semiconductor chip to the connected portion of the corresponding lead, wherein the thin portion of the lead is covered with sealing resin and the connecting member is joined to the connected portion inside the groove. [Claim 33] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a connected portion exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and a thin portion formed at the end on the tab side so as to be thinner than the connected portion, and a plurality of leads having grooves on the surface opposite to the exposed side that is placed within the sealing portion of the connected portion; and a connecting member that connects the surface electrode of the semiconductor chip to the connected portion of the corresponding lead, wherein the thin portion of the lead is covered with sealing resin and the connecting member is joined to the connected portion outside the groove. [Claim 34] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a connected portion exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and a thin portion formed at the end on the tab side so as to be thinner than the connected portion, a plurality of leads having inner and outer grooves on the surface opposite to the exposed side placed within the sealing portion of the connected portion; and a connecting member for connecting the surface electrode of the semiconductor chip to the connected portion of the lead corresponding thereto, wherein the thin portion of the lead is covered with sealing resin, and the connecting member is joined to the connected portion between the outer groove and the inner groove. [Claim 35] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab suspension lead for supporting the tab; a plurality of leads each having a connected portion exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side, the connected portion having a plating layer and a groove portion formed on the surface opposite to the exposed side positioned within the sealing portion; and a connecting member for connecting the surface electrode of the semiconductor chip to the plating layer of the corresponding lead, wherein the groove portion can prevent plating from flowing when the plating layer is formed. [Claim 36] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab hanging lead for supporting the tab and having an exposed portion exposed at the end of the surface of the sealing portion on the semiconductor device mounting side and a thin portion spanning the inside and outside of the outer periphery of the sealing portion; a plurality of leads arranged around the tab and having connection portions exposed at the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and connecting members for connecting the surface electrodes of the semiconductor chip to the corresponding leads. [Claim 37] A resin-sealed semiconductor device comprising: a tab for supporting a semiconductor chip; a sealing portion formed by sealing the semiconductor chip with resin; a tab hanging lead for supporting the tab and having an exposed portion exposed at the end of the surface of the sealing portion on the semiconductor device mounting side and a groove portion spanning the inside and outside of the outer periphery of the sealing portion; a plurality of leads arranged around the tab and having connection portions exposed at the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; and connecting members for connecting the surface electrodes of the semiconductor chip to the corresponding leads. 38. A semiconductor device according to claim 36 or 37, wherein said thin portion or said groove portion is formed on the exposed surface of said tab hanging lead opposite to the chip placement side. 39. A semiconductor device according to claim 36, 37 or 38, wherein said thin portion or said groove portion is formed in an elliptical shape that is long in the extending direction of said tab hanging lead. 40. A semiconductor device according to claim 36, 37, 38 or 39,
The semiconductor device is characterized in that the thin portion or the groove portion of the tab hanging lead is surrounded by a side wall. [Claim 41] A method for manufacturing a resin-sealed semiconductor device, comprising the steps of: preparing a lead frame having a tab capable of supporting a semiconductor chip; a plurality of tab suspension leads each having a support portion for supporting the tab and an exposed portion connected to the tab, the support portion being thinner than the exposed portion; and a plurality of leads arranged around the tab; joining the tab to the semiconductor chip; connecting surface electrodes of the semiconductor chip to the corresponding leads with connecting members; wrapping a sealing resin around the surface of the tab opposite the chip support surface and covering the thin portions of the tab suspension leads with the sealing resin, arranging the plurality of leads and the exposed portions of the tab suspension leads on the surface on which the semiconductor device is mounted, and resin-molding the semiconductor chip to form a sealing portion; dividing the tab suspension leads at the exposed portions of the tab suspension leads,
and separating the leads from the frame of the lead frame. [Claim 42] A method for manufacturing a resin-sealed semiconductor device, comprising the steps of: preparing a lead frame having a tab that is smaller than a semiconductor chip and capable of supporting the same; a tab suspension lead that has a support portion that supports the tab and an exposed portion that is connected to the tab, the support portion being thinner than the exposed portion; and a plurality of leads arranged around the tab; joining the tab and the semiconductor chip at a location inside the surface electrodes of the semiconductor chip; connecting the surface electrodes of the semiconductor chip to the corresponding leads with connecting members; wrapping a sealing resin around the surface of the tab opposite the chip support surface and covering the thin portions of the tab suspension lead with the sealing resin, arranging the plurality of leads and the exposed portions of the tab suspension lead on the surface on which the semiconductor device is mounted, and resin-molding the semiconductor chip to form a sealing portion; dividing the tab suspension lead at the exposed portions of the tab suspension lead,
and separating the leads from the frame of the lead frame. [Claim 43] A method of manufacturing a resin-sealed semiconductor device, comprising the steps of: preparing a lead frame having a tab capable of supporting a semiconductor chip; a tab suspension lead having a support portion for supporting the tab and an exposed portion connected to the tab; and a plurality of leads arranged around the tab and having a thick portion and an even thinner portion forming a step in the thickness direction; joining the tab to the semiconductor chip; connecting surface electrodes of the semiconductor chip to the corresponding leads with connecting members; wrapping a sealing resin around the surface of the tab opposite the chip support surface and covering the thin portions of the leads and the supporting portions of the tab suspension lead with the sealing resin, arranging the thick portions of the plurality of leads and the exposed portions of the tab suspension lead on the periphery of the surface on which the semiconductor device is mounted, and resin-molding the semiconductor chip to form a sealing portion; dividing the tab suspension lead at the exposed portions of the tab suspension lead,
and separating the leads from the frame of the lead frame. [Claim 44] A method of manufacturing a resin-sealed semiconductor device, comprising the steps of: preparing a lead frame having a tab capable of supporting a semiconductor chip, a tab suspension lead supporting said tab, and a plurality of leads arranged around said tab and having inner and outer grooves on the surface opposite to the exposed side of the connected portion; joining said tab to said semiconductor chip; connecting a surface electrode of said semiconductor chip to a corresponding location between said inner and outer grooves on said connected portion of said lead using a connecting member; and wrapping a sealing resin around the surface of said tab opposite to the chip support surface,
A method for manufacturing a semiconductor device, comprising: a step of arranging the plurality of leads on a surface on which the semiconductor device is mounted and resin-molding the semiconductor chip to form a sealing portion; and a step of separating the tab hanging lead and the plurality of leads from a frame portion of the lead frame. [Claim 45] A method of manufacturing a resin-sealed semiconductor device, comprising the steps of: preparing a lead frame having a tab capable of supporting a semiconductor chip; a tab suspension lead that supports the tab and has an exposed portion and a groove portion; and a plurality of leads that are arranged around the tab and have connection portions that are exposed on the peripheral edge of the surface of the sealing portion on the semiconductor device mounting side; joining the tab and the semiconductor chip; connecting the surface electrodes of the semiconductor chip and the corresponding leads with connecting members; and wrapping sealing resin around the surface of the tab opposite the chip support surface,
a step of arranging the plurality of leads and the exposed portions of the tab suspension leads on the surface of the semiconductor device mounting side, and forming the sealing portion by resin-molding the semiconductor chip with the grooves of the tab suspension leads aligned with the outer periphery of the sealing portion; and dividing the tab suspension leads at the exposed portions of the tab suspension leads,
and separating the leads from the frame of the lead frame.