JPWO1999030239A1 - Storage device and access method - Google Patents

Abstract

(57) [Abstract] An address conversion table that stores the correspondence between logical addresses and physical addresses for accessing a memory cell array (1) and an empty block table that indicates the location of empty blocks are stored in any block of the memory cell array (1). When reading data from the memory cell array (1), the address conversion table stored in the memory cell array (1) is referenced to determine the physical address and the data is read. When writing data, an empty block is identified from the empty block table stored in the memory cell array (1) and the data is written to that empty block. Furthermore, the updated address conversion table and empty block table are written to another empty block.

Description

[Detailed Description of the Invention] Storage Device and Access Method Technical Field This invention relates to a storage device and an access method, and more particularly to a block-erasable storage device and an access method thereof.

BACKGROUND ART Block-erasable storage devices are known that include block-erasable storage media such as flash memory and read and write information under the control of a central processing unit (CPU) or a dedicated controller.

Block-erasable storage media refers to storage media in which the contents of the target area must be erased before data can be written, and erasure can only be performed in units (commonly called blocks) equal to or larger than the smallest unit of storage capacity handled by the write process (commonly called a page, segment, etc.).

To manage external access, block-erasing memory devices are equipped with a free block table that stores information indicating the locations of free blocks, and an SRAM (static random access memory) that stores an address translation table that stores information indicating the correspondence between logical addresses and physical addresses.

When a block-erasing storage device receives a write request, it searches for an empty block registered in the empty block table, writes the data to the found block, adds the correspondence between the physical address and logical address of that block to the address translation table, and then deletes the block from the empty block table.

Furthermore, when a block-erasing storage device receives a read request, it searches the address translation table using the logical address of the data to be read as a key to determine the physical address of the location where the data to be read is stored, and then reads the data from that location.

In such storage devices, the overall volume of the storage device increases by the volume occupied by the SRAM, etc. Therefore, when using such storage devices in applications requiring low volume, such as JEIDA/PCMCIA cards, it is necessary to devise ways to reduce the volume.

Additionally, SRAM consumes a lot of power, and using SRAM to store various tables increases the overall power consumption of the storage device, making it unsuitable for applications requiring low power consumption, such as JEIDA/PCMCIA cards.

DISCLOSURE OF THE INVENTION This invention was developed in consideration of the above-mentioned circumstances, and aims to provide a block-erasable memory device with a small volume and low power consumption, and an access method therefor.

To achieve the above object, a storage device according to a first aspect of the present invention comprises: storage means (1) including a plurality of memory blocks to which physical addresses are assigned; erasing means (1e) for collectively erasing data stored in the storage means by memory block; writing means (4X, 4B, 5, 20) for inputting data and a logical address, determining a storage location for the data within the storage means, and writing the data to the storage location; The storage means stores an address conversion table that stores information indicating the correspondence between the logical address and the physical address of the storage means; The writing means includes means (4X, 4B, 5, 20) for adding information indicating the correspondence between the physical address of the location where the data is written and the input logical address to the address conversion table or updating the address conversion table.

In a storage device with this configuration, the address translation table is stored in a storage means, which is a block-erasable storage medium. Therefore, there is no need to provide a storage medium such as an SRAM for storing the address translation table in addition to the storage means. This makes it possible to provide a block-erasable storage device with a relatively small volume and low power consumption.

The storage device may further include reading means (4X, 4B, 5, 20) consisting of: means (20) for storing the physical address of the block in which the address conversion table is written; physical address reading means (4X, 4B, 5, 20) for accessing the block in which the address conversion table is stored and reading a physical address corresponding to the logical address of the data to be read; means (4X, 4B, 5, 20) for reading and outputting data stored at the physical address read by the physical address reading means.

This reading means can determine the physical address of the data to be read from the address conversion table stored in the storage means and read it out.

The storage means may also store a free block table that stores information indicating free blocks that do not store data.

With this configuration, the amount of memory used, such as SRAM, in addition to the storage means can be further reduced, leading to smaller volume and lower power consumption.

The free block table that stores the information about the free blocks that existed before the information was written to the free blocks is then deleted, and the free block table that stores the information about the free blocks that remain after the information is written to the free blocks by the free block writing means is stored in the storage means. This updates the free block information contained in the free block table, making it possible to obtain the latest free block information at any time.

The storage means may be configured, for example, with multiple flash memory chips. In this case, the address translation table (and the free block table) may be stored in any one block of the flash memory of any one of the chips. A means for storing information indicating which block of which chip the address translation table and free block table are stored may then be provided.

The storage means stores, for example, the address translation table and the free block table in one block.

This configuration allows for efficient use of the storage capacity of the memory means by limiting the number of blocks required to store the address translation table and free block table to one. It also simplifies the management of the storage locations of these tables.

A second aspect of the present invention provides a storage device comprising: storage means (1) including a plurality of memory blocks to which physical addresses are assigned; erasing means (1e) for erasing data stored in the storage means in units of memory blocks at once; writing means (4X, 4B, 5, 20) for inputting data to be written and a logical address, determining a storage location for the data within the storage means, and writing the data to the storage location; wherein the storage means stores free block information indicating free blocks that do not store the data; wherein the writing means writes the data to the free blocks indicated by the free block information.

According to this configuration, free block information is stored in the storage means, which is a block-erasing storage medium. Therefore, there is no need to provide another storage medium, such as an SRAM, for storing free block information in addition to the storage means. This makes it possible to provide a block-erasing storage device that is relatively small in volume and consumes low power.

Furthermore, if the writing means further includes means (1e, 4 X, 4B, 5, 20) for updating the free block information stored in the storage means to free block information representing the free block information remaining after the data is written to the free block by the writing means, the free block information is updated, and the latest free block information can be obtained at any time.

The free block information may be stored in a portion of each free block and may consist of chain information registered in a chain to point to another free block. In this case, the writing means may include means (4X, 4B, 5, 20) for identifying a free block according to the chain information and writing the data to that free block.

This configuration eliminates the need to use a single block to store the free block table, resulting in more efficient use of storage media. Furthermore, since the target block for writing is identified based on free block chain information, the frequency of use of each block can be evened out.

When the free block information is constructed from chain information, a first free block storage means (20) for storing the address of the first free block may be provided, and data may be written to the free block assigned the physical address stored therein, and the contents of the first free block storage means may be updated with the chain information registered in the block to which the data has been written.

When the storage means is configured with a flash memory or the like, the storage area is configured with a data area and a redundant area. In this case, the chain information can be stored in the redundant area.

In such a storage device, the chain information is written to the redundant area of an empty block, and the data is written over the empty block to which the chain information is already written.

In this case, the data area and the redundant area are arranged so that they do not overlap each other within the storage area, so that the chain information is not destroyed even when the data is overwritten.

In the storage device according to the second aspect, the storage means may also be configured, for example, by a multi-chip flash memory.

In this case, the chain information may be configured by information indicating in which block of which chip the next free block is stored.

Furthermore, a third aspect of the present invention relates to an access method for a block-erasing memory, which allows data to be erased in blocks and write data to free blocks from which data has been previously erased. The method stores an address conversion table in the memory, which indicates the correspondence between physical addresses assigned to the memory and the logical addresses of the data. When data to be written and its logical address are supplied, the method uses the address conversion table to determine whether data has already been written to the logical address. If data exists, the method identifies a free block and writes the data to the free block while erasing the block containing the old data. If data does not exist, the method identifies a free block and writes the data to the free block. Next, the method adds or updates information indicating the correspondence between the physical address of the block to which the data has been written and the logical address to the address conversion table in the memory. When the logical address of the data to be read is supplied, the address translation table in the memory is accessed to determine the physical address where the data is stored, and the data is read from that physical address and output.

Furthermore, a fourth aspect of the present invention relates to an access method for a block-erasing memory in which data can be erased in blocks and data can be written to free blocks from which data has been previously erased. The method includes storing a free block table indicating free blocks in the memory, and when data to be written is supplied, identifying a free block based on the free block table in the memory and writing the data to the identified free block.

According to the access methods of the third and fourth aspects, part of the memory can be used as an address translation table or free block table, eliminating the need for additional memory such as SRAM to store these tables, thereby contributing to smaller capacity and lower power consumption.

Furthermore, a fifth aspect of the present invention relates to an access method for a block-erasing memory that allows data to be erased in blocks and data to be written to free blocks from which data has been previously erased. The method includes: storing free block information indicating free blocks in the memory in a block of the memory; and, when data to be written is supplied, identifying a free block based on the free block information, writing the data to the identified free block; identifying a new free block based on the free block information; erasing the contents of the block storing the free block information; and writing the updated free block information to the newly identified free block.

According to the access method of the fifth aspect, part of the memory can be used as an address translation table or free block table, thereby reducing capacity and power consumption. Furthermore, by updating the free block information, the latest free block information can be obtained at any time.

Furthermore, a sixth aspect of the present invention relates to an access method for a block-erasing memory in which data can be erased in blocks and data can be written to free blocks from which data has been previously erased. The method includes: storing free block chain information, consisting of information sequentially indicating other free blocks, in a portion of each free block of the memory; and, when data to be written is supplied, determining the first free block in the chain of free blocks defined by the free block chain information, and writing the data to the determined free block.

According to the access method of the sixth aspect, a part of the memory can be used as a free block table.

In addition, since the blocks to which data is written are in the order of the chain defined by the chain information, the write frequency can be made uniform across the entire memory.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing the basic configuration of a storage device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of a memory cell array.

FIG. 3 is a diagram showing the logical structure of a storage area.

FIG. 4 is a diagram illustrating an example of the configuration of the free block table.

FIG. 5 is a diagram showing an example of the configuration of the address conversion table.

FIG. 6 is a flowchart showing the process of reading data.

FIG. 7 is a flowchart showing the process of determining a physical address.

FIG. 8 is a flowchart showing the write process.

FIG. 9 is a flowchart showing the process of erasing old data.

FIG. 10 is a flowchart showing the process of updating the free block table and the address translation table.

FIG. 11 is a conceptual diagram showing a chain of free blocks in a storage device according to the second embodiment.

FIG. 12 is a flowchart of a data write process in the storage device according to the second embodiment.

FIG. 13 is a flowchart showing the process of updating free block information and the address translation table in the storage device according to the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION The following describes a storage device according to the best mode for carrying out the present invention.

(First Embodiment) The storage device according to this embodiment stores address translation tables and other data in the flash memory unit itself. As shown in Figure 1, it is composed of a flash memory unit 10 and a controller 20.

The flash memory unit 10 comprises a memory cell array 1, an I/O buffer 2, an X-address buffer 3X, a block address buffer 3B, an X-address decoder 4X, a block address decoder 4B, a control circuit 5, and a global buffer 6.

Memory cell array 1 is composed of multiple memory cells. Each memory cell is, for example, a NAND type, and has a storage capacity of 1 byte. These memory cells are logically arranged in a matrix of 16,384 rows and 528 columns, as shown in Figure 2. Therefore, memory cell array 1 has an overall storage capacity of 8.65 MB.

The memory cell array 1 includes eight data input/output terminals Tdata, 16,384 row control input terminals Trowcont commonly connected to memory cells in corresponding rows, a read control terminal Treadcont and a write control terminal Twritecont common to all memory cells, and an erase control circuit 1e for erasing data.

When a control signal is input to the read control terminal Treadcont of memory cell array 1, if a control signal is supplied to the row control input terminal Trowcont, the memory cells in the row to which the control signal is supplied output their stored contents to the data input/output terminal Tdata in 528 increments, one memory cell at a time (i.e., one byte) from the beginning.

On the other hand, when a control signal is input to the write control terminal Twritecont, the data input from the data input/output terminal Tdata is divided into 528 byte chunks and stored starting from the first memory cell.

However, because each memory cell is a NAND type, data can only be written in the direction of changing the stored value from "1" to "0." Once a memory cell has a stored value of "0," it will maintain that state until its contents are reset.

As shown in Figure 2, each row of the memory cell matrix constitutes a page with a storage capacity of 528 bytes. The pages are assigned consecutive page addresses ranging from 1 to 16384, and the memory cells contained in each page are assigned consecutive addresses ranging from 1 to 528.

As shown in Figures 2 and 3, each page is organized into a block, with 16 pages from the beginning. Each block has a storage capacity of 8 kilobytes, and the entire storage area is composed of 1,024 blocks.

As shown in Figure 3, each page consists of a data area occupying the first 512 bytes and a redundant section occupying the last 16 bytes. The data area stores the original data, while the redundant section stores error check codes and other information.

When a control signal instructing the data erase control circuit 1e to erase data from a specific block is input, the contents of all memory cells in that block are reset (i.e., the value stored in each memory cell becomes "1").

The memory cell array 1 stores an empty block table and an address conversion table for accessing the memory cell array 1.

The free block table is stored in the first page of any block in the memory cell array 1 and contains information indicating which of the blocks in the memory cell array 1 are free blocks (i.e., blocks that are in a reset state and do not contain memory cells storing data "0"). Information about the blocks in which the free block table is stored is stored in the control circuit 5, as described below.

An example of the structure of the free block table when the total number of blocks in memory cell array 1 is 1024 is shown in Figure 4. This free block table is composed of the first 128 bytes of memory cells (i.e., the first 1024 bits) of a particular block, and has a one-to-one correspondence from the first bit to blocks 1 through 1024. If the corresponding block is a free block, it stores a "1," and if it is not a free block, it stores a "0."

The address translation table is stored in the second page or later of the block in which the free block table is stored, and stores information representing the logical addresses assigned to each block of the memory cell array 1.

A logical address is a unit recognized as a unit of data read/write by the CPU (Central Processing Unit) 12 of the external computer 11 (described below) and the controller 20 when this storage device is read or written using the operations described below.

The total area allocated to the logical addresses is a predetermined value smaller than the storage capacity of the memory cell array 1, e.g., 16,000 pages, and the storage area occupied by each logical address is, for example, equal to the storage area occupied by one page.

Specifically, a logical address is composed of a virtual memory area of a size (e.g., 16,000 pages) that is smaller than the memory capacity of the memory cell array 1, divided into 512-byte sections, and each section is assigned a consecutive number starting from 0. The logical address is then composed of the consecutive numbers, i.e., LBAs (Logic Block Addresses).

An example of the structure of an address translation table is shown in Figure 5. The address translation table consists of multiple records, each of which contains a logical address at the beginning, followed by the block number (block address) in which the first page of the area associated with that logical address is located, and the number of that first page.

As shown in FIG. 1, the I/O buffer 2 is connected to the global buffer 6, the data input/output terminal Tdata of the memory cell array 1, and the control circuit 5.

In accordance with instructions from the control circuit 5, the I/O buffer 2 outputs the data stored in the global buffer 6 to the data input/output terminal Tdata of the memory cell array 1 one byte at a time, and outputs the data output from the data input/output terminal Tdata to the global buffer 6 one byte at a time.

The X-address buffer 3X receives a row address signal indicating the row address (i.e., page address) of the memory cell array 1 from the global buffer 6 and outputs it to the X-address decoder 4X.

The X address decoder 4X supplies an active-level control signal to the row control input terminal Trowcont of the row indicated by the row address signal or the row indicated by the control circuit 5.

The block address buffer 3B receives a block address signal indicating the address of each block of the memory cell array 1 from the global buffer 6 and outputs the signal to the block address decoder 4B.

The block address decoder 4B supplies an erase control circuit 1e with a signal instructing the erase control circuit 1e to erase data in a block indicated by the block address signal or in a block instructed by the control circuit 5.

The control circuit 5 receives and analyzes commands from the global buffer 6, and controls the X-address buffer 3X, the X-address decoder 4X, the block address decoder 4B, and the I/O buffer 2 in accordance with the analysis results.

The control circuit 5 also receives a write signal Swrite and a latch signal Slatch from the controller 20. In accordance with these signals, the control circuit 5 controls the memory cell array 1 and the global buffer 6 as described below. The control circuit 5 also supplies a busy signal Sbusy and a ready signal Sready to the controller 20 at timings described below.

Furthermore, when the data stored in the global buffer 6 represents a predetermined command such as a setup command or an erase command, which will be described later, the control circuit 5 executes the processing indicated by the command, as will be described later.

The busy signal Sbusy and the ready signal Sready may be transmitted via the same signal line. Therefore, for example, when the control circuit 5 applies a voltage representing a binary logic value "1" to a specific signal line, it may be considered that the control circuit 5 is supplying the busy signal Sbusy, and when it applies a voltage representing a binary logic value "0," it may be considered that the control circuit 5 is supplying the ready signal Sready.

The global buffer 6 is connected to the I/O buffer 2, the control circuit 5, and the controller 20. In response to a control signal output from the control circuit 5, the global buffer 6 stores the signals on the bus line 13 and the contents stored in the I/O buffer 2 that are currently being supplied at the time the control signal is received, and outputs the stored contents to the X address buffer 3X or the control circuit 5.

The controller 20, which includes a CPU and the like, is connected to the control circuit 5 of the flash memory unit 10 and is also connected to the global buffer 6 of the flash memory unit 10 and the CPU 12 of the computer 11 via a bus line 13. However, the CPU constituting the controller 20 may be the same as the CPU 12 of the computer 11.

In response to commands provided by the CPU 12 or the like of the external computer 11, the controller 20 supplies a write signal Swrite and a latch signal Slatch to the control circuit 5, and supplies a physical address, data to be written, commands, etc. to the global buffer 6, thereby controlling the flash memory unit 10, as described below.

The controller 20 also stores data indicating the positions of the address translation table and free block table, and the position of the last written block, and references the stored data when executing the processing described below in accordance with commands supplied from the CPU 12. When the controller 20 receives from the CPU 12 the amount of data to be read, expressed in bytes (i.e., the number of bytes), it stores this information and references it in the processing described below.

(Operation of the First Embodiment) Next, the process of writing data to this storage device will be described with reference to Figures 6 through 10.

FIG. 6 is a flowchart showing the process of reading data.

FIG. 7 is a flowchart showing the process of determining a physical address.

FIG. 8 is a flowchart showing the write process.

FIG. 9 is a flowchart showing the process of erasing old data.

FIG. 10 is a flowchart showing the process of updating the free block table and the address translation table.

(Data Reading) When reading data from this storage device, the CPU 12 in the computer 11 executes the data reading process shown in Figure 6.

When the process starts, the CPU 12 outputs the logical address at which the data to be read is stored onto the bus line 13, and supplies the controller 20 with a command to read the data and the page number of the storage area where the data to be read is stored (FIG. 6, step S101).

In response to the command from the CPU 12, the controller 20 acquires the logical address and page number supplied via the bus line 13 and stores both (step S102).

The controller 20 then supplies the physical address of the first page of the address translation table to the global buffer 6, sends a latch signal Slatch to the control circuit 5, and waits for a ready signal Sready to be supplied from the control circuit 5 (step S103).

In response to the latch signal Slatch from the controller 20, the control circuit 5 begins supplying a busy signal Sbusy to the controller 20 and sends an instruction to the global buffer 6 to latch the physical address supplied by the controller 20. In response to this instruction, the global buffer 6 latches the physical address supplied by the controller 20 (step S104). Of the physical address latched in the global buffer 6, the block address portion is supplied to the block address decoder 4B via the block address buffer 3B, and the page address portion is supplied to the X address decoder 4X via the X address buffer 3X.

To read the address conversion table, the control circuit 5 instructs the X address decoder 4X, which receives a page address from the global buffer 6, to select the page indicated by the page address.

In response to an instruction from the control circuit 5, the X address decoder 4X outputs an active-level control signal to the row control input terminal Trowcont of the page in which the address translation table is stored. This selects the page of the address translation table designated by the controller 20.

Next, the control circuit 5 sends a data read instruction to the read control terminal Treadcont of the memory cell array 1, stops the supply of the busy signal Sbusy, and supplies a ready signal Sready to the controller 20. Meanwhile, in response to the instruction sent from the control circuit 5, the memory cell array 1 sequentially outputs the memory contents of the corresponding page of the address translation table to the controller 20, one byte at a time, via the I/O buffer 2 and the global buffer 6.

Meanwhile, the controller 20 sequentially reads the information supplied from the global buffer 6, thereby reading each logical address stored in the page and the physical address associated with each logical address (step S105).

The controller 20 then determines whether or not any of the logical addresses read from the address conversion table matches the logical address obtained from the CPU 12 in step S102 (step S106).

If it is determined in step S106 that there is no matching logical address, the controller 20 supplies the physical address of the next page of the address translation table to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S107), and the storage device returns the process to step S104.

On the other hand, if it is determined in step S106 that a matching logical address exists, the process proceeds to step S108.

In step S108, the controller 20 supplies the value of the physical address indicated by the logical address determined to match in step S106 (i.e., the physical address of the first page of the pages containing the data to be read) to the global buffer 6 and sends a latch signal Slatch to the control circuit 5.

The flash memory unit 10 then performs substantially the same processing as that performed when responding to the latch signal Slatch supplied by the controller 20 in step S103, and sequentially supplies the contents of the physical address supplied by the controller 20 to the global buffer 6 (i.e., the contents of the first page of the data to be read that has not yet been read) to the controller 20, byte by byte, via the global buffer 6 (step S109).

Meanwhile, in step S109, the controller 20 sequentially reads the information supplied by the global buffer 6 to read the data to be read, and supplies the read data to the CPU 12 via the bus line 13 (step S110).

The controller 20 then determines whether the number of pages read since the start of the process in step S108 has reached the number of pages supplied from the CPU 12 and stored by itself in step S102 (step S111).

If it is determined that the address has not been reached, the controller 20 supplies the next physical address containing the data to be read to the global buffer 6 at the timing when the control circuit 5 stops supplying the busy signal Sbusy, and sends a latch signal Slatch to the control circuit 5 (step S112).Then, the storage device returns to step S109.

On the other hand, if it is determined that the count has been reached, the controller 20 notifies the CPU 12 of the end of reading by, for example, sending an end code to the CPU 12 via the bus line 13 or outputting a control signal (not shown) to the CPU 12 (step S113).

When the CPU 12 detects the end of the read operation (step S114), it ends the data read operation.

By the processing of steps S101 to S114, the location of the physical address corresponding to the logical address is searched for using the address conversion table stored in the memory cell array 1 itself, and the data at that location is sequentially read out.

If there are multiple logical addresses to be read, steps S101 to S114 are repeated the same number of times as the number of logical addresses to be read.

(Data Write: Determining a New Physical Address) When writing data to memory cell array 1, this storage device first performs the physical address determination process shown in Figure 7 to determine the physical address to which the data will be written.

For example, the CPU 12 first calculates the number of pages required for writing based on the size of the data to be written, assuming that one page has a storage capacity of 512 bytes, and then determines the logical address to which the data will be written.

The CPU 12 then outputs the logical address with the smallest number among the logical addresses to be written onto the bus line 13 and sends a command to the controller 20 to write the data (step S201).

In response to the command sent from the CPU 12 in step S201, the controller 20 performs substantially the same processing as steps S103 to S107 in the processing of FIG. 6 (step S202).

That is, the contents of the address translation table are read from the flash memory unit 10, and by sequentially determining whether any of the read contents match the logical address obtained from the CPU 12 in step S201, the physical address associated with the logical address obtained from the CPU 12 is identified.

Once the physical address is identified in step S202, the controller 20 stores the identified physical address (step S203). Then, to read the free block table, the controller 20 supplies the physical address of the free block table to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S204).

The control circuit 5 causes the X address decoder 4X to select a page with an empty block table, in the same manner as when the latch signal Slatch is supplied in step S103.

When a page is selected, the control circuit 5 sends a data read instruction to the read control terminal Treadcont of the memory cell array 1. Upon receiving the instruction, the memory cell array 1 sequentially outputs the contents of the page in the free block table, one byte at a time, to the controller 20 via the I/O buffer 2 and the global buffer 6.

The controller 20 then sequentially reads the information provided by the global buffer 6 to obtain the free block table (step S205).

Next, the controller 20 identifies a physical address belonging to any free block based on the contents of the acquired free block table (step S206), and thereafter determines that the physical address identified in step S206 will be treated as the physical address indicated by the logical address to be written.

However, in step S206, after the process of FIG. 7 is started, a physical address already identified in step S206 is not identified again.

Furthermore, in step S206, the block to which the physical address identified in step S206 belongs after the start of the process of FIG. 7 is treated as a free block even after data is written to that physical address.

Furthermore, a physical address to which no logical address is assigned may be selected as the physical address to which data is to be written.

(Data writing: writing to flash memory) After completing step S206, the controller 20 executes the write process shown in Figure 8.

That is, after the controller 20 identifies the physical address through the processing of step S206, it supplies the identified physical address to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S211).

In response to the latch signal Slatch, the control circuit 5 stops supplying the busy signal Sbusy and starts supplying the ready signal Sready to the controller 20. Then, the X address decoder 4X selects the physical address identified in step S206.

Meanwhile, in response to the ready signal Sready, the controller 20 requests the CPU 12 to supply the data to be written (step S212). In response to this request, the CPU 12 supplies the first byte of the data to be written to the controller 20 via the bus line 13.

The controller 20 then stores the data to be written, which is supplied from the CPU 12 via the bus line 13, supplies it to the global buffer 6, and sends a write signal Swrite to the control circuit 5 (step S213).

In response to the write signal Swrite, the control circuit 5 instructs the global buffer 6 to latch the data to be written that has been supplied to the global buffer 6, stops supplying the ready signal Sready, and resumes supplying the busy signal SBusy to the controller 20. The global buffer 6 latches the data on the bus line 13 and stores it in the I/O buffer 2.

Next, the control circuit 5 instructs the I/O buffer 2 to output the data stored in the I/O buffer 2 to the data input/output terminal Tdata. In response to the instruction, the I/O buffer 2 outputs the data stored in itself by the global buffer 6 to the data input/output terminal Tdata.

Next, the control circuit 5 outputs an active-level write control signal to the write control terminal Twritecont to cause the memory cell array 1 to store the data currently input to the data input/output terminal Tdata. In response to the write control signal, the memory cell array 1 records the data input to the data input/output terminal Tdata in the first memory cell of the currently selected page.

After outputting an active-level write control signal to the write control terminal Twritecont of the memory cell array 1, the control circuit 5 stops supplying the busy signal Sbusy and resumes supplying the ready signal Sready to the controller 20. When the controller 20 detects the resumption of supply of the ready signal Sready, it proceeds to step S214.

In step S214, after sending a signal requesting subsequent data, the controller 20 refers to the value of the byte counter and determines whether 512 bytes of data have been written to the currently selected page.

Then, when it is determined that 512 bytes have been written, the controller 20 requests the CPU 12 to send the next logical address (step S215).

Then, the CPU 12 sends the next logical address onto the bus line 13. When the controller 20 acquires that logical address, the controller 20 treats that logical address as having been acquired in step S201, and the process returns to step S202 in the process of FIG. 7.

On the other hand, if it is determined that 512 bytes have not been written, the controller 20 sends a signal to the CPU 12 requesting subsequent data to be written (step S216).

In response to this signal, the CPU 12 determines whether there is subsequent data to be written. If there is no subsequent data, the CPU 12 supplies a control code indicating the end of writing to the bus line 13. On the other hand, if there is subsequent data, the CPU 12 supplies the subsequent one byte of data to the bus line 13.

After sending a signal requesting subsequent data in step S216, when the controller 20 receives subsequent data or a control code indicating the end of writing from the CPU 12, the controller 20 determines whether the received code is a control code indicating the end of writing (step S217).

If the controller 20 determines that the control code is not the relevant one, the process returns to step S213. If the controller 20 determines that the control code is the relevant one, the process proceeds to the old data erasure process shown in FIG. 9.

The method by which the CPU 12 notifies the controller 20 that there is no data to be written may be any method, and is not limited to sending a control code via the bus line 13. For example, the CPU 12 may send a control signal indicating that there is no data to be written to the controller via any other control line.

(Data Write: Old Data Erase) Upon receiving the write completion control code, the controller 20 executes the old data erase process shown in Figure 9.

When the process of FIG. 9 begins, the controller 20 first identifies a physical address belonging to the same block as the physical address stored by itself in step S203 (i.e., the old physical address that was associated with the logical address to be written until the new physical address was associated in step S206) based on the contents of the address conversion table that has already been read (step S221).

The storage device then determines that each of the physical addresses identified in step S221 represents the first page of the data to be read, and performs data read for each of these physical addresses according to the processing of steps S108 to S114 of Figure 6 (step S222).The controller 20 then performs processing substantially identical to the processing of steps S204 to S206 to identify the physical address at which the data read in step S222 will be stored (step S223).

However, in step S223, the physical address for storing the data is determined not to be a physical address belonging to the same block as the block in which the read data was stored.

Next, the storage device writes the data read in step S222 to the physical address identified in step S223 according to the process of FIG. 8 (step S224).

Next, the controller 20 supplies the global buffer 6 with a predetermined setup command for specifying the block from which the stored contents are to be erased, and sends a latch signal Slatch to the control circuit 5 (step S225).

When the latch signal Slatch is supplied in step S225, the control circuit 5 detects that the data supplied to the global buffer 6 is a setup command, and determines that the next data to be supplied to the global buffer 6 should be treated as the block address of the block to be erased.

Next, the controller 20 supplies the global buffer 6 with the block address of the block from which the stored contents are to be erased (i.e., the block to which the physical address stored by the controller 20 in step S203 belongs), and sends a latch signal Slatch to the control circuit 5 (step S226).

In response to the latch signal Slatch supplied in step S226, the control circuit 5 sends an instruction to the global buffer 6, causing the global buffer 6 to latch the block address supplied by the controller 20. The block address latched by the global buffer 6 is supplied to the block address decoder 4B via the block address buffer 3B, thereby selecting the block whose stored contents are to be erased.

Next, the controller 20 supplies a predetermined erase command to the global buffer 6 to erase the stored contents, and sends a latch signal Slatch to the control circuit 5 (step S227).

When the latch signal Slatch is supplied in step S227, the control circuit 5 detects that the data supplied to the global buffer 6 is an erase command and instructs the block address decoder 4B to erase the contents of the selected block.

Upon receiving the instruction, the block address decoder 4B sends a signal to the erase control circuit 1e instructing it to erase the data in the block selected for erasure. This erases the recorded contents of that block.

By processing steps S221 to S227, the data recorded in memory cell array 1 is erased, and the data stored in the same block as the erased data is saved to another page.

Note that the process of erasing old data does not necessarily have to be performed after the write process. Therefore, for example, after determining the physical address to which data is to be written, the contents of the block containing the old physical address that was associated with the new logical address associated with that physical address may first be erased, and then new data may be written to the physical address to which data is to be written.

Furthermore, data erasure is not limited to being performed as part of the data writing process, as in steps S221 to S227 described above.

Therefore, data may be erased without writing new data.

Specifically, for example, the CPU 12 first sends a command to the controller 20 instructing the controller 20 to erase data, and then supplies the logical address of the data to be erased to the controller 20 via the bus line 13.

In response to the command, the controller 20 performs the same processing as steps S201 to S203 of the processing in FIG. 7 to identify the physical address indicated by the logical address of the data to be erased (i.e., the physical address of the data to be erased).

The controller 20 then treats the identified physical address to be erased as the physical address identified in step S203, and performs the processing of steps S221 to S227 described above. As a result, the recorded contents of the block to which the physical address to be erased belongs are erased.

In the above-described data write process, when specifying a new physical address to write to, the controller 20 may specify that the data be written sequentially to blocks following the free block to which data was last written, and if there are no free blocks following that, then the data be written sequentially to free blocks following the first block.

This allows free blocks to be written to cyclically, preventing data updates to specific blocks from becoming too frequent, thereby preventing performance degradation in specific blocks.

(Updating the Free Block Table and Address Translation Table) Once the data erasure and writing are completed through the above process, the controller 20 initiates the process shown in Figure 10 to update the free block table and address translation table.

In the process shown in FIG. 10, first, in order to update the free block table, the controller 20 performs substantially the same process as steps S201 to S205 in FIG. 7 to obtain the free block table from the flash memory unit 10 and temporarily stores the free block table (step S301).

Next, based on the contents of the temporarily stored free block table, the controller 20 identifies one free block into which to write the free block table and address translation table, and stores the first page of that block (step S302).

The controller 20 then converts bits in the temporarily stored free block table that indicate free blocks into which data has been written and free blocks identified in step S302, and bits that indicate blocks to which physical addresses identified in steps S206 and S223 belong, from "1" to "0." The controller 20 also converts bits that indicate blocks in which the free block table and address conversion table currently exist, and bits that indicate blocks whose recorded contents were erased in step S227, from "0" to "1" (step S303).

Next, the controller 20 supplies the physical address of the first page of the free block identified in step S302 to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S304).

In response to the latch signal Slatch, the control circuit 5 stops supplying the busy signal Sbusy and starts supplying the ready signal Sready to the controller 20. Then, the control circuit 5 causes the X address decoder 4X to select the physical address supplied from the controller 20 to the global buffer 6.

Meanwhile, in response to the ready signal Sready, the controller 20 supplies the first byte of the free block table converted in step S303 to the global buffer 6 (step S305) and sends a write signal Swrite to the control circuit 5 (step S306).

In response to the write signal Swrite, the control circuit 5 causes the global buffer 6 to latch the data supplied from the controller 20 to the global buffer 6, stops supplying the ready signal Sready, and resumes supplying the busy signal SBusy to the controller 20. The global buffer 6 latches the data on the bus line 13 and stores it in the I/O buffer 2.

Next, the control circuit 5 causes the I/O buffer 2 to supply the data stored in the I/O buffer 2 to the data input/output terminal Tdata, and supplies an active-level write control signal to the write control terminal Twritecont, causing the data supplied to the data input/output terminal Tdata to be written into the first memory cell of the currently selected page.

Then, the control circuit 5 stops supplying the busy signal Sbusy and resumes supplying the ready signal Sready to the controller 20.

When the controller 20 detects the resumption of the supply of the ready signal Sready, it determines whether any portion of the free block table temporarily stored in itself remains that has not yet been supplied to the flash memory unit 10 (step S307).

If it is determined that there are remaining free blocks, the controller 20 supplies the next byte of the free block table that it temporarily stores to the global buffer 6 (step S308), and then proceeds to step S306.

On the other hand, if it is determined that no more pages remain, the controller 20 supplies the physical address of the first page of the address conversion table to the global buffer 6 in order to update the address conversion table, supplies a latch signal Slatch to the control circuit 5, and waits for a ready signal Sready to be supplied from the control circuit 5 (step S309).

Then, in the same manner as when the latch signal was supplied in step S103, the flash memory unit 10 stops supplying the busy signal Sbusy, supplies the ready signal Sready to the controller 20, and supplies the memory contents of the page of the address translation table designated by the controller 20 to the controller 20.

Meanwhile, the controller 20, similar to step S105, reads from the flash memory unit 10 each logical address stored in the page corresponding to the physical address provided by the controller 20, and the physical address associated with each logical address, and temporarily stores them (step S310).

Next, the controller 20 determines whether any of the temporarily stored logical addresses matches a logical address that it has stored as a target for which the physical address assignment should be changed (step S311).

If it is determined that there is no match, the controller 20 proceeds to step S313. If it is determined that there is a match, the controller 20 converts the physical address temporarily stored in itself that is associated with the logical address determined to match into a physical address that should be newly associated with that logical address (step S312), and proceeds to step S313.

For example, in step S311, the logical address supplied by the CPU 12 to the controller 20 as the target for data writing is determined to match the logical address stored by the controller 20 as the target for which the physical address assignment should be changed. Then, in step S312, the physical address indicated by that logical address is converted from the old physical address identified in step S202 to the new physical address identified in step S206.

Next, the storage device performs substantially the same processing as steps S301 to S308, thereby writing the portion of the address translation table that it temporarily stores, equivalent to one page, to the page of memory cell array 1 next to the page that was most recently written to since the start of the processing of FIG. 10 (step S313).

When writing is complete, the controller 20 determines whether writing of the address translation table is complete by determining whether the number of pages written in step S313 is equal to the total number of pages in the address translation table (step S314).

If it is determined that the process is complete, the process proceeds to step S316. If it is determined that the process is not complete, the physical address of the next page in the address translation table is supplied to the global buffer 6, a latch signal Slatch is sent to the control circuit 5 (step S315), and the process returns to step S310.

In step S316, the controller 20 stores the updated positions of the free block table and the address translation table.

Then, the storage device erases the contents of the logical addresses where the pre-update free block table and address translation table are located (step S317), following the same process as steps S221 to S227 described above.

In this storage device, the correspondence between the logical and physical addresses of data is written to an address translation table in the order in which the data is written. Then, when reading data, the correspondence between the logical and physical addresses is read by sequentially checking the address translation table. Alternatively, the following method can be used to speed up the reading of the correspondence between logical and physical addresses:

For example, when writing data, the controller 20 may use a predetermined hash function to determine the storage location in the address translation table of the correspondence between the logical address and the physical address from the logical address sent from the CPU 12, and control the flash memory unit 10 to store the correspondence between the logical address and the physical address in the determined storage location. When reading data, the controller 20 may use the same hash function to determine the storage location of the correspondence between the logical address and the physical address from the logical address sent from the CPU 12, and read the physical address from the determined storage location in the flash memory unit 10.

In this case, a conflict may occur between the storage locations determined from the logical addresses sent from the CPU 12. In this case, the correspondence between the logical address and the physical address can be stored in the storage location next to the determined storage location, or a special area can be provided to store the conflicting addresses.

As described above, in this memory device, the address translation table and free block table are stored in the memory cell array 1 itself, and these tables can be used to read and write data.

The size of each block is not limited to the above. For example, each block does not have to consist of 16 pages, but may be an integer multiple of the size of each page.

Furthermore, if the storage device is, for example, a flash memory with a JEIDA/PCMCIA interface, the size of each page is generally determined by the operating system (OS) running on computer 11, but it does not necessarily have to be determined by the OS.

The size of each block is generally a value specific to the storage device, but the size of each block in the storage device may be specified by external control.

(Second Embodiment) In the storage device of the first embodiment, information indicating the locations of free blocks was stored centrally in a specific area. However, information indicating the locations of free blocks does not need to be stored centrally. For example, free blocks can be managed in a chained fashion by sequentially storing information indicating the locations of other free blocks in each free block.

A second embodiment of a storage device having such chained free blocks and the process of managing the free blocks will be described below with reference to FIGS. 11 to 13.

The basic configuration of the storage device of this embodiment is substantially the same as the basic configuration of the storage device of the first embodiment. However, in this embodiment, the address translation table is stored in the leading area of any block.

Furthermore, as shown in FIG. 11, free block information indicating the number of the free block that is closest to the free block in question among the free blocks that are logically subsequent to that free block is stored in a predetermined position in the redundant portion of each free block.

The chain of free blocks defined by this free block information is chained in a different order than the physical free block layout.

The control circuit 5 also stores the free block number of the first free block in the free block chain.

In the storage device of this embodiment, as described above, the data area and the redundant area are arranged so as not to overlap each other within each page.

Therefore, even if data is written to a free block that already has free block information written to it by simply overwriting the data, the free block information written in the redundant portion of the free block will not be destroyed.

(Operation of the Second Embodiment) The process of writing data to this storage device is identical to that of the first embodiment, except for the data write process and the process of updating the free block information and address translation table. Therefore, the operation of this storage device will be explained with reference to Figures 12 and 13, focusing on the data write process and the process of updating the free block information and address translation table.

(Data Writing) When writing data to this storage device, processing begins at step S501 shown in Figure 12.

In step S501, the CPU 12 identifies the logical address to be written, then supplies the lowest-numbered logical address to the bus line 13 and issues a command to the controller 20 to write the data.

In response to the command supplied in step S501, the controller 20 stores the logical address supplied from the CPU 12 via the bus line 13 as the logical address to be written (step S502).

Next, the controller 20 performs substantially the same process as the process of step S202 described above to identify the physical address associated with the logical address to be written that is stored in the controller 20 (step S503).

Next, the controller 20 references the data stored therein and identifies the first page of the first free block (step S504). It then determines that the physical address identified in step S503 and the physical address corresponding to the page identified in step S504 will be interchanged and treated as such (step S505).

As a result, the physical address to be written to becomes the physical address of the free block at the beginning of the chain, identified in step S504.

Next, the controller 20 supplies the physical address determined as the write target in step S505 to the global buffer 6 and instructs the control circuit 5 to read the 513th byte and subsequent bytes from the beginning of the page indicated by the physical address (step S506).

The control circuit 5 instructs the X-address decoder 4X to select the page identified in step S504, and then sends a data read instruction to the read control terminal Treadcont of the memory cell array 1. The memory cell array 1 sequentially supplies the free block information stored in the redundant portion of the page to the controller 20, one byte at a time, via the I/O buffer 2 and the global buffer 6.

When the controller 20 reads the free block information provided by the flash memory unit 10, it stores the free block information as information about the position of the first free block (step S507). The free block information stored in step S507 represents the free block that will become the new first free block in the chain after the process shown in FIG. 12 has been completed.

Next, the storage device treats the physical address corresponding to the page determined as the write target in step S505 as the physical address identified in step S206 in the first embodiment, and writes the data by performing substantially the same processing as steps S211 to S217 described above (step S508).

Then, in the process of step S508, if it is determined in the process corresponding to step S217 that a control code indicating the end of writing has been supplied from the CPU 12, the controller 20 ends the data writing process.

Furthermore, if it is determined in step S214 that 512 bytes of data have been written to the currently selected page, the controller 20 sends a signal to the CPU 12 requesting the next logical address. In response to this signal, the CPU 12 transmits the next logical address over the bus line 13. The controller 20 then acquires the next logical address from the CPU 12 via the bus line 13, overwrites the previously stored logical address with this logical address as the logical address to be written, and returns the process to step S503.

By the processing of steps S501 to S508 described above, the physical addresses indicated by the logical address to be written are identified sequentially, starting from the beginning of the chain of free blocks, and data is written to the identified free blocks.

(Updating free block information and address conversion tables) When updating free block information and address conversion tables, the controller 20 begins processing at step S601 in Figure 13.

In the process shown in FIG. 13, the controller 20 first references the data stored therein and identifies the first page of the first free block (step S601).

Next, the controller 20 supplies the physical address of the page identified in step S601 to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S602).

In response to the latch signal Slatch, the control circuit 5 instructs the X address decoder 4X to select the page indicated by the physical address supplied to the global buffer 6. Once the page is selected, the control circuit 5 sends a data read instruction to the read control terminal Treadcont of the memory cell array 1. The memory cell array 1 sequentially outputs the memory contents of the selected page, one byte at a time, to the controller 20 via the I/O buffer 2 and the global buffer 6.

The controller 20 then sequentially reads the contents of the global buffer 6, starting from the 513th byte, and acquires the free block information stored in the redundant portion of the page that was read (step S603).

After reading the free block information, the controller 20 overwrites the information for the first page of the first free block identified in step S601 with that free block information. In other words, the information for the location of the first free block is updated to the information for the location of the next free block (step S604).

Next, the controller 20 executes the processes of steps S309 to S315 described above to update the address translation table (step S605), and stores the location of the updated address translation table (step S606).

However, the updated address translation table is written to the logical address corresponding to the currently selected page identified in step S601. The information to be updated includes information about the physical block to which the logical address has been newly assigned, as well as information about the results of the physical address swap performed in step S505.

Next, in order to add free block information, the controller 20 references the data stored therein and identifies the first page of the first free block (step S607).

Next, the controller 20 supplies the physical address of the page it is currently identifying to the global buffer 6 and sends a latch signal Slatch to the control circuit 5 (step S608).

In response to the latch signal Slatch, the control circuit 5 causes the X address decoder 4X to select the page indicated by the physical address supplied to the global buffer 6, and sends a data read instruction to the read control terminal Treadcont of the memory cell array 1, causing the memory cell array 1 to sequentially supply the memory contents of the selected page to the controller 20 via the I/O buffer 2 and the global buffer 6.

The controller 20 then sequentially reads the information supplied from the global buffer 6, starting from the 513th byte from the beginning, to obtain the information stored in the redundant portion of the page (step S609).

Next, the controller 20 determines whether or not the information read in step S609 contains free block information (step S610).

If there is free block information, the controller 20 identifies the first page of the next free block indicated by the free block information (step S611) and returns the process to step S608.

If there is no free block information, the currently specified page is the first page of the last free block.

At this time, the controller 20 performs substantially the same processing as steps S301 to S308 described above, controlling the flash memory unit 10 to write data to the currently specified page, with the first 512 bytes being blank and the data containing, from byte 513 onward, information about the block in which the old, pre-update address translation table is currently stored as free block information (step S612).

This causes the block currently containing the old address translation block to be attached to the end of the chain of free blocks.

Next, the storage device erases the contents of the block containing the old address translation table (step S613) by following the same process as steps S221 to S227 described above. As a result, the block containing the old address translation table becomes a free block.

By the processing of steps S601 to S613 described above, the free block information and the address translation table are updated.

When initializing the memory cell array 1, the controller 20 erases the contents of all blocks in the memory cell array 1, and then controls the flash memory unit 10 to write free block chain information to the redundant section of each block.

In this case, the controller 20 writes the chain information so that free blocks are linked together at random, as shown in Figure 11. By configuring the chain information in this way and distributing the data write locations, it is possible to prevent data from being written repeatedly to only some areas.

The present invention is not limited to the above-described embodiment, and various modifications and applications are possible.

For example, in the above embodiment, data is transferred between the CPU 12 and the storage device in 1-byte units for ease of understanding, but the data transfer unit may be any unit, such as 2-byte or 4-byte units. Similarly, the capacity of the memory cell is not limited to 1 byte and may be 2 bytes, etc.

Furthermore, the memory cell array 1 used in the storage device of the above embodiment was only one chip. However, the present invention can also be applied to storage devices having multiple flash memory chips. In this case, the address translation table (and free block table) can be stored in one block of one of the flash memory chips, and the controller 20 can store information about the chip storing the address translation table (and free block table). Furthermore, if free block information is constructed using chain information, as in the second embodiment above, chain information indicating the chip with the next free block and its block number can be written to the redundant area.

In the above embodiment, the memory cell array 1 is configured as a NAND type, but it may be configured as a NOR type.

Furthermore, while the above embodiment has the control circuit 5 disposed within the storage device, it is possible to control access to the memory cell array 1 without using the control circuit 5 by having the controller 20 or the CPU 12 perform the operations performed by the control circuit 5. It is also possible to control access to the memory cell array 1 without using the controller 20 by having the CPU 12 perform the operations performed by the controller 20.

When the CPU 12 executes the operations of the control circuit 5 and the controller 20, the program for executing the above-described control operations is installed into the computer 11 from a medium (e.g., floppy disk, CD-ROM, etc.) that stores the program, and the program is run on the OS (operating system) to execute the above-described processes.

As described above, according to the present invention, information indicating the locations of free blocks, information indicating the correspondence between logical addresses and physical addresses, etc., is stored in a block-erasable storage medium. Therefore, there is no need to prepare a separate storage medium for storing information indicating the locations of free blocks, information indicating the correspondence between logical addresses and physical addresses, etc.

───────────────────────────────────────────────────── (Note) This publication is based on the publication published internationally by the International Bureau of Patents (WIPO). The effect of the international publication of the Japanese patent application (Japanese utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act) and is unrelated to this publication.

Claims (24)

[Claims] 1. A storage device comprising: a storage means (1) including a plurality of memory blocks to which physical addresses are assigned; an erasing means (1e) for erasing data stored in the storage means in units of memory blocks at once; a writing means (4X, 4B, 5, 20) for inputting data and a logical address, determining a storage location for the data within the storage means, and writing the data to the storage location; wherein the storage means stores an address conversion table that stores information indicating the correspondence between the logical address and the physical address of the storage means; and the writing means includes means (4X, 4B, 5, 20) for adding information indicating the correspondence between the physical address of the location where the data is written and the input logical address to the address conversion table or updating the address conversion table. 2. The storage device according to claim 1, further comprising reading means (4X, 4B, 5, 20) comprising: means (20) for storing the physical address of the block in which the address conversion table is written; physical address reading means (4X, 4B, 5, 20) for accessing the block in which the address conversion table is stored and reading a physical address corresponding to the logical address of the data to be read; and means (4X, 4B, 5, 20) for reading and outputting data stored at the physical address read by the physical address reading means. 3. The storage device according to claim 2, wherein the storage means stores a free block table that stores information indicating free blocks that do not store data, and the writing means includes free block selection means (20) that accesses the block in which the free block table is stored and selects a block to be written from among the free blocks registered in the free block table, and free block writing means (4X, 4B, 5, 20) that writes the data to be written to the free block selected by the free block selection means. 4. The storage device according to claim 3, wherein the storage means stores the address translation table and the free block table in a single block. 5. The storage device according to claim 3, further comprising free block table updating means (1e, 4X, 4B, 5, 20) comprising: means (1e, 4X, 4B, 5, 20) for deleting the free block table that stores information about the free blocks that existed before the free block writing means wrote the information to the free blocks; and means (4X, 4B, 5, 20) for storing in the storage means the free block table that stores information about the free blocks that remain after the free block writing means has written the information to the free blocks. 6. The storage device according to claim 5, wherein the storage means stores the address translation table and the free block table in a single block. 7. The storage device according to claim 1, wherein the storage means stores a free block table that stores information indicating free blocks that do not store data, and the writing means includes free block selection means (20) that accesses the block in which the free block table is stored and selects a block to be written from among the free blocks registered in the free block table, and free block writing means (4X, 4B, 5, 20) that writes the data to be written to the free block selected by the free block selection means. 8. The storage device according to claim 7, wherein the storage means stores the address translation table and the free block table in a single block. 9. The storage device according to claim 7, further comprising free block table updating means (1e, 4X, 4B, 5, 20) comprising: means (1e, 4X, 4B, 5, 20) for deleting the free block table that stores information about the free blocks that existed before the free block writing means wrote the information to the free blocks; and means (4X, 4B, 5, 20) for storing in the storage means the free block table that stores information about the free blocks that remain after the free block writing means has written the information to the free blocks. 10. The storage device according to claim 9, wherein the storage means stores the address translation table and the free block table in a single block. 11. A storage device comprising: a storage means (1) including multiple memory blocks to which physical addresses are assigned; an erasing means (1e) for erasing data stored in the storage means in units of memory blocks; and a writing means (4X, 4B, 5, 20) for inputting data to be written and a logical address, determining a storage location for the data within the storage means, and writing the data to the storage location; wherein the storage means stores free block information indicating free blocks that do not store the data, and the writing means writes the data to the free blocks indicated by the free block information. 12. The storage device according to claim 11, wherein the writing means further comprises means (1e, 4x, 4b, 5, 20) for updating the free block information stored in the storage means to the free block information representing information on the free blocks remaining after the data is written to the free blocks by the writing means. 13. The storage device according to claim 12, wherein the free block information is stored in a portion of each free block and is composed of chain information registered in a chain so as to point to another free block, and the writing means includes means (4X, 4B, 5, 20) for identifying a free block according to the chain information and writing the data to that free block. 14. The storage device according to claim 13, wherein the storage means is composed of a data area and a redundant area, and the chain information is stored in the redundant area. 15. The storage device according to claim 12, wherein the free block information is stored in a portion of each free block and is composed of chain information registered in a chain so as to point to another free block, and the writing means includes a first free block storage means (20) that stores the physical address of the first free block in the chain defined by the chain information, and means (4X, 4B, 5, 20) that writes the data to the free block assigned this physical address and stores the chain information registered in that block in the first free block storage means. 16. The storage device according to claim 15, wherein the storage means is composed of a data area and a redundant area, and the chain information is stored in the redundant area. 17. The storage device according to claim 11, wherein the free block information is stored in a portion of each free block and is composed of chain information registered in a chain so as to point to another free block, and the writing means includes means (4X, 4B, 5, 20) for identifying a free block according to the chain information and writing the data to that free block. 18. The storage device according to claim 17, wherein the storage means is composed of a data area and a redundant area, and the chain information is stored in the redundant area. 19. The storage device according to claim 11, wherein the free block information is stored in a portion of each free block and is composed of chain information registered in a chain that points to another free block, and the writing means includes a first free block storage means (20) that stores the physical address of the first free block in the chain defined by the chain information, and means (4X, 4B, 5, 20) that writes the data to the free block assigned this physical address and stores the chain information registered in that block in the first free block storage means. 20. The storage device according to claim 19, wherein the storage means is composed of a data area and a redundant area, and the chain information is stored in the redundant area. 21. A method for accessing a block-erasing memory that allows data to be erased in blocks and that allows data to be written to previously erased free blocks, the method comprising: storing in the memory an address conversion table indicating the correspondence between physical addresses assigned to the memory and the logical addresses of the data; when data to be written and its logical address are provided, determining whether data has already been written to the logical address using the address conversion table; if data exists, identifying a free block and writing the data to the free block while erasing the block containing the old data; if data does not exist, identifying a free block and writing the data to the free block; then adding or updating information indicating the correspondence between the physical address of the block to which the data was written to the address conversion table in the memory; and when the logical address of data to be read is provided, accessing the address conversion table in the memory to determine the physical address of the location where the data is stored, and reading and outputting the data from the physical address. 22. A method for accessing a block-erasing memory that allows data to be erased in blocks and data to be written to free blocks from which data has been previously erased, comprising: storing free block information in the memory that indicates the free blocks in the memory; and, when data to be written is supplied, identifying a free block based on the free block information, writing the data to the identified free block; and simultaneously identifying a new free block based on the free block information, and writing updated free block information to the newly identified free block. 23. A method for accessing a block-erasing memory that allows data to be erased in blocks and data to be written to previously erased free blocks. The method includes: storing free block information indicating free blocks in the memory in a block of the memory; when data to be written is supplied, identifying a free block based on the free block information, writing the data to the identified free block; identifying a new free block based on the free block information, erasing the contents of the block storing the free block information; and writing the updated free block information to the newly identified free block. 24. A method for accessing a block-erasing memory that allows data to be erased block by block and data to be written to a previously erased free block, comprising: storing free block chain information, consisting of information sequentially indicating other free blocks, in a portion of each free block of the memory; and, when data to be written is supplied, determining the free block at the beginning of the free block chain defined by the free block chain information, and writing the data to the determined free block.