JPWO1998016868A1 - Substrate for liquid crystal device, liquid crystal device and projection display device - Google Patents

Abstract

(57) [Abstract] A first light-shielding film (7) is provided below at least a channel region (1c) of a TFT that drives a pixel, and a second light-shielding film (3) is provided above the channel region (1c), thereby preventing light from being irradiated from above or below the channel region (1c). The second light-shielding film (3) is also formed to cover the channel region (1c) and the first light-shielding film (7), preventing incident light from being irradiated directly onto the surface of the first light-shielding film (7).

Description

[Detailed Description of the Invention] Liquid Crystal Device Substrate, Liquid Crystal Device, and Projection Display Device Technical Field The present invention relates to a substrate for a liquid crystal device, and technology suitable for use in a liquid crystal device and a projection display device using the same. More specifically, the present invention relates to a light-shielding structure for a substrate for a liquid crystal device that uses thin-film transistors (hereinafter referred to as TFTs) as pixel switching elements.

BACKGROUND ART Conventionally, practical liquid crystal devices have pixel electrodes formed in a matrix on a glass substrate, with TFTs made of amorphous silicon or polysilicon corresponding to each pixel electrode. The TFTs then apply voltage to each pixel electrode to drive the liquid crystal.

Among the liquid crystal devices, devices that use polysilicon films as TFTs are attracting attention because they are suitable for high integration, since transistors that constitute peripheral driving circuits such as shift registers can also be formed on the same substrate using the same process.

In a liquid crystal device using the above-mentioned TFTs, the TFTs for driving pixel electrodes (hereinafter referred to as pixel TFTs) are covered with a light-shielding film such as a chrome film called a black matrix (or black stripe) provided on the opposing substrate, preventing light from directly irradiating the channel regions of the TFTs and causing leakage current.

However, light-induced leakage current can flow not only due to incident light, but also due to light reflected by a polarizer or other element on the back surface of the LCD device substrate illuminating the TFT.

To address this issue, an invention has been proposed in which a light-shielding film is also provided below the TFT to reduce leakage current due to reflected light (Japanese Patent Publication No. 3-52611). However, if the light-shielding film provided below the TFT is formed so that it extends into the opening of the black matrix provided on the opposing substrate, incident light may directly strike the light-shielding film, and the reflected light may irradiate the TFT channel region, resulting in leakage current. This is because, in the technology that provides a light-shielding film below the TFT, it is difficult to achieve high-precision alignment between the black matrix provided on the opposing substrate and the pixel region formed on the liquid crystal device substrate. As a result, incident light from the opposing substrate directly strikes the light-shielding film that extends into the opening of the black matrix and is reflected, irradiating the TFT channel region and causing leakage current. In particular, if there is a large misalignment between the light-shielding film and the black matrix on the LCD device substrate, the amount of light reflected by the surface of the light-shielding film will be significantly increased. This reflected light will then irradiate the channel region, increasing the leakage current of the TFT and causing display degradation such as crosstalk.

An object of the present invention is to provide a technique capable of reducing light-induced leakage current from a TFT in a liquid crystal device. Another object of the present invention is to provide a technique capable of reducing light-induced leakage current from a TFT without providing a black matrix on the opposing substrate.

DISCLOSURE OF THE INVENTION To achieve the above-mentioned object, the present invention provides a liquid crystal device substrate as described in claim 1, which has a plurality of data lines formed on a substrate, a plurality of scanning lines intersecting the plurality of data lines, a plurality of thin-film transistors connected to the plurality of data lines and the plurality of scanning lines, and a plurality of pixel electrodes connected to the plurality of thin-film transistors, characterized in that a first light-shielding film is formed at least below the channel region of the thin-film transistor and the junction between the channel region and the source/drain region, and a second light-shielding film is formed above the junction between the channel region and the source/drain region.

According to the liquid crystal device substrate of claim 1, the first light-shielding film can prevent light from above from entering the channel region and the junctions between the channel region and the source/drain regions, and the second light-shielding film can prevent light from below from entering the channel region and the junctions between the channel region and the source/drain regions.

This makes it possible to reduce the leakage current of the TFT due to light.

The liquid crystal device substrate according to claim 2 is characterized in that the first light-shielding film is a metal film selected from the group consisting of a tungsten film, a titanium film, a chromium film, a tantalum film, and a molybdenum film, or an alloy film.

According to the liquid crystal device substrate of claim 2, by using a metal film or metal alloy film that has high light-shielding properties and is electrically conductive as the first light-shielding film, the first light-shielding film functions as a light-shielding film against light reflected from the rear surface of the liquid crystal device substrate, and can prevent light from entering the channel region and the junctions between the channel region and the source/drain regions.

The liquid crystal device substrate described in claim 3 is characterized in that the first wiring extending from the first light-shielding film is electrically connected to a constant potential line outside the display area.

According to the liquid crystal device substrate of claim 3, if the first light-shielding film is formed in a floating state below the channel region of the TFT, an unstable potential difference may occur between the terminals of the TFT, which may result in changes in TFT characteristics. Therefore, since the first light-shielding film must be fixed at a predetermined constant potential, the first wiring extending from the first light-shielding film is connected to a constant potential line such as ground potential outside the screen area. This prevents changes in TFT characteristics caused by an unstable potential difference between the terminals of the TFT, and does not degrade image quality.

In the liquid crystal device substrate described in claim 4, the first wiring extending from the first light-shielding film is formed below the scanning lines and along the scanning lines.

According to the liquid crystal device substrate of claim 4, the first wiring extending from the first light-shielding film is formed below the scan lines and along the scan lines. This allows wiring without affecting the pixel aperture ratio. However, the first light-shielding film is formed so as to be located below the scan lines on the side of the scan lines closer to the pixel aperture region, so that incident light does not directly strike the surface of the first light-shielding film.

In a fifth aspect of the present invention, there is provided a substrate for a liquid crystal device, wherein the line width of the first wiring extending from the first light-shielding film is formed to be narrower than the line width of the scanning line formed above the first wiring.

The liquid crystal device substrate according to claim 6 is characterized in that the first wiring extending from the first light-shielding film is covered by the scanning line formed above it. The liquid crystal device substrate according to claims 5 and 6 makes it possible to prevent incident light from being directly irradiated onto the first wiring extending from the first light-shielding film and being reflected by the scanning line.

The liquid crystal device substrate described in claim 7 is characterized in that capacitor lines for adding additional capacitance to the pixels are formed in the same layer as the scanning lines, extend parallel to the scanning lines, and second wiring extending from the first light-shielding film is formed below the capacitor lines.

According to the liquid crystal device substrate of claim 7, the second wiring extending from the first light-shielding film is also formed below the capacitance line extending parallel to the scan line, thereby forming an additional capacitance between the drain region of the TFT and the second wiring, with the first interlayer insulating film as a dielectric.

This allows the additional capacitance to be increased without reducing the pixel aperture ratio.

The liquid crystal device substrate described in claim 8 is characterized in that a third wiring extending from the first light-shielding film is formed below the data line and along the data line.

According to the liquid crystal device substrate of claim 8, a third wiring extending from the first light-shielding film may be formed below the data line along the data line, provided that the first light-shielding film is formed so that the data line covers the first light-shielding film wired below the data line in a portion where the data line contacts or is close to the pixel opening region, so that incident light is not directly irradiated onto the surface of the first light-shielding film.

The liquid crystal device substrate described in claim 9 is characterized in that the data lines also serve as the second light-shielding films and are made of any one of a metal film selected from the group consisting of aluminum film, tungsten film, titanium film, chromium film, tantalum film, and molybdenum film, or an alloy film thereof.

According to the liquid crystal device substrate of claim 9, the data lines are formed of a metal film or a metal alloy film, so that the data lines also function as the second light-shielding film. Therefore, a layer solely for light-shielding purposes is not required.

The liquid crystal device substrate according to claim 10 is characterized in that the line width of the third wiring extending from the first light-shielding film is formed to be narrower than the line width of the data line.

The liquid crystal device substrate according to claim 11 is characterized in that the channel region and the junctions between the channel region and the source/drain regions are disposed below the data lines, and the first light-shielding film provided below the channel region and the junctions between the channel region and the source/drain regions is covered by the data lines at least at the channel region and the junctions between the channel region and the source/drain regions.

According to the liquid crystal device substrate of claim 11, the data line (second light-shielding film) is formed to cover at least the channel region and the junction between the channel region and the source/drain region from light irradiation from above. In this case, it is necessary to prevent light reflected from the surface of the first light-shielding film from being irradiated onto the channel region and the junction between the channel region and the source/drain region. Therefore, the data line is formed to cover the channel region and the first light-shielding film provided below the junction between the channel region and the source/drain region.

The liquid crystal device substrate according to claim 12 is characterized in that an LDD region is formed at the junction between the channel region and the source/drain regions.

According to the liquid crystal device substrate of claim 12, the junction between the channel region and the source/drain region of the pixel TFT is formed as a low-concentration LDD region, thereby reducing leakage current when the TFT is off. However, since LDD regions are generally known to be prone to electron excitation when irradiated with light, the LDD regions are also formed so as to be covered from above and below with the first and second light-shielding films, just like the channel region.

The liquid crystal device substrate according to claim 13 is characterized in that an offset region is formed at a junction between the channel region and the source/drain regions.

According to the liquid crystal device substrate of claim 13, the junction between the channel region and the source/drain region of the pixel TFT is an offset region into which no impurity ions are implanted, thereby reducing leakage current when the TFT is off. However, like the LDD region, the offset region is also prone to electron excitation when irradiated with light. Therefore, like the channel region, the offset region is formed so as to be covered from above and below with a first light-shielding film and a second light-shielding film.

In the liquid crystal device substrate according to claim 14, the scanning lines are made of a metal film selected from the group consisting of a tungsten film, a titanium film, a chromium film, a tantalum film, and a molybdenum film, or a metal alloy film.

According to the liquid crystal device substrate of claim 14, by forming the scan lines at least from a metal film or a metal alloy film, the scan lines themselves can be used as light-shielding films. This allows not only the data lines but also the scan lines to function as light-shielding films, so that all sides of the pixel electrodes can be formed to overlap with the data lines and scan lines, making it possible to omit a black matrix provided on the opposing substrate.

The substrate for a liquid crystal device described in claim 15 is characterized in that the minimum distance L1 from the side surface of the first light-shielding film to the channel region is formed so as to satisfy the relationship 0.2 μm≦L1≦4 μm.

According to the substrate for a liquid crystal device described in claim 15, the influence of light reflected by the first light-shielding film can be prevented.

The substrate for a liquid crystal device according to claim 16 is characterized in that a minimum distance L2 from a side surface of the second light-shielding film to the first light-shielding film satisfies the relationship 0.2 μm≦L2.

According to the substrate for a liquid crystal device described in claim 16, the influence of light reflected by the first light-shielding film can be prevented.

A liquid crystal device according to claim 17 is characterized in that a liquid crystal device substrate and a counter substrate having a counter electrode are disposed at a predetermined distance, and liquid crystal is sealed in the gap between the liquid crystal device substrate and the counter substrate.

According to the liquid crystal device described in claim 17, a liquid crystal device substrate and a counter substrate having a counter electrode are bonded together with a predetermined cell gap, liquid crystal is sealed between the liquid crystal device substrate and the counter substrate, and a voltage is applied to the liquid crystal to display gradations. If light is incident on the liquid crystal device from the counter substrate side, high-quality images that are not affected by light can be obtained.

The liquid crystal device described in claim 18 is characterized in that a third light-shielding film is formed on the opposing substrate.

According to the liquid crystal device described in claim 18, a highly light-shielding black matrix (third light-shielding film) made of a metal film such as a chromium film or a black organic film is formed on the opposing substrate. The black matrix shields the pixel TFTs provided on the liquid crystal device substrate from direct light irradiation, thereby providing a liquid crystal device that can achieve high-quality image quality.

The liquid crystal device described in claim 19 is characterized in that the third light-shielding film is formed so as to cover at least the first light-shielding film.

According to the liquid crystal device of claim 19, the black matrix (third light-shielding film) on the opposing substrate covers the first light-shielding film provided on the liquid crystal device substrate, thereby preventing incident light from being directly incident on the surface of the first light-shielding film. This prevents light reflected from the light-shielding film surface from reaching the channel region of the TFT and the junction between the channel region and the source/drain region, thereby reducing light-induced leakage current in the TFT.

The liquid crystal device according to claim 20 is characterized in that microlenses are formed in a matrix on the counter substrate in correspondence with each of the plurality of pixel electrodes formed on the liquid crystal display substrate.

According to the liquid crystal device described in claim 20, a microlens is provided on the opposing substrate to focus light on pixel aperture regions on the liquid crystal device substrate. A first light-shielding film is provided on the liquid crystal device substrate to prevent light focused by the microlens from reaching the channel regions of the pixel TFTs even if the light is reflected from the rear surface of the liquid crystal device substrate. Therefore, the TFT characteristics are not affected by the intense light focused by the microlens, and a liquid crystal device that provides bright, high-quality image quality can be provided.

The projection display device described in claim 21 is characterized by comprising a light source, a liquid crystal device that modulates light from the light source and transmits or reflects the light, and projection optical means that condenses the light modulated by the liquid crystal device and projects it in an enlarged form.

According to the projection display device of claim 21, the projection display device is equipped with the liquid crystal device of the present invention, and even if light is irradiated from the backside of the liquid crystal device substrate due to reflection by a dichroic prism or the like, the first light-shielding film on the liquid crystal device substrate prevents the light from entering. Therefore, even if the light source is made brighter and strong light is incident on the liquid crystal device, the TFT characteristics are not affected, and a projection display device that can obtain bright, high-quality images can be provided.

These and other advantages of the present invention will be clearly explained in the following embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view of a pixel showing a first embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 2 is a cross-sectional view of the pixel taken along line A-A' in FIG.

3A to 3C are cross-sectional views showing the manufacturing process (first half) of the liquid crystal device substrate of the first embodiment in the order of steps.

4A to 4C are cross-sectional views showing the manufacturing process (second half) of the liquid crystal device substrate of the first embodiment in the order of steps.

FIG. 5 is a plan view of a pixel showing a second embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 6 is a cross-sectional view of the pixel taken along line B-B' in FIG.

FIG. 7 is a plan view of a pixel showing a third embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 8 is a cross-sectional view of the pixel taken along line C-C' in FIG.

FIG. 9 is a plan view of a pixel showing a fourth embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 10 is a cross-sectional view of the pixel taken along line D-D' in FIG.

FIG. 11 is a plan view of a pixel showing a fifth embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 12 is a plan view of a pixel showing a sixth embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 13 is a plan view of a pixel showing a seventh embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 14 is a cross-sectional view of the pixel taken along line E-E' in FIG.

FIG. 15 is a block diagram showing an example of a system configuration of a substrate for a liquid crystal device to which the present invention is preferably applied.

FIG. 16 shows an example of the configuration of a liquid crystal device using a liquid crystal device substrate according to the present invention. (a) is a plan view, and (b) is a cross-sectional view taken along line H-H'.

FIG. 17 is a schematic diagram of a liquid crystal projector, an example of a projection display device that uses a liquid crystal device substrate according to the present invention as a light valve.

FIG. 18 is a cross-sectional view showing an example of the configuration of a liquid crystal device using microlenses on the opposing substrate.

FIG. 19 is a plan view of a pixel showing an eighth embodiment of a liquid crystal device substrate to which the present invention is applied.

FIG. 20 is a cross-sectional view of the pixel taken along line F-F' in FIG.

1 Semiconductor layer 2 Scanning line (gate electrode) 3 Data line (second light-shielding film) 4 Contact hole between pixel electrode and drain region 5 Contact hole between data line and source region 6 Counter substrate black matrix (third light-shielding film) 7 First light-shielding film 10 Substrate 11 First interlayer insulating film 12 Gate insulating film 13 Second interlayer insulating film 14 Pixel electrode 15 Third interlayer insulating film 16 Capacitor line 17 Resist mask 20 Screen area 30 Liquid crystal device 31 Counter substrate 32 Liquid crystal device substrate 33 Counter electrode 36 Sealing layer 37 Liquid crystal 38 Liquid crystal injection hole 39 Sealant 40 External input/output terminal 50 Data line driving circuit 51 X shift register 52 Sampling switch 53 X buffer 54-56 Image signal line 60 Scanning line driver circuit 61 Y shift register 63 Y buffer 80 Microlens 90 Pixel 91 Pixel TFT 370 Light source 373, 375, 376 Dichroic mirror 374, 377 Reflecting mirror 378, 379, 380 Light valve 383 Dichroic prism 384 Projection lens Best mode for carrying out the invention Preferred embodiments of the present invention are described below with reference to the accompanying drawings.

(Example 1) Figures 1 and 2 show a first example of a substrate for a liquid crystal device suitable for application of the present invention. Figure 1 is a plan view of adjacent pixels, and Figure 2 shows a cross section taken along line A-A' in Figure 1, i.e., a cross-sectional structure along semiconductor layer 1, which serves as the active layer of the TFT.

In Figure 1, reference numeral 1 denotes the first polysilicon film constituting the semiconductor layer of a TFT, and as shown in Figure 2, a gate insulating film 12 is formed on the surface of this semiconductor layer 1 by thermal oxidation or the like. Reference numeral 2 denotes a scan line which serves as a common gate electrode for TFTs in the same row (horizontal in the figure), and reference numeral 3 denotes a data line which is arranged vertically so as to intersect with scan line 2 and supplies a voltage to be applied to the source region of a TFT in the same column. Scan line 2 is formed from the second polysilicon film, and data line 3 is formed from a conductive layer such as an aluminum film.

Also, reference numeral 4 denotes a contact hole for connecting the pixel electrode 14, which is made of a conductive layer such as an ITO film, to the drain region of the TFT in the semiconductor layer 1, and reference numeral 5 denotes a contact hole for connecting the data line 3 to the source region of the TFT in the semiconductor layer 1. Reference numeral 6 denotes a black matrix (third light-shielding film) provided on the opposing substrate 31 in correspondence with the scanning line 2 and data line 3, and is formed of a metal film such as a chromium film or a black organic film.

In the first embodiment, a first light-shielding film 7 (shown as a portion shaded upward to the right in FIG. 1 ) made of a metal film such as tungsten, titanium, chromium, tantalum, or molybdenum, or a metal alloy film thereof, is provided below the semiconductor layer 1, which serves as the active layer of the TFT, particularly below the junctions between the channel region 1c (shown as a portion shaded downward to the right in FIG. 1 ) and the LDD regions (or offset regions) 1d and 1e and the source/drain regions 1a and 1b, and below the scan lines 2. In this manner, the semiconductor layer 1 is sandwiched from above and below by the first light-shielding film 7, the second light-shielding film (data line) 3, and the third light-shielding film (black matrix) 6 on the opposing substrate side. This prevents incident light, as well as light reflected from the rear surface of the liquid crystal device substrate, from reaching the junctions between the TFT channel region 1c and the LDD regions (or offset regions) 1d and 1e and the source-drain regions 1a and 1b, thereby suppressing leakage current. Furthermore, even if an error occurs in the positional accuracy between the display area of the liquid crystal device substrate and the black matrix (third light-shielding film) 6 on the counter substrate 31 side when the liquid crystal device substrate and the counter substrate are bonded together, the second light-shielding film (data line) 3 covers the TFT channel region 1c, LDD regions (or offset regions) 1d and 1e, and first light-shielding film 7, so incident light does not directly strike the channel region 1c, LDD regions (or offset regions) 1d and 1e, or the first light-shielding film 7. This significantly reduces light-induced leakage current from the TFT.

The first light-shielding film 7 extends below the scan line 2 to supply a constant potential, such as ground potential, to the first light-shielding film 7 below the channel region 1c, which is necessary for light shielding. This prevents the first light-shielding film 7 from floating. This prevents changes in TFT characteristics. The constant potential can be connected to a constant potential line (not shown), such as a negative power supply, supplied to a peripheral driver circuit built on the same substrate in the same process as pixel formation. In particular, matching this to the low potential level of the gate signal supplied to the scan line 2 prevents changes in TFT characteristics. Therefore, it is most effective to electrically connect the constant potential to the negative power supply (not shown) of the scan line driver circuit that drives the scan line 2.

Furthermore, the first light-shielding film under the scan line 2 is preferably formed so that it is located lower and inside the scan line 2 relative to the side of the scan line 2 closer to the pixel aperture region, so that light does not directly strike the first light-shielding film 7 even if the pattern formation is misaligned with the scan line 2. This prevents reflection by the first light-shielding film 7 in the portion below the scan line 2. It is also more desirable to perform an anti-reflection treatment on the surface of the first light-shielding film 7 by roughening the surface by oxidation or the like to scatter light, or by forming a polysilicon film or the like.

Furthermore, in the first embodiment, at least the channel region 1c and LDD regions (or offset regions) 1d and 1e of the TFT are formed below the data line (second light-shielding film) 3, and the channel region 1c is completely covered by the data line (second light-shielding film) 3, which has the advantage of more reliably preventing incident light from directly irradiating the channel region 1c.

Although not particularly limited, in this embodiment, to efficiently obtain the capacitance added to the drain of the TFT, the first semiconductor layer 1 constituting the channel region 1c extends upward along the data line 3 as indicated by reference symbol 1f and is further bent upward along the scan line 2 of the preceding pixel (the upper pixel in FIG. 1) toward its own pixel electrode 14. A portion of the preceding scan line 2 also extends downward along the data line 3 as indicated by reference symbol 2f. This results in a capacitance between the extension portion 1f of the first semiconductor layer 1 and the extension portion 2f of the scan line 2 (with the gate insulating film 12 as a dielectric) being connected to the drain of the TFT that applies voltage to each pixel electrode 14 as an added capacitance. Forming the capacitance in this manner minimizes the effect on the pixel aperture ratio. This has the advantage of maintaining a high pixel aperture ratio while increasing the added capacitance.

Next, the cross-sectional structure of the pixel TFT of the present invention will be described in detail with reference to Figure 2, which shows a cross section taken approximately along the semiconductor layer 1 from contact holes 4 to 5 in Figure 1. Reference numeral 10 denotes a substrate made of alkali-free glass, quartz, or the like. Reference numeral 11 denotes a first interlayer insulating film such as a silicon oxide film or silicon nitride film formed between the semiconductor layer 1 of the TFT and the first light-shielding film 7, which is formed by a high-pressure CVD method or the like. Reference numeral 12 denotes a gate insulating film, 13 denotes a second interlayer insulating film, 15 denotes a third interlayer insulating film, and 14 denotes a pixel electrode made of an ITO film or the like.

In this Example 1, the TFTs, which function as pixel switching elements, are formed with an LDD structure (or offset structure). That is, the source/drain regions consist of LDD regions (or offset regions) 1d and 1e and source/drain regions 1a and 1b, with the channel region 1c located below the gate electrode 2. As can be seen in Figure 2, the first light-shielding layer 7 is not formed in the drain region 1b, resulting in a step in the semiconductor layer 1 between the first light-shielding layer 7 and the first light-shielding layer 7. However, because this step is several microns away from the junction between the drain region 1b and the LDD region 1e, i.e., the step is located several microns away from the junction toward the drain region, this step does not degrade the TFT characteristics. By using an LDD or offset structure for the TFT, leakage current when the TFT is turned off can be further reduced. Incidentally, the TFT having the above-described configuration has been described as having an LDD structure (or an offset structure), but it goes without saying that it may have a self-aligned structure in which source and drain regions are formed in a self-aligned manner using the gate electrode 2 as a mask.

Furthermore, according to the first embodiment, the first light-shielding film 7 is formed to cover from below the junctions between the source/drain regions 1a, 1b of the semiconductor layer 1 and the channel region 1c and LDD regions (or offset regions), and the data lines (second light-shielding film) 3 are formed to cover the channel region 1c and LDD regions (or offset regions) 1d, 1e from above. Therefore, the channel region 1c and the LDD regions (or offset regions) 1d, 1e are doubly shielded from incident light from above and from reflected light from below. Furthermore, by forming the data lines (second light-shielding film) 3 to cover the top of the first light-shielding film 7 in the areas where the data lines (second light-shielding film) 3 contact or are close to the pixel aperture regions, the incident light is prevented from being reflected on the surface of the first light-shielding film 7.

In addition to the above, the black matrix (third light-shielding film) 6 provided on the opposing substrate 31 is formed to cover the channel region 1c and the LDD regions (or offset regions) 1d and 1e, thereby more effectively blocking light from reaching the channel region 1c and the LDD regions (or offset regions) 1d and 1e. Furthermore, the black matrix (third light-shielding film) 6 is formed to broadly cover the first light-shielding film 7, thereby more effectively preventing incident light from directly reaching the first light-shielding film 7. Therefore, in a liquid crystal device using the liquid crystal device substrate of the present invention, incident light is reflected by the first light-shielding film 7 and does not illuminate the channel region 1c and the LDD regions (or offset regions) 1d and 1e. This minimizes light-induced leakage current from the TFTs, providing high-quality image quality without image degradation such as crosstalk.

(Manufacturing Process) Next, the manufacturing process of this embodiment will be described with reference to Figures 3 and 4. First, a conductive metal film, such as tungsten, titanium, chromium, tantalum, or molybdenum, or a metal alloy film, such as metal silicide, is formed on a substrate 10, such as alkali-free glass or quartz, by sputtering or other methods to a thickness of approximately 500 to 3000 angstroms, preferably approximately 1000 to 2000 angstroms. This film is then patterned using photolithography and etching techniques to form a first light-shielding film 7 (Figure 3a). This first light-shielding film 7 is formed so as to cover at least the channel region 1c and LDD regions (or offset regions) 1d and 1e of the TFTs to be formed later. Note that the material of the first light-shielding film 7 may be an organic film as long as it absorbs light. Furthermore, in order to prevent reflection on the surface of the first light-shielding film 7, it is preferable to form irregularities on the surface of the first light-shielding film 7 by oxidation or the like, thereby scattering incident light. Alternatively, a polysilicon film may be formed above the first light-shielding film 7 to form a two-layer structure, allowing incident light to be absorbed by the polysilicon film.

Next, a first interlayer insulating film 11 is formed on the first light-shielding film 7 to a thickness of approximately 1,000 to 15,000 angstroms, preferably 5,000 to 10,000 angstroms (FIG. 3b). The first interlayer insulating film 11 insulates the first light-shielding film 7 from the semiconductor layer 1 to be formed later, and is formed, for example, from a silicon oxide film or a silicon nitride film using atmospheric pressure CVD or TEOS gas.

After forming the first interlayer insulating film 11, the substrate 10 is heated to a temperature of approximately 500°C while monosilane gas or disilane gas is supplied at a flow rate of approximately 400-600 cc/min at a pressure of approximately 20-40 Pa to form an amorphous silicon film on the first interlayer insulating film 11. This is then annealed in an N2 atmosphere at a temperature of approximately 600-700°C for approximately 1-72 hours to form a polysilicon film by solid-phase growth. Subsequently, the semiconductor layer 1 of the TFT is formed by photolithography, etching, and other processes (Figure 3c). This polysilicon film may be formed by low-pressure CVD or the like to a thickness of about 500 to 2000 angstroms, preferably about 1000 angstroms, or may be formed by implanting silicon ions into a polysilicon film deposited by low-pressure CVD or the like to make it amorphous, and then recrystallizing it by annealing or the like to form a polysilicon film.

Next, the semiconductor layer 1 is thermally oxidized to form a gate insulating film 12 on the semiconductor layer 1 (FIG. 3d). Through this process, the semiconductor layer 1 finally has a thickness of 300 to 1,500 angstroms, preferably 350 to 450 angstroms, and the gate insulating film 12 has a thickness of approximately 600 to 1,500 angstroms.

When using a large substrate of 8 inches or so, a two- or more-layer gate insulating film structure may be formed by shortening the thermal oxidation time to form a thin thermal oxide film in order to prevent warping of the substrate due to heat, and then depositing a high-temperature silicon oxide film (HTO film) or a silicon nitride film on the thermal oxide film by a CVD method or the like. Next, of the polysilicon layer constituting the semiconductor layer, a region (if in FIG. 1 ) extending upward along the data line 3 to form an additional capacitance is doped with an impurity, for example, phosphorus, at a dose of approximately 3×10 ¹² /cm ² to reduce the resistance of that portion of the semiconductor layer 1. The lower limit of this dose is determined from the viewpoint of ensuring the conductivity required to form the additional capacitance of the semiconductor layer 1, and the upper limit is determined from the viewpoint of suppressing deterioration of the gate insulating film 12.

Next, a polysilicon film that will become the gate electrode and scan line 2 is deposited on the semiconductor layer 1 via the gate insulating film 12 and patterned by photolithography, etching, or other processes (Figure 3e). The gate electrode may be made of a polysilicon film, or a light-shielding material, such as a conductive metal film (e.g., tungsten, titanium, chromium, tantalum, or molybdenum) or a metal alloy film (e.g., metal silicide), can block incident light from reaching the channel region 1c and the LDD regions (or offset regions) 1d and 1e, further improving the light-shielding effect. This allows the black matrix (third light-shielding film) 6 on the opposing substrate 31 to be omitted, thereby preventing a decrease in the transmittance of the liquid crystal device due to precision errors during bonding of the opposing substrate 31 and the liquid crystal device substrate.

Next, to form an N-channel TFT, impurity ions (e.g., phosphorus ions) are implanted at a dose of approximately 0.1 to 10× ¹⁰ /cm using the gate electrode ² as a mask to form low-concentration regions (LDD regions) 1d and 1e (FIG. 3f).

Furthermore, a resist mask 17 wider than the width of the gate electrode 2 is formed on the gate electrode 2, and impurity ions (e.g., phosphorus ions) are implanted at a density of approximately 0.1 to 10×10¹⁵/cm² ion implantation is performed with a dose of 100 uF (Figure 4g). This results in an LDD structure in the masked region. This results in LDD regions 1d and 1e and source/drain regions 1a and 1b, and a channel region 1c below the gate electrode 2. When ion implantation is performed in this manner, impurity ions are also introduced into the polysilicon film that served as the gate electrode (scanning line) 2, further lowering the resistance of the gate electrode (scanning line) 2.

Instead of these impurity introduction steps, a resist mask 17 wider than the gate electrode 2 may be formed without implanting low-concentration impurity ions (e.g., phosphorus ions), and high-concentration impurity ions (e.g., phosphorus ions) may be implanted to form offset N-channel source/drain regions 1a, 1b. Alternatively, high-concentration impurity ions (e.g., phosphorus ions) may be implanted using the gate electrode 2 as a mask to form self-aligned N-channel source/drain regions.

Although not shown, in order to form P-channel TFTs for the peripheral drive circuits, the pixel TFT section and the N-channel TFT section are protected by a resist film, and using the gate electrode 2 as a mask, impurity ions (e.g., boron ions) are implanted at ^a dose of approximately 0.1 to 10× ¹⁰ /cm to form low-concentration regions (LDD regions) 1d and 1e.

Furthermore, a resist mask 17 wider than the gate electrode 2 is formed on the gate electrode 2, and impurity ions (e.g., boron ions) are implanted at a dose ^of approximately 0.1 to 10× ¹⁰ /cm (FIG. 4g). This results in the masked region having a lightly doped drain (LDD) structure. That is, LDD regions 1d and 1e and source/drain regions 1a and 1b are formed, and a channel region 1c is formed below the gate electrode 2.

Instead of these impurity introduction processes, a resist mask 17 wider than the gate electrode 2 may be formed without implanting low-concentration impurity ions (e.g., boron ions), and high-concentration impurity ions (e.g., boron ions) may be implanted to form offset P-channel source/drain regions 1a, 1b. Alternatively, high-concentration impurity ions (e.g., boron ions) may be implanted using the gate electrode 2 as a mask to form self-aligned P-channel source/drain regions. These ion implantation processes enable the fabrication of CMOS (complementary metal-oxide semiconductor) TFTs, allowing peripheral driver circuitry to be integrated within the same substrate as the pixel TFTs.

Thereafter, a second interlayer insulating film 13 made of a silicon oxide film, a silicon nitride film, or the like is formed over the entire surface of the substrate 10 to a thickness of 5,000 to 15,000 angstroms by, for example, CVD, so as to cover the gate electrode 2. The second interlayer insulating film 13 is formed of a silicon oxide film (NSG) or a silicon nitride film that does not contain boron or phosphorus. After annealing to activate the source and drain regions, contact holes 5 are opened in the second interlayer insulating film 13 by, for example, dry etching, corresponding to the source regions 1a of the pixel TFTs. Next, a conductive metal or metal alloy film such as aluminum, titanium, tungsten, tantalum, chromium, or molybdenum is formed by, for example, sputtering to a thickness of 2,000 to 6,000 angstroms, and the data lines (second light-shielding film) are patterned by, for example, photolithography and etching. At this time, the data line (second light-shielding film) 3 is connected to the semiconductor layer 1 through the contact hole 5 (FIG. 4h). At this time, the data line (second light-shielding film) 3 is formed so as to cover at least the channel region 1c and the LDD regions (or offset regions) 1d and 1e.

Next, a third interlayer insulating film 15 is formed over the entire surface of the substrate 10, covering the data lines 3, to a thickness of 5,000 to 15,000 angstroms, for example, by CVD or atmospheric pressure ozone TEOS. The third interlayer insulating film 15 is formed from a boron-phosphorus silicon dioxide (BPSG) or silicon nitride film. Alternatively, an organic film or other material may be applied using a spin coater to form a planarized film without steps. Performing this planarization process during the formation of the third interlayer insulating film immediately before the formation of the pixel electrodes 14 minimizes the reduction in contrast of the liquid crystal device due to poor liquid crystal alignment. Finally, a contact hole 4 is opened in the third interlayer insulating film 15 by dry etching or other methods, connecting the pixel electrodes 14 to the semiconductor layer 1 (Figure 4i).

The pixel electrodes 14 are formed, for example, by forming an ITO film to a thickness of about 400 to 2000 angstroms by sputtering or the like, and then patterning the film by photolithography, etching, or the like. Then, an alignment film made of polyimide or the like is coated on the entire surface of the substrate 10 to a thickness of about 200 to 1000 angstroms over the pixel electrodes 14 and the third interlayer insulating film 15, and rubbing (alignment treatment) is performed to form a substrate for a liquid crystal device.

In the first embodiment, an LDD structure was described, but an offset structure or a self-aligned structure using the gate electrode as a mask may also be used. In the case of an offset structure, the step of FIG. 4f can be omitted. In the case of a self-aligned structure, high-concentration impurities can be implanted in the step of FIG. 4f and the step of FIG. 4g can be omitted.

(Example 2) Figures 5 and 6 show a second example of a substrate for a liquid crystal device suitable for application of the present invention. Figure 5 is a plan view of adjacent pixels, and Figure 6 shows a cross section taken along line B-B' in Figure 5, i.e., a cross-sectional structure taken along semiconductor layer 1, which serves as the active layer of the TFT.

In Example 2, a first light-shielding layer 7 (shown as the hatched area with an upward-sloping diagonal line in FIG. 5 ) is formed below the semiconductor layer 1 and below the scanning line 2, and the semiconductor layer 1 is formed so that the semiconductor layer 1 intersects the scanning line 2 twice. This configuration maintains a constant distance between the pixel TFT's channel region 1c (shown as the hatched area with an downward-sloping diagonal line in FIG. 5 ) and each contact hole, even if the scanning line (gate electrode) 2 is misaligned with respect to the semiconductor layer 1, preventing degradation of image quality due to differences in pixel TFT characteristics. Furthermore, because the semiconductor layer 1, which forms the pixel TFT's channel region 1c, intersects the scanning line 2 twice, and the channel regions 1c formed at each intersection are connected in series, the resistance component of the pixel TFT increases, advantageously reducing leakage current when the TFT is off.

In this second embodiment, the pixel TFT may also have an LDD structure or an offset structure. By incorporating an LDD structure or an offset structure into a dual-gate structure or triple-gate structure, leakage current can be further reduced. Furthermore, in this second embodiment, one of the two channel regions 1c and the LDD regions (or offset regions) 1d, 1e (the left side in FIG. 5 ) is located below the data line (second light-shielding film) 3 made of an aluminum film or the like. Therefore, the data line (second light-shielding film) 3 functions as a light-shielding film against light incident from above, i.e., from the opposing substrate 31 side, preventing direct light irradiation on the channel region 1c and the LDD regions (or offset regions) 1d, 1e of the pixel TFT, thereby further reducing leakage current. In this case, the channel region 1c and LDD regions (or offset regions) 1d and 1e (on the right side in Figure 5) that are not covered by the data line (second light-shielding film) 3 are at risk of being directly exposed to incident light. However, at least one of the two serially connected channels is not affected by light, so light-induced leakage current is not a problem, and the dual gate allows for low resistance when the TFT is off.

In addition, in this second embodiment, as in the first embodiment, the first light-shielding film 7 is formed smaller than the black matrix 6 on the opposing substrate 31 side. Therefore, incident light does not directly strike the surface of the first light-shielding film 7, thereby suppressing leakage current in the pixel TFTs due to light reflected from the first light-shielding film 7 itself. Furthermore, to prevent incident light from directly striking the first light-shielding film 7 extending below the scanning line 2, the first light-shielding film 7 is formed narrower than the width of the scanning line 2. This prevents reflection by the first light-shielding film 7 below the scanning line 2.

Although not particularly limited, in this embodiment, in order to efficiently obtain capacitance added to the drain of the TFT, the first semiconductor layer 1 constituting the channel region 1c extends upward along the data line 3 as indicated by reference symbol 1f and is further bent upward toward the adjacent pixel electrode 14 (the pixel to the left in FIG. 5) along the scan line 2 of the preceding pixel (the upper pixel in FIG. 5). A portion of the preceding scan line 2 also extends downward along the data line 3 as indicated by reference symbol 2f. As a result, the capacitance between the extension portion 1f of the first semiconductor layer 1 and the extension portion 2f of the scan line 2 (with the gate insulating film 12 as a dielectric) is connected as additional capacitance to the drain of the TFT that applies voltage to each pixel electrode 14. Forming the capacitance in this manner minimizes the effect on the pixel aperture ratio. This has the advantage of maintaining a high pixel aperture ratio while increasing the additional capacitance.

Moreover, the second embodiment can be formed by the same manufacturing process as the first embodiment.

(Example 3) Figures 7 and 8 show a third example of a substrate for a liquid crystal device suitable for application of the present invention. Figure 7 is a plan view of adjacent pixels, and Figure 8 shows a cross section taken along line C-C' in Figure 7, i.e., a cross-sectional structure taken along semiconductor layer 1, which serves as the active layer of the TFT.

The third embodiment differs from the first embodiment in that the first light-shielding film 7 (the portion with upward-sloping diagonal lines in FIG. 7 ) is provided not only under the scanning lines 2 but also under the data lines 3. That is, in the third embodiment, the first light-shielding film 7 extends below the scanning lines 2 and the data lines 3, forming a matrix wiring. This configuration further reduces the wiring resistance of the first light-shielding film 7 when electrically connected to a constant potential wiring such as ground potential. Furthermore, even if a break occurs due to a foreign object or the like during the substrate processing, a constant potential is still supplied. Therefore, the low resistance of the wiring and redundant structure result in high-quality image quality without crosstalk.

Also, in the third embodiment, similar to the first embodiment, a first light-shielding film 7 made of a metal film such as a tungsten film, a titanium film, a chromium film, a tantalum film, or a molybdenum film, or a metal alloy film such as a metal silicide, is provided below the channel region 1c of the pixel TFT (the shaded area downward to the right in FIG. 7 ) and below the scan line 2 and the data line 3, respectively. Therefore, the scan line 2 and the data line (second light-shielding film) 3 function as a light-shielding layer against incident light from the opposing substrate 31 side, and the first light-shielding film 7 functions as a light-shielding layer against reflected light from the rear surface of the liquid crystal device substrate, preventing the reflected light from irradiating the channel region 1c and LDD regions (or offset regions) 1d and 1e of the pixel TFT, thereby suppressing light-induced leakage current. Furthermore, in Example 2, all sides of the pixel electrode 14, i.e., the vertical sides in FIG. 7 overlap the data line 3, and the horizontal sides overlap the first light-shielding film 7 below the scanning line 2, separating adjacent pixel electrodes from each other by the first light-shielding film 7 above the data line 3 and below the scanning line 2. This configuration eliminates the need for a black matrix (third light-shielding film) 6 on the opposing substrate 31. Experiments conducted by the inventors using a tungsten silicide film for the first light-shielding film 7 with a thickness of approximately 2000 angstroms yielded an optical density of 3 or greater, thereby achieving a light-shielding layer with high light-shielding properties equivalent to those of the black matrix on the opposing substrate 31. This eliminates the need for alignment accuracy when bonding the black matrix (third light-shielding film) 6 on the opposing substrate 31 to the liquid crystal device substrate, thereby providing the advantage of consistent transmittance across the liquid crystal device.

In the third embodiment, the first light-shielding film is arranged in a matrix below the data lines 3 and the scanning lines 2. However, if wiring made of the first light-shielding film 7 is formed at least below the scanning lines 2 as in the first embodiment, it goes without saying that the black matrix on the opposing substrate can be omitted.

Moreover, the third embodiment can also be formed by the same manufacturing process as the first embodiment.

(Example 4) Figures 9 and 10 show a fourth example of a liquid crystal device substrate suitable for application of the present invention. Figure 9 is a plan view of adjacent pixels, and Figure 10 shows a cross section taken along line D-D' in Figure 9, i.e., a cross-sectional structure taken along the semiconductor layer 1 that serves as the active layer of the TFT. Example 4 differs from Example 3 in that the scan lines 2 have a multilayer structure consisting of a polysilicon layer 2a and a metal film such as a tungsten film or a molybdenum film, or a metal alloy film 2b such as a metal silicide, and in that the first light-shielding film 7 (the area indicated by diagonal lines slanting upward to the right in Figure 9) is provided only below the data lines (second light-shielding film) 3. In Example 3 described above, only the polysilicon film forming the scan lines 2 is located above the first light-shielding film 7. Therefore, if the channel regions 1c (the area indicated by diagonal lines slanting downward to the right in Figure 9) and LDD regions (or offset regions) 1d and 1e are close to the pixel apertures, they may be affected by incident light. Therefore, this problem is solved by forming the scanning lines 2 from a non-light-transmitting metal or metal alloy film. That is, the vertical sides of the pixel electrodes 14 in FIG. 9 are shielded from light by the data lines 3, and the horizontal sides are shielded from light by the scanning lines 2. Therefore, in Example 4, the wiring extending from the first light-shielding film 7 is routed only below the data lines 3, but it may also be routed only below the scanning lines 2 as in Example 1, or routed in a matrix as in Example 3.

The metal or metal alloy film 2b may be formed by sputtering, or by depositing a metal film on the polysilicon film 2a and then silicidating the metal film 2b through heat treatment. The scan line 2 is not limited to the two-layer structure described above; it may also have three or more layers. For example, the scan line 2 may be formed of a polysilicon film 2a with good adhesion to the semiconductor layer 1, a low-resistance metal silicide layer 2b such as tungsten silicide, or the like, and a polysilicon film covering the polysilicon film 2a and the metal silicide layer 2b to prevent peeling of the metal silicide layer. Forming the scan line 2 from a metal or metal alloy film in this way not only serves as a light-shielding film, but also reduces wiring resistance compared to a polysilicon film alone, thereby reducing gate signal delays.

In this fourth embodiment, as in the first embodiment, in the portion of the data line (second light-shielding film) 3 that contacts or is close to the pixel opening region, the first light-shielding film 7 extending downward is formed to be narrower than the width of the data line (second light-shielding film) 3. This is because the data line 3 functions as a light-shielding layer against incident light, and the line width of the upper data line (second light-shielding film) 3 is formed to be wide so that the light is not directly irradiated onto the first light-shielding film 7.

In Example 4, a first light-shielding film 7 made of a metal silicide such as tungsten silicide is provided below the channel region 1c and LDD regions (or offset regions) 1d and 1e of the pixel TFT and below the data line 3, respectively. The scan line 2 has a multilayer structure including a non-transparent metal film or metal silicide film. Therefore, the scan line 2 and data line 3 function as light-shielding layers against incident light from the opposing substrate 31, and the first light-shielding film 7 functions as a light-shielding film against reflected light from the rear surface of the substrate. This prevents the reflected light from reaching the channel region 1c and LDD regions (or offset regions) 1d and 1e of the pixel TFT, thereby suppressing light-induced leakage current in the TFT. In this case, as in Example 3, all sides of the pixel electrode 14 overlap the data line 3 and the scan line 2, and are separated from adjacent pixel electrodes 14 on the data line 3 and the scan line 2. Therefore, similar to the third embodiment, the fourth embodiment also has the advantage that it is not necessary to provide a black matrix on the opposing substrate.

Moreover, the fourth embodiment can also be formed by the same manufacturing process as the first embodiment.

(Example 5) Figure 11 shows a fifth example of a liquid crystal device substrate suitable for application of the present invention. Figure 11 is a plan view of adjacent pixels. The cross section taken along line A-A' in Figure 11, i.e., the cross section taken along the semiconductor layer 1, which serves as the active layer of the TFT, has the same structure as the cross section (Figure 2) described in Example 1. In Example 5, instead of extending the scan line 2 below the data line 3 to form an additional capacitance, a capacitance line 16 is provided parallel to the scan line 2, and an extension portion 1f of the semiconductor layer 1 is provided below this capacitance line 16 to form an additional capacitance. The capacitance line 16 is formed from a second-layer polysilicon film formed in the same process as the scan line 2, and is fixed to a constant potential, such as ground potential, outside the screen area. This constant potential can be effectively achieved by using a constant potential line, such as a power supply line for peripheral drive circuits, eliminating the need for a dedicated external terminal. Furthermore, the gates of the pixel TFTs are single-gate. In liquid crystal devices using such capacitive line substrates, the capacitive lines 16 must be shielded from light, so the black matrix (third light-shielding film) 6 provided on the opposing substrate 31 must be large. In this case, because there is a margin of distance between the pixel opening on the capacitive line 16 side and the pixel TFT channel region 1c (the area shaded diagonally downward to the right in Figure 11), the effect of incident light can be almost ignored. Therefore, the effect of incident light is limited to the pixel opening on the scanning line 2 side, which has the advantage of halving the leakage current due to light.

Moreover, the fifth embodiment can also be formed by the same manufacturing process as the first embodiment.

(Example 6) Figure 12 shows a sixth example of a substrate for a liquid crystal device incorporating the present invention. Figure 12 is a plan view of adjacent pixels. The cross section taken along line B-B' in Figure 12, i.e., the cross section taken along the semiconductor layer 1 serving as the active layer of the TFT, has the same structure as the cross section (Figure 6) described in Example 2. As in Example 5, Example 6 also includes a capacitance line 16 parallel to the scan line 2, and an extension 1f of the semiconductor layer 1 below this capacitance line 16 to provide additional capacitance. However, the semiconductor layer 1 of the pixel TFT is U-shaped, and the gate electrode is configured as a dual gate. The capacitance line 16 is formed from a second-layer polysilicon film formed in the same process as the scan line 2, and is fixed to a constant potential such as ground potential outside the screen area. Therefore, in Example 6, the capacitance line 16 must be shielded from light, and the black matrix (third light-shielding film) 6 provided on the opposing substrate 31 must be formed with a large surface area. In this case, because there is a margin in the distance from the pixel opening on the capacitance line 16 side to the pixel TFT channel region 1c (the area shaded diagonally downward to the right in Figure 12), the effect of incident light can be almost ignored. Therefore, the effect of incident light is limited to the pixel opening on the scan line 2 side, which has the advantage of reducing the leakage current due to light by half.

Furthermore, because the gate electrode of the pixel TFT has a dual-gate structure, the resistance of the TFT when it is off is increased, further reducing leakage current. In addition, in Figure 12, as in Example 2, only one of the two channel regions 1c is formed below the data line (second light-shielding film) 3. However, if at least one of the channel regions 1c is shielded by the data line 3, the leakage current of the TFT due to light can be reduced.

Moreover, the sixth embodiment can be formed by the same manufacturing process as the first embodiment.

(Example 7 and Size Regulation of Light-Shielding Film in Data Line 3) Figures 13 and 14 show a representative example of a pixel region of a substrate for a liquid crystal device to which the present invention is applied, which is a variation of Example 5. In Example 7, the capacitance line 16 is partially formed obliquely below the pixel electrode 14 to improve the pixel aperture ratio. Figure 13 is a plan view of adjacent pixels, and Figure 14 is a cross-sectional view taken along line E-E' in Figure 13. The cross-section taken along line A-A' in Figure 13, i.e., the cross-sectional structure taken along the semiconductor layer 1 that serves as the active layer of the TFT, is similar to the cross-section described in Example 1 (Figure 2). In Example 7, the semiconductor layer 1 is formed above the first light-shielding film 7 (the portion with upward-right diagonal lines in Figure 13) via the first interlayer insulating film 11. The semiconductor layer 1 is formed so that at least the channel region 1c (the portion with downward-right diagonal lines in Figure 13) and the LDD regions (or offset regions) 1d and 1e are covered by the data line (second light-shielding film) 3. Furthermore, at least the first light-shielding film 7 is covered with a black matrix (third light-shielding film) 6 on the opposing substrate 31, which is bonded to the liquid crystal device substrate with liquid crystal interposed therebetween. Here, the pattern shape of the first light-shielding film 7 must be devised so that it is not directly irradiated with incident light from the opposing substrate 31 side.

Therefore, as shown in Figure 14, the sizes of the first light-shielding film 7, the second light-shielding film (data line) 3, and the third light-shielding film (black matrix on the opposing substrate) 6 are defined relative to the width W of the channel region 1c and the LDD regions (or offset regions) 1d and 1e. The width W of the channel region 1c and the LDD regions (or offset regions) 1d and 1e may be the same, or they may differ in size. Ideally, the widths of the LDD regions (or offset regions) 1d and 1e and the gate electrode (scanning line) 2 should be the same width W, taking into account pattern alignment accuracy, in order to stabilize pixel TFT characteristics. If the sizes are to be varied, high-quality image quality can be achieved by narrowing the width of the LDD regions (or offset regions) 1d and 1e, which are more likely to excite electrons by light, relative to the channel region 1c. In all embodiments of the present invention, the size of the light-shielding film is specified assuming that the widths of the channel region 1c and the LDD regions 1d and 1e are approximately the same. In FIG. 14 , if the minimum distances from the side of the first light-shielding film 7 covering the channel region 1c and the LDD regions (or offset regions) 1d and 1e as viewed from the back surface of the substrate 10 are defined as L1 and L1', respectively, the pattern layout should be such that at least the relationship shown in the following definition (1) holds:

0.2 μm ≦ L1, L1' ≦ 4 μm (1) To maintain a high aperture ratio of the liquid crystal device while considering the pattern accuracy of the first light-shielding film 7, it is desirable to lay out the pattern so that the relationship shown in the following definition (2) holds.

0.8 μm ≦ L1, L1' ≦ 2 μm ... (2) The value in definition equation (2) is derived from the fact that, because the thickness of the first interlayer insulating film 11 is approximately 8000 Å, light reflected from the back surface of the substrate 10 must be reflected at an angle of 45 degrees or more from the side surface of the first light-shielding film 7 relative to the incident light in order to reach the channel region 1c and the LDD regions (or offset regions) 1d and 1e. Because incident light is generally parallel to the vertical direction and strikes the screen area of an LCD device, the probability of incident light being reflected at an angle of 45 degrees or more from the side surface of the first light-shielding film 7 is low. Therefore, if the value of definition equation (2) is satisfied, the effect of reflected light can be largely ignored.

Next, we define the relationship between the first light-shielding film 7 and the second light-shielding film (data line) 3. The second light-shielding film (data line) 3 located above the first light-shielding film 7 must be formed wide so that incident light does not directly irradiate the first light-shielding film 7. In particular, the LDD regions 1d and 1e are susceptible to the effects of incident light because they do not have scanning lines 2. Therefore, the minimum distances from the side surfaces of the second light-shielding film to the first light-shielding film are defined as L2 and L2'. It is recommended that the pattern layout be such that at least the relationship shown in the following definition (3) holds:

0.2 μm ≦ L2, L2′ ... (3) Since the combined thickness of the first interlayer insulating film 11 and the second interlayer insulating film 13 is preferably approximately 15,000 Å, it is even better to lay out the pattern so that the relationship shown in the following definition (4) holds.

1.5 μm ≦ L2, L2' ... (4) This is similar to the relationship between the first light-shielding film 7 and the channel region 1c and the LDD regions (or offset regions) 1d and 1e described above. Unless the incident light is incident at an angle of 45 degrees or greater from the second light-shielding film (data line) 3, the light will not reach the surface of the first light-shielding film 7. Furthermore, as shown in Figure 13, the first light-shielding film 7 below the channel region 1c extends along the scanning line 2, so the definitions (3) and (4) do not hold in this area. However, this does not pose a problem because at least the areas near the channel region 1c and the LDD regions (or offset regions) 1d and 1e are covered by the scanning line 2 and the third light-shielding film (black matrix on the opposing substrate) 6.

Next, we define the relationship between the second light-shielding film (data lines) 3 and the third light-shielding film (black matrix on the opposing substrate) 6. Essentially, if the second light-shielding film (data lines) 3 provides sufficient light-shielding properties, the third light-shielding film (black matrix on the opposing substrate) 6 is not necessary. Therefore, if the scanning lines 2 are formed from a light-shielding film and all edges of the pixel electrodes 14 are formed to overlap adjacent data lines 3 and scanning lines 2, the black matrix (third light-shielding film) 6 on the opposing substrate can be omitted. Therefore, because the third light-shielding film (black matrix) 6 can narrow the light-transmitting area of pixels due to misalignment between the liquid crystal device substrate 10 and the opposing substrate 31, it is desirable to not form the black matrix (third light-shielding film) 6 on the opposing substrate in order to achieve a high aperture ratio. However, there is a risk of light transmission through pinholes in the metal film, such as an aluminum film, or metal alloy film that forms the second light-shielding film. Forming a third light-shielding film (black matrix on the opposing substrate) 6 on the data lines to prevent this creates a redundant structure. If a black matrix (third light-shielding film) is formed, it is desirable that the distances L3 and L3' from the side surfaces of the second light-shielding film (data lines) 3 to the third light-shielding film 6 satisfy the relationship defined by equation (5).

L3, L3' ≦ 1 μm (5) This is because satisfying definition (5) has almost no effect on the aperture ratio.

Furthermore, the channel width W is largely dependent on the writing characteristics of the pixel TFT. However, if the TFT on/off ratio can be maintained at six digits or more, the shorter the channel width, the less susceptible it is to light. Therefore, it is recommended to form the channel width W within the range 0.2 μm ≦ W ≦ 4 μm (6). Even more desirable is forming the channel width W within the range 0.2 μm ≦ W ≦ 2 μm (7), which allows the data line (second light-shielding film) 3 to be formed with a narrower width, thereby achieving an even higher aperture ratio.

Moreover, the seventh embodiment can be formed by the same manufacturing process as the first embodiment.

(Embodiment 8 and Size Regulation of Light-Shielding Film in Scan Line 2 Area) FIGS. 19 and 20 show an eighth embodiment of a substrate for a liquid crystal device incorporating the present invention. FIG. 19 is a plan view of adjacent pixels, and FIG. 20 is a cross-sectional view taken along the line F-F' in FIG. 19. In this embodiment, the first light-shielding film 7 (the area indicated by diagonal lines slanting upward to the right in FIG. 19) of the pixel shown in embodiment 7 is formed in a matrix pattern not only under the scan line 2 but also under the data line 3 and the capacitor line 16. This configuration further reduces the resistance of the first light-shielding film 7 and also forms an additional capacitance between the drain region 1b of the semiconductor layer 1 and the first light-shielding film 7, with the first interlayer insulating film 11 acting as a dielectric. Furthermore, even if a defect exists in the black matrix 6 on the opposing substrate 31, the first light-shielding film 7 also serves as the black matrix 6, thereby reducing defects such as point defects.

Next, in FIG. 23, the relationship between the first light-shielding film 7 and the scanning line 2 is defined. The distance L4 from the side surface of the first light-shielding film 7 below the scanning line 2 to the side surface of the scanning line 2 on the pixel aperture region side may be defined as follows: (8)

0.2 μm ≦ L4 (8) This is because, when the side of the scan line 2 and the edge of the pixel aperture region, i.e., the third light-shielding film 6, are in the same positional relationship, the first light-shielding film 7 must be at least closer to the scan line 2 than the side of the scan line 2, otherwise incident light will be directly incident on the surface of the first light-shielding film 7.

Next, the relationship between the first light-shielding film 7 below the capacitance line 16 and the capacitance line 16 is defined. The distance L5 from the side surface of the first light-shielding film 7 below the capacitance line 16 to the side surface of the capacitance line 16 on the pixel opening region side may be expressed by the following definition formula (9).

0.2 μm ≦ L5 (9) This is because, when the side of the capacitor line 16 and the edge of the pixel aperture region, i.e., the third light-shielding film 6, are in the same positional relationship, the first light-shielding film must be at least closer to the capacitor line 16 than the side of the capacitor line 16, otherwise incident light will directly strike the surface of the first light-shielding film.

Moreover, the eighth embodiment can be formed by the same manufacturing process as the first embodiment.

It goes without saying that the defining formulas (1) to (9) defined in Examples 7 and 8 are applicable to all liquid crystal device substrates and liquid crystal devices to which the present invention is applied.

Furthermore, in the above-described Examples 1 to 8, the first light-shielding film 7 is formed directly on the surface of the substrate 10 made of alkali-free glass, quartz, or the like. However, it is also possible to achieve planarization by forming grooves corresponding to the pattern of the first light-shielding film 7 on the surface of the substrate 10 by etching, and then embedding the first light-shielding film 7 in these grooves. The surface of the first light-shielding film 7 may also be subjected to an anti-reflection treatment. Possible methods for the anti-reflection treatment include thermally oxidizing the surface of the first light-shielding film 7 made of a metal film or a metal alloy film such as a metal silicide to form an oxide film, or coating the surface of the first light-shielding film 7 with a polysilicon film by a CVD method or the like.

(Description of Liquid Crystal Device) Figure 16(a) shows the planar layout of a liquid crystal device 30 incorporating the liquid crystal device substrate 32. Figure 16(b) shows a cross-sectional view taken along line H-H' in (a).

As shown in Figures 16(a) and 16(b), the counter substrate 31 and the liquid crystal device substrate 32 are bonded together across a predetermined cell gap by a sealing layer 36 containing a gap material formed in an area corresponding to the gap between the screen area 20 and the data line drive circuit 50 and scanning line drive circuit 60. Liquid crystal 37 is sealed in the inner area of the sealing layer 36. The sealing layer 36 is partially interrupted, and the liquid crystal 37 is injected through this interruption (liquid crystal injection hole 38). In the liquid crystal device 30, after the counter substrate 31 and the liquid crystal device substrate 32 are bonded together, the inner area of the sealing layer 36 is depressurized to inject the liquid crystal 37. After the liquid crystal 37 is sealed in, the liquid crystal injection hole 38 is sealed with a sealant 39.

The sealing layer 36 is made of epoxy resin or various UV-curable resins, and the gap material blended with it is made of cylindrical or spherical plastics or glass fiber with a diameter of approximately 2 μm to 6 μm. The liquid crystal 37 is made of well-known TN (Twisted Nematic) liquid crystal or the like. Furthermore, if a polymer-dispersed liquid crystal, in which the liquid crystal is dispersed as minute particles in a polymer, is used, alignment films and polarizers are not required, thereby providing a liquid crystal device with high light utilization efficiency.

In this embodiment of the liquid crystal device 30, the counter substrate 31 is smaller than the liquid crystal device substrate 32, and the liquid crystal device substrate 32 is attached to the counter substrate 31 with its peripheral portion extending beyond the outer periphery. Therefore, the data line drive circuit 50 and the scanning line drive circuit 60 are positioned further outward than the outer periphery of the counter substrate 31, preventing degradation of the alignment film (e.g., polyimide) and the liquid crystal 37 due to DC components from the peripheral drive circuits. Furthermore, the liquid crystal device substrate 32 is formed with numerous external input/output terminals 40 in an area outside the counter substrate 31 for electrical connection to an external IC. These terminals are connected to a flexible printed circuit board or the like by wire bonding, ACF (Anisotropic Conductive Film) crimping, or other methods.

Furthermore, as shown in FIG. 18 , by forming microlenses 80 in a matrix on the opposing substrate 31 side corresponding to each pixel electrode 14 formed on the liquid crystal device substrate 32, incident light can be focused onto the pixel aperture region of the pixel electrode 14, significantly improving contrast and brightness. Furthermore, because the microlenses 80 focus the incident light, it is possible to prevent oblique light from reaching the channel region 1c and LDD regions (or offset regions) 1d and 1e of the pixel TFT 91. A first light-shielding film 7 is provided on the liquid crystal device substrate 32 to prevent light focused by the microlenses from reaching the channel region 1c and LDD regions (or offset regions) 1d and 1e of the pixel TFT 91, even if the light reflected by the back surface of the liquid crystal device substrate 32 is reflected. Therefore, the TFT characteristics are not affected by the intense light focused by the microlenses, and a liquid crystal device can be provided that provides bright, high-quality image quality. Furthermore, when using microlenses 80, light incident on the pixel aperture regions can be focused as shown by the dashed lines in FIG. 18 , making it possible to eliminate the black matrix 6 on the opposing substrate 31 side. While the microlenses 80 in FIG. 18 are provided on the opposing electrode 33 side of the opposing substrate 31, they may be provided on the opposite side of the opposing substrate 31 from the opposing electrode 33 side to focus light onto the liquid crystal device substrate 32 on which the pixel TFTs are formed. This has the advantage of making cell gap adjustment easier than when the microlenses are provided on the opposing electrode 33 side. Furthermore, as shown in FIG. 18 , microlenses 80 made of resin or the like are arranged closely together and a thin glass sheet is attached with an adhesive. Forming the opposing electrode 33 on the thin glass sheet facilitates cell gap adjustment and ensures sufficient light utilization efficiency.

(Method of Driving a Liquid Crystal Device) Figure 15 shows an example system configuration of a liquid crystal device 30 using the liquid crystal device substrates of Examples 1 to 8 described above. In the figure, 90 denotes pixels located at the intersections of scan lines 2 and data lines 3, which are arranged to intersect with each other. Each pixel 90 comprises a pixel electrode 14 made of an ITO film or the like, and a pixel TFT 91 that applies a voltage to the pixel electrode 14 in accordance with an image signal supplied to the data line 3. The gate electrodes of the pixel TFTs 91 in the same row are connected to the same scan line 2, and their drain regions 1b are connected to the corresponding pixel electrode 14. The source regions 1a of the pixel TFTs 91 in the same column are connected to the same data line 3. In this embodiment, the transistors constituting the data line driver circuit 50 and the scan line driver circuit 60 are so-called polysilicon TFTs, which use a polysilicon film as the semiconductor layer, just like the pixel TFTs 91. The transistors constituting the peripheral drive circuits (data line drive circuit 50, scan line drive circuit 60, etc.) are CMOS type TFTs, which can be formed on the same substrate as the pixel TFTs 91 using the same process.

In this embodiment, a shift register (hereinafter referred to as an X shift register) 51 that sequentially selects the data lines 3 is disposed on at least one outer side (the upper side in the figure) of the screen area 20 (the area in which pixels are arranged in a matrix), and an X buffer 53 is provided for amplifying the output signal of the X shift register 51. Furthermore, a shift register (hereinafter referred to as a Y shift register) 61 that sequentially selects and drives the scanning lines 2 is disposed on at least another side of the screen area 20. Furthermore, a Y buffer 63 is provided for amplifying the output signal of the Y shift register 61.

Furthermore, a sampling switch (TFT) 52 is provided at the other end of each data line 3. These sampling switches 52 are connected between image signal lines 54, 55, and 56 transmitting externally input image signals VID1 through VID3, for example, and are configured to be sequentially turned on/off by the sampling signal output from the X shift register 51. The X shift register 51 generates sampling signals X1, X2, X3, ..., Xn that sequentially select all data lines 3 during one horizontal scanning period based on an externally input clock signal CLX1, its inverted clock signal CLX2, and a start signal DX, and supplies these to the control terminals of the sampling switches 52. Meanwhile, the Y shift register 61 operates in synchronization with an externally input clock signal CLY1, its inverted clock signal CLY2, and a start signal DY, and sequentially drives each scanning line 2 Y1, Y2, ..., Ym.

(Explanation of Projection Display Device) Figure 17 shows an example of the configuration of a liquid crystal projector as an example of a projection display device that uses the liquid crystal device of the above embodiment as a light valve.

In FIG. 17, reference numeral 370 denotes a light source such as a halogen lamp, 371 denotes a parabolic mirror, 372 denotes a heat ray cut filter, 373, 375, and 376 denote blue-reflecting, green-reflecting, and red-reflecting dichroic mirrors, respectively, 374 and 377 denote reflecting mirrors, 378, 379, and 380 denote light valves formed from the liquid crystal device of the above-described embodiment, and 383 denotes a dichroic prism.

In the liquid crystal projector of this embodiment, white light emitted from light source 370 is condensed by parabolic mirror 371 and passes through heat-cut filter 372, blocking infrared rays, allowing only visible light to enter the dichroic mirror system. Then, blue-reflecting dichroic mirror 373 first reflects blue light (wavelengths of approximately 500 nm or less) while transmitting other light (yellow light). The reflected blue light is then redirected by reflecting mirror 374 and enters blue modulation light valve 378.

Meanwhile, the light transmitted through the blue-reflecting dichroic mirror 373 is incident on the green-reflecting dichroic mirror 375, which reflects green light (wavelengths of approximately 500 to 600 nm) and transmits the other light, i.e., red light (wavelengths of approximately 600 nm or longer).

The green light reflected by dichroic mirror 375 enters green modulation light valve 379. The red light transmitted through dichroic mirror 375 is redirected by reflecting mirrors 376 and 377 and enters red modulation light valve 380.

Light valves 378, 379, and 380 are driven by blue, green, and red primary color signals, respectively, supplied from an image signal processing circuit (not shown). The light incident on each light valve is modulated by the respective light valve and then combined by dichroic prism 383. Dichroic prism 383 is formed so that red reflecting surface 381 and blue reflecting surface 382 are perpendicular to each other. The color image combined by dichroic prism 383 is then enlarged and projected onto a screen by projection lens 384 for display.

By using a liquid crystal device incorporating the present invention, light-induced leakage current in the pixel TFTs 91 is minimized, enabling the liquid crystal projector using the liquid crystal device as a light valve to display high-contrast images. Furthermore, because the liquid crystal device has excellent light resistance, even if a bright light source 370 is used or a polarizing beam splitter is installed in the optical path between the light source 370 and the light valves 378, 379, and 380 to convert the polarization and improve light utilization efficiency, image degradation such as optical crosstalk does not occur. Therefore, a bright liquid crystal projector can be realized. Furthermore, because light reflected from the back surface of the liquid crystal device substrate is virtually negligible, there is no need to attach a polarizing plate or film with an anti-reflection coating to the output side of the liquid crystal device, as in the past, thereby reducing costs.

As shown in FIG. 17 , the present invention is particularly advantageous when using a three-element light valve and dichroic prism corresponding to red, green, and blue. For example, light reflected by dichroic mirror 274 passes through light valve 378 and is combined by dichroic prism 383. In this case, the light incident on light valve 378 is modulated by 90 degrees before entering the projection lens. However, there is a possibility that a small amount of light incident on light valve 378 may leak and enter light valve 380 on the opposite side. Therefore, taking light valve 380 as an example, not only is light reflected by dichroic mirror 377 incident from the incident direction (direction L in the drawing), but a portion of the light transmitted through light valve 378 may also pass through dichroic prism 382 and enter light valve 380. Furthermore, when light reflected by dichroic mirror 377 passes through light valve 380 and enters dichroic prism 382, it may be slightly reflected (specularly reflected) by dichroic prism 383 and re-enter light valve 380. Thus, the light valve experiences significant light incidence from the incident side and from the opposite side. Even in such cases, as shown in the above-described embodiment, the present invention forms light-shielding layers above and below pixel TFT 91 to prevent light from entering from both the incident side and the side opposite the incident side. Furthermore, the black matrix 6 on the opposing substrate 31 is formed larger than the first light-shielding film 7 to prevent light reflected from the surface of first light-shielding film 7 from entering the channel region 1c and LDD regions (or offset regions) 1d and 1e of pixel TFT 91. Therefore, the channel region 1c and LDD regions (or offset regions) 1d and 1e are shielded from light both from the incident side and the side opposite the incident direction (the back surface). Therefore, the leakage current of the TFT due to light can be significantly reduced.

Industrial Application Field As described above in detail, the liquid crystal device substrate described in claim 1 prevents light from entering the channel region and the junctions between the channel region and the source/drain regions by using the first light-shielding film for light from above and the second light-shielding film for light from below, thereby reducing light-induced leakage current in TFTs. Therefore, this invention makes it possible to manufacture high-performance active matrix liquid crystal device substrates, for example. Furthermore, liquid crystal device substrates incorporating this invention are ideal for liquid crystal displays, projectors, and the like.

───────────────────────────────────────────────────── (Note) This publication is based on the publication published internationally by the International Bureau of Patents (WIPO). The effect of the international publication of the Japanese patent application (Japanese utility model registration application) related to this publication arises pursuant to Article 184-10, Paragraph 1 of the Patent Act (Article 48-13, Paragraph 2 of the Utility Model Act) and is unrelated to this publication.

Claims (21)

[Claims] 1. A liquid crystal device substrate having a substrate on which a plurality of data lines are formed, a plurality of scanning lines intersecting the plurality of data lines, a plurality of thin-film transistors connected to the plurality of data lines and the plurality of scanning lines, and a plurality of pixel electrodes connected to the plurality of thin-film transistors, characterized in that a first light-shielding film is formed at least below the channel region of the thin-film transistor and the junction between the channel region and the source/drain region, and a second light-shielding film is formed above the junction between the channel region and the source/drain region. 2. The liquid crystal device substrate according to claim 1, wherein the first light-shielding film is a metal film selected from the group consisting of a tungsten film, a titanium film, a chromium film, a tantalum film, and a molybdenum film, or an alloy film. 3. The liquid crystal device substrate according to claim 1 or 2, wherein the first wiring extending from the first light-shielding film is electrically connected to a constant potential line outside the pixel screen area. 4. The liquid crystal device substrate according to any one of claims 1 to 3, wherein the first wiring extending from the first light-shielding film is formed below and along the scanning lines. 5. The liquid crystal device substrate according to any one of claims 1 to 4, wherein the line width of the first wiring extending from the first light-shielding film is narrower than the line width of the scanning line formed above it. 6. The liquid crystal device substrate according to claim 5, wherein the wiring extending from the first light-shielding film is covered by the scanning line formed above it. 7. The liquid crystal device substrate according to any one of claims 1 to 4, wherein a capacitance line for adding additional capacitance to the pixel is formed in the same layer as the scan line and extends parallel to the scan line, and a second wiring extending from the first light-shielding film is formed below the capacitance line. 8. The liquid crystal device substrate according to any one of claims 1 to 7, wherein the third wiring extending from the first light-shielding film is formed below and along the data line. 9. The liquid crystal device substrate according to any one of claims 1 to 8, wherein the data lines also serve as the second light-shielding film and are made of a metal film selected from the group consisting of an aluminum film, a tungsten film, a titanium film, a chromium film, a tantalum film, and a molybdenum film, or an alloy film thereof. 10. The liquid crystal device substrate according to any one of claims 1 to 9, wherein the line width of the third wiring extending from the first light-shielding film is formed to be narrower than the line width of the data line. 11. The liquid crystal device substrate according to any one of claims 1 to 10, wherein the channel region and junctions between the channel region and the source/drain regions are disposed below the data lines, and a first light-shielding film provided below the channel region and junctions between the channel region and the source/drain regions is covered by the data lines at least at the channel region and the junctions between the channel region and the source/drain regions. 12. The substrate for a liquid crystal device according to any one of claims 1 to 11, wherein an LDD (lightly doped drain) region is formed at a junction between the channel region and the source/drain regions. 13. The liquid crystal device substrate according to any one of claims 1 to 11, wherein an offset region is formed at a junction between the channel region and the source/drain regions. 14. The liquid crystal device substrate according to any one of claims 1 to 13, wherein the scan lines are made of a metal film selected from the group consisting of tungsten film, titanium film, chromium film, tantalum film, and molybdenum film, or a metal alloy film. 15. The liquid crystal device substrate according to any one of claims 1 to 13, wherein the minimum distance L1 from the side surface of the first light-shielding film to the channel region is 0.2 μm≦L1≦4 μm. 16. The liquid crystal device substrate according to any one of claims 9 to 15, wherein a minimum distance L2 from a side surface of the second light-shielding film to the first light-shielding film satisfies the relationship 0.2 μm≦L2. 17. A liquid crystal device comprising: a liquid crystal device substrate according to any one of claims 1 to 16; and a counter substrate having a counter electrode, disposed at a predetermined distance; and liquid crystal sealed in the gap between the liquid crystal device substrate and the counter substrate. 18. The liquid crystal device according to claim 17, wherein a third light-shielding film is formed on the opposing substrate. 19. The liquid crystal device according to claim 17 or 18, wherein the third light-shielding film is formed so as to cover at least the first light-shielding film. 20. The liquid crystal device according to any one of claims 17 to 19, wherein microlenses are formed in a matrix on the opposing substrate in correspondence with each of the plurality of pixel electrodes formed on the liquid crystal display substrate. 21. A projection display device comprising: a light source; a liquid crystal device having a configuration as defined in any one of claims 17 to 20 that modulates light from the light source and transmits or reflects the light; and projection optical means that condenses the light modulated by the liquid crystal device and projects it in an enlarged form.