JPS6345865A - Floating gate type mos semiconductor device - Google Patents

Abstract

PURPOSE:To ensure excellent workability in the manufacturing of a control gate electrode and floating gate electrode by a method wherein the floating gate electrode is formed on the sides of the control gate electrode with the intermediary of an insulating film. CONSTITUTION:A gate oxide film 2 is grown on a P-type silicon substrate 1. A step follows wherein a polycrystalline silicon film is formed to be a control gate electrode 3. Next, a silicon oxide film 4 is grown on the surface of the control gate electrode 3. A second polycrystalline silicon layer 5A is then deposited by vapor growth, after which the entire surface is subjected to anisotropic ion etching. After a silicon oxide film is grown to cover the entire surface, arsenic is diffused for the formation of N<+> diffusion layers 7 to serve as source.drain. Finally, an aluminum wiring is built after contact holes are provided in the control gate electrode 3 and N<+> diffusion layers 7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a floating gate type MO3 semiconductor device.

[Conventional technology]

Conventionally, this type of floating gate type MOS semiconductor device has a gate oxide film 2, a control gate electrode 3 made of polycrystalline silicon, a silicon oxide film 4, and a control gate electrode 3 made of polycrystalline silicon on a P-type semiconductor substrate 1, as shown in FIG. It has a structure in which floating gate electrodes 5 are sequentially stacked.

Next, a method of manufacturing this conventional floating gate type MO3 semiconductor device will be explained with reference to FIGS. 5(a) to 5(d).

First, as shown in FIG. 5(a), a gate oxide film 2 is formed on a P-type silicon substrate 1, and then a first polycrystalline silicon layer 3A is deposited on this gate oxide film 2. Subsequently, the entire surface of the first polycrystalline silicon layer 3A is oxidized to form a silicon oxide film 4. Subsequently, a second layer is formed on this silicon oxide film 4.
A polycrystalline silicon layer 5A is deposited. Next, a mask 9 made of a desired 7 photoresist is formed on this second polycrystalline silicon layer 5A using a normal photolithography technique.
form.

Next, as shown in FIG. 5(b), the second polycrystalline silicon layer 5A, silicon oxide WA4. Then, the first polycrystalline silicon layer 3A is sequentially etched to form a floating gate electrode 5 and a control gate electrode 3 made of polycrystalline silicon on a self-aligned line.

Next, as shown in FIG. 5C, after removing the mask 9, the entire surface is oxidized in a high temperature oxygen atmosphere, and a silicon oxide film 4 is formed to cover the control gate electrode 3 and the floating gate electrode 5.
Grow A.

Next, as shown in FIG. 5(d), in order to form the source and drain of the MOS transistor, As ions are implanted at 70 keV and at a dose of lXl015 cm-2 to form an N+ type scattering layer 7. After that, normal MOS
The floating gate type MO3 semiconductor device shown in FIG. 4 is completed according to the transistor manufacturing method.

[Problem that the invention seeks to solve]

As mentioned above, in order to manufacture a conventional floating gate type MO3 semiconductor device, a silicon oxide film and two polycrystalline silicon layers are sequentially etched, and therefore, high etching accuracy is required. However, current etching techniques tend to cause undercuts, and when dry etching is used, it is necessary to change the reaction gas, resulting in poor processability and complicated processes. Furthermore, compared to normal MO3 semiconductor devices, floating gate MO8 semiconductor devices have larger steps, so it is difficult to flatten the glabellar film, which causes disconnection in the metal wiring formed on the surface, reducing reliability. There are also points.

An object of the present invention is to provide a floating gate type MO3 semiconductor device in which the floating gate electrode and the control gate electrode have good workability, the glabellar film can be easily flattened, and the reliability is high.

[Means for solving problems]

The floating gate type MO3 semiconductor device of the present invention includes a gate insulating film formed on a -conductivity type semiconductor substrate, a control gate electrode formed on the gate insulating film, and an insulating film formed on the surface of the control gate electrode. and a floating gate electrode formed on a side surface of the control gate electrode with the insulating film interposed therebetween.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the invention.

In FIG. 1, a control gate electrode 3 made of polycrystalline silicon is formed on the surface of a P-type silicon substrate 1 with a gate oxide film 2 interposed therebetween. And this control gate electrode 3
A floating gate electrode 5 made of polycrystalline silicon is formed on the side surface of the control gate electrode 3 with a silicon oxide film 4 formed so as to cover it. In addition, in Figure 1, 6
Reference numeral 7 indicates a phosphosilicate glass film as a glabellar film, and 7 indicates an N+ type scattering layer 8 forming a source/drain, which is an aluminum wiring.

In the first embodiment configured as described above, since the floating gate electrode 5 is formed on the side surface of the control gate electrode 3 via the silicon oxide film 4, the control gate electrode 3 and the floating gate electrode 5 are has good workability and can be easily formed. Moreover, since the step difference in the floating gate electrode 5 portion does not become large as in the conventional case, the occurrence of disconnection in the wiring formed on the upper surface is almost eliminated.

Next, a manufacturing method of the first embodiment of the present invention will be described with reference to the drawings.

FIGS. 3(a) to 3(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 3(a), a P-type silicon substrate 1 with a surface index (100) and an impurity concentration l A gate oxide film 2 is grown.Next, a first polycrystalline silicon film with a thickness of approximately 4000 layers, which will become the control gate electrode 3, is formed by a normal vapor phase growth method.This polycrystalline silicon film is The first polycrystalline silicon film is converted into N type by thermal diffusion of phosphorus.The first polycrystalline silicon film is then patterned to form a control gate electrode 3.

Next, as shown in FIG. 3(b), oxidation is performed in a high temperature oxygen atmosphere to grow a silicon oxide film 4 on the surface of the control gate electrode 3.

Next, as shown in FIG. 3(C), second polycrystalline silicon is deposited to a thickness of about 3,500 layers over the entire surface by vapor phase growth. Phosphorous may or may not be introduced into this polycrystalline silicon.

Next, as shown in 31st ffi (d), the entire surface is etched by an anisotropic ion etching method. By this etching, a floating gate electrode 5 made of polycrystalline silicon is left on the side surface of the control gate electrode 3, and the surface of the silicon oxide film 4 is exposed in other parts.

Next, as shown in FIG. 3(e), after growing a silicon oxide film on the entire surface in a high-temperature oxygen atmosphere, arsenic is introduced by ion implantation to form an N+ type scattered layer 7 that will become the source and drain. Form.

Hereafter, the entire surface is flattened with a phosphosilicate glass film with good reflow properties according to the usual manufacturing method of MOS type semiconductor devices,
A contact hole is formed on the control gate electrode 3 and the N+ type scattered layer 7 by a normal patterning technique, followed by depositing 1.0 μm of aluminum, and then buttering is performed.
By forming aluminum wiring, the floating gate type MO3 semiconductor device shown in FIG. 1 is completed.

FIG. 2 is a sectional view of a second embodiment of the present invention, which differs from FIG. 1 in that the floating gate electrode 5 is formed only on one side of the control gate electrode 3. FIG. This second
To manufacture this embodiment, one of the floating gate electrodes 5 formed in FIG. 3(d) may be removed by photolithography.

In the embodiment of the bookcase 2 configured in this way, the M.O.
3. The current supply capability β of the semiconductor device can be increased.

That is, in the first embodiment shown in FIG. 1, if the same voltage (for example, 3V) is applied to the control gate electrode 3 and the drain consisting of one N++ diffusion layer 7 to form a channel, the other N1 diffusion layer 7 Since arsenic as an impurity is not introduced into the region of the P-type silicon substrate 1 adjacent to the source 7 and below the floating gate electrode 5, it functions as a resistance region. For this reason, the current supply capacity β of the MO3 semiconductor device is
decreases. On the other hand, in the second embodiment shown in FIG. 2, since the floating gate electrode 5 on the source side is not formed, the above-mentioned resistance region is not formed, and the current supply capability β is improved accordingly. It becomes what it is.

〔Effect of the invention〕

As explained above, the present invention forms a floating gate electrode on the side surface of a control gate electrode with an insulating film interposed therebetween.
This has the effect that the control gate electrode and the floating gate electrode can be formed with good workability, and that the interlayer film can be easily flattened. Therefore, a highly reliable floating gate MO3 semiconductor device without disconnection occurring in the wiring on the interlayer film can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a first embodiment of the invention, FIG. 2 is a sectional view of a second embodiment of the invention, and FIGS. 3(a) to 3(e) are sectional views of a first embodiment of the invention. A cross-sectional view of a semiconductor chip shown in the order of steps to explain an example manufacturing method, FIG. 4 is a cross-sectional view of a conventional floating gate type MOS semiconductor device, and FIGS. 5(a) to (d)
1A and 1B are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method of an example of a conventional floating gate type MO3 semiconductor device. 1...P-type silicon substrate, 2...gate oxide film, 3
... Control gate electrode, 4,4A... Silicon oxide film, 5... Floating gate electrode, 6... Phosphorsilicate glass film, hand Ir! gJ $2yl $3 times

Claims (1)

[Claims] a gate insulating film formed on a semiconductor substrate of one conductivity type;
A control gate electrode formed on the gate insulating film, an insulating film formed to cover the control gate electrode, and a floating gate electrode formed on a side surface of the control gate electrode with the insulating film interposed therebetween. A floating gate MOS semiconductor device characterized by: