JPS6337403B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a new configuration of a master control register of a programmable controller (hereinafter referred to as PC).

Some program storage type PCs used for sequence control are equipped with a master control function to enable efficient program creation.

The sequence ladder diagram of FIG. 1 is a suitable example of using this master control function, and FIG. 5 shows a program in which the sequence of FIG. 1 is assembled using this master control function.

The master control function refers to the master control set command (this is
The MCS instruction (denoted as MCS instruction) sets the master control register in a state that stores a specific condition, so that instructions input after this is set are included in the sequence under the specified condition, and the master control reset instruction (denoted as MCS instruction) This is a function that resets the master control register when an MCR instruction (expressed as an MCR instruction) is given. This is shown in Figures 1 and 5.
This will be explained using figures.

In Figure 1, the symbols 0.0, 0.1, 0, 3, etc. indicate elements that function as relays with normally open contacts, and the symbols 0.2, 2.3, etc. indicate normally closed elements. Indicates an element that has the function of a relay with contacts, and those marked with symbols such as 8.1 and 9.0 indicate auxiliary relays, indicators, timers, and other arbitrary output elements.

In the column representing the type of command in Fig. 5, the symbol R represents a command word that means the beginning of logic or intermediate storage of operation results in the case of an element having the function of a relay with a normally open contact, and A represents a logical product. , O represents a command word meaning logical sum, AN represents a command word meaning negated logical product, W represents a command word meaning output element,
RN represents a command word that means the beginning of logic or intermediate storage of calculation results in the case of an element having the function of a relay with normally closed contacts. In addition, MCS and
It was previously mentioned that MCR represents the master control set and master control reset commands, respectively. Operating elements such as keys for issuing these commands are provided on a panel (not shown) of the sequence controller, and the operator creates a program while operating these keys. That is, in the case of the sequence shown in Fig. 1, as understood from Fig. 5, the operator presses the keys R, 0.0, A, 0.1, O, 0.3, AN, 0.2.
If you operate in this order, the program will be assembled up to point A in Figure 1. At point A, there is a branch in the program. Therefore, the operator issues a master control set command using the MCS key, gives the condition that programming starts from a branch point, and then operates the R key 0.4 to reach point B. There is also a branch in the program at point B. Then key again
Give master control set command by MCS. After operating the key MCS, operate the key R, which means the beginning of logic, the key 1.0, and the key W, which means the output element, and the key 8.1.
Reach the point. When the key R is operated under the conditions in which the master control set command is given, the program returns to point B. The master control set instruction sets the master control register to provide such conditions.
Afterwards, the operation progresses and after operating key 8.6, press the key
Manipulating the MCR returns the program to the starting point (more on this later). So key R,
When 0.0, A, 0.1, O, 0.3, AN, and 0.2 are operated, the controller returns to point A again, and then reaches the final key operation, the key MCR, as shown in FIG.

When a controller has a master control function, it is possible to efficiently program programs as described above, and the number of program steps can be reduced compared to a controller that does not have this function.

However, even in the case of FIG.
Notice that steps 2 through 27 are the same as steps 0 through 5. In other words, when programming a sequence diagram like the one shown in Figure 1,
If you reset the master control register with the MCR instruction, you will need to program the master control register conditions again from the beginning even if you want to create another interlock with the same conditions.

The reason for this is that the conventional master control register circuit had a configuration as shown in FIG.

In FIG. 3, 1 is a flip-flop used as a master control register;
4 and 6 are logic gates, 2 is an arithmetic unit that performs an operation according to the instruction word, and 5 is a register (flip-flop) that stores the operation result. Master control register 1 is reset by signal H immediately after power is turned on or when an MCR instruction is executed. The input information A designated by the number in each command word is subjected to a logical operation in the arithmetic unit 2 with the signal E of the register 5 which is the result signal of the previous arithmetic operation, and is input to the AND gate 4. This signal is logically ANDed with signal C, which is the information of master control register 1, by AND gate 4, and then latched into operation result storage register 5 by signal G. When setting the interlock condition in register 1 or updating the contents, the information stored in register 5 is latched into register 1 by signal F generated when the MCS instruction is executed.

For example, when executing the program shown in FIG. 5, the contents of the master control register 1 and the operation result storage register 5 are O at first, so the signal C is "1" and the signal E is "0". When the state of contact 0.0 is input to the arithmetic unit 2 as input information A, "1" is set in the register 5 via the logic gate 4 if the contact 0.0 is "1" (on). Next, when the state of contact 0.1 is input to the calculator 2 as input information A, the state of contact 0.1 becomes "1".
(ON), the AND condition is satisfied with "1" in register 5, and signal B becomes "1", so "1" is set in register 5 again. Next, even if the state of contact 0.2 is input to the arithmetic unit 2 as input information A, "1" is set in the register 5 again because it is an OR instruction. When the state of contact 0.3 is input to computing unit 2 as input information A, the contact
If the state of 0.3 is “0”, “1” is written to register 5.
is set, and when the state of contact 0.3 is "1", register 5 is set to "0". next
Signal F is applied by the MCS instruction, and the contents of register 5 are inverted and set in register 1. If the contents of register 5 are "1", register 1 is set to "0", so signal C remains "1", and the following program execution becomes valid. On the other hand, when the contents of register 5 are "0", register 1 is set to "1", so signal C becomes O and signal D of logic gate 4 becomes "0" regardless of the state of signal B. ” and
Register 5 remains set to "0".
That is, if register 1 is set to "1", the previous conditions are not satisfied, so register 5 is set to "0" regardless of the following conditions. However, the state of this register 1 is rewritten by the next MCS instruction, and is also reset by the MCR instruction. In this way, master control register 1 was rewritten with the MCS instruction or reset with the MCR instruction, so even if you wanted to obtain an interlock with the same conditions, you had to program the master control register conditions from the beginning again. It is. In order to avoid this, it was necessary to rewrite the sequence as shown in Fig. 2 to a new sequence using auxiliary relay 20.0 and create a program as shown in Fig. 6.

The purpose of this invention is to reset the master control registers at once by the master control reset (MCR) instruction.
It is an object of the present invention to provide a master control register circuit for a programmable sequence controller in which only the conditions of the immediately preceding master control set (MCS) command are reset and sequence programs can be efficiently performed.

In this invention, the master control register is composed of a shift register into which new conditions are sequentially input for each master control set instruction (MCS), and the outputs from each stage of this shift register are combined and output from the arithmetic unit. The transfer of the operation results to the operation result storage register is controlled, and each master control reset (MCR) instruction resets only the conditions of the immediately preceding master control set (MCS) instruction.

FIG. 4 shows an embodiment of the invention.

Reference numeral 11 denotes a master control register using a shift register, and output groups taken out from each stage of this register 11 enter an AND gate 14 through an inverter gate group 13. On the other hand, the input information A is logically operated with the content E of the operation result storage register 15 by the arithmetic unit 12, and is ANDed with the signal C, which is the AND signal of the output group of the master control register 11, by the AND gate 17, and the operation result is It is latched at 15. Furthermore, this content E is connected to the lowest bit position of the master control register 11 via an inverter gate 16.

In such a configuration, all bits of the master control register 11 are reset immediately after power is turned on or by a "clear all bits of the master control register command" (this is called a CLRM command). All bits of this master control register are logically ANDed by the AND gate 14, so if at least one of these bits has a logic value of "1", the signal C, which is the output signal of the AND gate 14, becomes a logic product. Value “0”
becomes. On the other hand, the input information A is subjected to logical operation processing by the arithmetic unit 12 with the signal E, which is the result of the previous calculations, and is passed through the AND gate 17 to the register 15.
is latched to.

When the MCS instruction is executed, the output signal E of register 15
is latched to the lowest stage of the register 11 via the inverter gate 16, and the contents of the master control register are shifted upward one bit at a time as shown below. In addition, in the MCR instruction, as shown in the figure, a logical value "0" is entered at the top position of register 11,
The bits are shifted downward one bit at a time in the following order.

In a master control register circuit having such a structure, there is no need to rewrite the sequence as shown in FIG. 2, and programming can be performed efficiently as shown in FIG. 7. That is, in FIG. 7, branch points A, B,
The state of D is stored in the third, second, and first stages of the register 11, respectively. If the state of branch point A is "0", "1" is written to register 11, so signal C becomes "0" and register 5 remains set to "0".
Therefore, the states of branch points B and D are also "0",
“1” is written in the lower three stages of the register 11.
On the other hand, the states of branch points A and B are "1", but since contact 1.3 is "0" (off), branch point D
If only the state of register 1 is "0", register 1
Only the bottom row of 1 becomes "1". Then, when the register 11 is shifted by the MCS instruction in step 21 and the lowest ``1'' is removed, control in subsequent steps is performed based on the states of branch points A and B. Similarly, the MCR instruction in step 25 shifts the state of branch point B stored in the bottom row of register 11 to disappear, and the state of branch point B stored in the bottom row of register 11 is shifted to disappear.
From then on, the program is executed based only on the state of branch point A.

Furthermore, the master control register circuit shown in Fig. 4 can be easily used as a master control register as shown in Fig. 3, since the contents of the master control register 11 can be reset all at once by using the CLRM instruction as described above. Can be used.

Note that even if the master control register circuit shown in Figure 4 has a logical configuration using hardware,
It can also be realized by an interpreter method using a micro central processing unit.

As can be understood from the above description, according to the present invention, the master control function, which is one of the functions provided in a programmable controller, is provided by a multi-stage shift register. Sequences that require these conditions can be programmed efficiently and without the need to rewrite the sequence, such as by using a new auxiliary relay.

[Brief explanation of the drawing]

FIG. 1 shows an example of a sequence suitable for using the master control function, and FIG. 2 shows an example of a sequence suitable for using the master control function, and FIG. 3 shows a conventional master control register circuit, FIG. 4 shows an embodiment of the present invention, and FIG. 5 shows the master control register circuit in FIG. 3. A diagram showing how to give instructions when programming the sequence shown in Figure 1 with a programmable sequence controller that uses a control register circuit. Figure 6 shows the case where the sequence shown in Figure 2 is programmed using the same sequence controller as in Figure 5. FIG. 7 is a diagram showing how to give instructions when programming the sequence shown in FIG. 1 with a programmable sequence controller using the master control register circuit according to the present invention as shown in FIG. be. 11: Shift register, 12: Arithmetic unit, 13:
Inverter gate, 14: AND gate, 15:
Operation result storage register, 16: inverter gate, 17: AND gate.

Claims (1)

[Claims] 1 A calculation result storage register that temporarily stores calculation results by a program based on a ladder diagram, etc.;
It consists of an arithmetic unit that calculates the contents of the operation result storage register and information input by the next instruction, and a shift register, and each time a master control set instruction is added, the contents of the operation result storage register at that time are updated. A master control register which sequentially shifts and stores the contents of the operation result storage register and which erases the stored contents of the operation result storage register by shifting the contents in the opposite direction to the time of storage each time a master control reset command is applied; and the master control register. A master control register circuit comprising a logic control circuit for storing an AND output of all bits of the logical output of the arithmetic unit and the arithmetic result output of the arithmetic unit in the arithmetic result storage register.